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Power Circuits:
Voltage Regulation:
The voltage regulation circuit provides a steady, stable power supply to the rest of the
board regardless of changes to the load current or supply voltage. The circuit is set up to
take an input voltage of over 5V. When the switch is closed, the input voltage is sent to
pin 1 of NJM78L05A, the 5V regulator, to provide a steady 5V supply on the VCC line,
output at pin 2. The output from pin 2 of the 5-volt regulator is also sent to pin 1 of
ZR78L033C, a 3.3V regulator, to provide a steady 3.3-volt supply on pin 2. Capacitors
around the voltage regulators help to steady and filter the input signal. From pin 2 of the
5-volt regulator, VCC is connected to the processor on pins 20, 21, 40, 49, 61, 69, 80, 89,
100, 120, 129, 140, 149, and 160, to the network chip on pins 1, 4, 27, 47, 59, 60, 76, and
77, and to the Flash ROM on pins 14, 42, and 28. VCC is also connected to the
undervoltage-sensing circuit on pin 2, to the SIMM on pins 10, 30, and 39, to the LED on
pin 1, to OSC_66_SE1129, the oscillator, on pin 1, to 74LS161, the 4-bit counter, on pins
1 and 7, the critical interrupt circuit at pin 4, the manual reset circuit at pin 4, and the
bypass capacitor banks.
Undervoltage reset:
The undervoltage circuit provides an active-low reset signal to the processor whenever
the voltage power supply falls below 5.0 volts. The MC34064P-5 Undervoltage Sensing
Circuit is specifically designed for use as a reset controller in microprocessor-based
systems. This circuit was chosen due to its low cost, small package, and built-in
hysteresis to prevent unnecessary or erratic reset operation. The MC34064P-5
undervoltage-sensing chip provides the actual reset signal. A pull-up resistor ensures that
the undervoltage-sensing circuit does not produce a false reset signal and a capacitor
between the reset signal and ground adds a controllable time-delay to the circuit. The
reset signal is output on pin 1 of the chip. This reset signal is used as input to the
processor on pin 91, the edge connector on pin 35, the 28F640J5 Intel Flash ROM on pin
55, and to the network chip on pin 53.
Power Indicator:
A light emitting diode, LED, is connected in series with a resistor between VCC and
ground. The resistor reduces the voltage, which reduces heat produced by the LED, thus
extending its usability, and reduces the chance of its destruction in case of a voltage
spike. This LED will provide a visual indicator of the board's power status. When the
LED is illuminated, the board is receiving 5 volts of power. If the LED ceases to
illuminate power is not within acceptable standards.
Clock Circuit:
The clock circuit is based around OSC_66_SE1129, a 40 MHz crystal oscillator. VCC is
input to pin 1 of the oscillator from pin 2 of NJM78L05A, the 5-volt regulator. The wave
output from pin 5 of the oscillator is connected to input pin 2 of 74LS161, a 4-bit counter.
The counter also requires VCC as input to pins 1 and 7. The counter changes the wave
from the oscillator into a cleaner signal for use in the circuit. The 'cleaner' signal is
necessary to meet the requirements of the board's components. The result is a 40 MHz
system clock and a clock signal at half that speed for use in the serial port and timer
clock. The serial port and timer clock require a clock speed that is half the system clock
as specified in their datasheets. The 1st bit output from the counter, from pin 14, is the
system clock. The system clock is input to the 403GCX PowerPC Processor at pin 22
and to the edge connector at pin 33. The 2nd bit output from pin 13 of the counter drives
the serial clock and timer clock. The serial clock is input to the processor at pin 26. The
timer clock is input to the processor at pin 25, the DP83902AV Network chip at pins 69
and 40, and the edge connector at pin 34.
Reset/Interrupt:
Manual Reset/Reset:
The manual reset circuit is designed using the MAX811. The MAX811 has an activelow reset output, which is guaranteed to be in the correct state for input from VCC down
to 1 volt. This chip was chosen because the reset signal is guaranteed be asserted if the
supplied power is reduced from acceptable standards. This reset signal is sent before
power drops below the minimum necessary for the system ICs. The automatic reset
conditions have small limits, thereby reducing the chance of spurious resets. If the reset
circuit must be valid down to 0 volts, a resistor may be necessary to prevent stray current
from reaching the processor or other ICs. This is because when VCC is less than 1 volt
the reset circuit becomes an open circuit, and ICs could drift to unspecified voltages. The
reset circuit will also enable the user to reset the board at will. A manual single-pole,
single-throw, SPST, switch (normally closed) provides an input to pin 3 of the reset chip.
When the manual switch is pressed, the chip outputs a debounced active-low reset signal
to pin 2. This signal is input to the PowerPC 403GCX processor at pin 91, the edge
connector on pin 35, the 28F640J5 Intel Flash ROM on pin 55, and to the network chip
on pin 53. The manual reset signal is on the same lines as the undervoltage reset, as they
have the same result and functionality.
Manual Interrupt/Interrupt:
The manual interrupt circuit is designed using the MAX6816. The MAX6818 was
chosen due to its undervoltage lockout circuitry, which ensures that the outputs are in the
correct state following power-up, and the specification that any change to input must be
stable for 40ms prior to the output changing. This specification reduces the number of
unnecessary interrupts due to voltage inconsistencies. The specifications also state that
overvoltage clamping diodes will protect against voltages as high as 25 volts. The
manual interrupt circuit allows the user to abort the processor's current operation at will.
A manual single throw, single pole switch, SPST, (normally closed) provides an input to
pin 2 of the debouncing chip. VCC is provided through pin 4 of the chip. When the
manual switch is pressed, the chip will output a debounced, active-low critical interrupt
signal to pin 3. This critical interrupt signal is input to pin 36 of the processor and to pin
36 of the edge connector.
Processor:
Address bus signals A6-A29 are connected from pins 92-99, 103-110, 112-119 of the
processor to pins 67-90 of the edge connector. These address lines contain a valid
address during the read/write cycles from/to SRAM, ROM, or a peripheral device.
Address lines A6-A25 are also connected to pins 2-5, 8-13, 43, 45-50, and 52-54 of the
Flash ROM. Additionally, lines A6-A15 are connected to the SIMM through pins 14-19
and 28-29, and 31-32. Address lines A0-A3 are not necessary because only one of the 32
storage attribute regions are being utilized. Since the storage attributes are the same
everywhere in the 128MB region, only A4 is needed. From the processor address lines
A4-A5 and A30-A31 are devoted to SRAM, ROM and peripheral signals and are directly
connected to an external bus master. These four lines carry the Write Byte Enable
(WBE) signals. When the processor is the bus master, these four outputs select the active
byte(s) in memory during a memory write. When the processor is not the bus master,
WBE0:1 are used as inputs for bank register selection and WBE2:3 are used as the
A30:A31 inputs for byte selection and page crossing detection. Bank registers are used
to configure the properties of banks, including device width, timings, size, etc.; this
programming must be completed to access external memory hardware. For this board,
the external memory is the Flash ROM and SIMM. From the processor, pins 122 and
123 carry the WBE0:1 (A4 and A5) signals to pins 37 and 51 of the Flash ROM. These
same signals are also connected to the edge connector on pins 91-92 and to the SIMM
through pins 12-13. Signals WBE2:3 are connected from processor pins 124-125 to the
edge connector, pins 65-66, these signals do not need to be connected to the Flash ROM
or SIMM because address lines A30-A31 are not utilized.
Data bus signals D0-D15 are transmitted from processor pins 42-48, 51-58, and 62 to
network chip pins 12-23 and 28-31. These data lines are also connected to the edge
connector through pins 1-16, to the Flash ROM through pins 16-19, 24-27, 30-33, and
38-41, and to the DRAM SIMM through pins 2, 4, 6, 8, 20, 22, 24, 26, 49, 51, 53, 55, 57,
61, 63, and 65. Data bus signals D0-D15 carry data that is being transmitted to a device
compatible with halfword size, for example, the Flash ROM. Data signals D16-D31 are
transmitted from processor pins 63-68, 71-79, and 82 to pins 17-32 of the edge connector
and to pins 3, 5, 7, 9, 21, 23, 25, 27, 50, 52, 54, 56, 58, 60, 62, and 64 of the SIMM. The
edge connector and DRAM SIMM receive the entire data bus signal, A0-A31, from the
processor.
There are several connections between the processor and network chip. Among these are
the input signals transmitted from the network chip; INT0, an interrupt signal, DMAR0,
an external request for a DMA transfer on channel 0, Ready, a signal used to insert a wait
state into bus transactions, and HoldReq which indicates that the external master bus has
relinquished control. There are also signal outputs from the processor to the network
chip; EOT0/TC0 is an end of transfer signal/terminal count signal on channel 0 and
HoldAck, which is zero when the processor has control of the bus. DMAA0 is an
input/output signal that indicates when a transaction is taking place between the processor
and the network chip. The connection details and signal operation are detailed in the next
section.
The edge connector is designed to allow expansion and error detection. Due to these
operations, there are several connections between the processor and edge connector.
Many of the signals mentioned above are routed to the edge connector; HoldAck and
HoldReq are on pins 50 and 93, respectively, DMAA0, pin96, DMAR0, pin 95, and
Ready is on pin 49. Connections also include the processor control signals BUSERR and
ERROR.
Network Interface:
The network interface is handled by DP83902AV, a networking chip, and CCM9052, a
twisted-pair interface (TPI) connection, an RJ45 connector. The networking chip
provides Ethernet protocol through pins 54-57 and 61-62 to pins 1-2, 4-5, and 7-8 of the
TPI. Signals TXO+ and TXO- of the network chip are twisted pair transmit outputs
resistively combined external to the chip to provide a differential output signal with
equalizations to compensate for intersymbol interference (ISI). RXI+ and RXI- of the
network chip are twisted pair receive input signals that feed a differential amplifier,
which passes valid data to the ENDEC module. The network chip also has several
connections to the processor. INT0 in an interrupt signal from pin 5 of the network chip
to pin 31 of the processor, this interrupt may be programmed to be edge-triggered or level
triggered and may be active high or active low. Pin 38 from the network chip carries
signal DMAR0, an external request for a DMA transfer on channel 0, to the processor pin
2. DMAA0 is an input/output signal from pin 32 of the network chip to pin 156 of the
processor, this signal is a channel 0 acknowledge signal and has an active level when a
transaction is taking place between the processor and a peripheral, in this case, the
network chip. EOT0 is an input to the network chip pin 6 from input/output pin 128 of
the processor. EOT0/TC0 is an end of transfer signal or terminal count signal on channel
0. When used as TC0, logic 0 indicates the completion of a DMA transfer. Pin 43 of the
network chip sends the Ready signal to pin 13 of the processor. The Ready signal is used
to insert a wait state into bus transactions; this signal can be synchronous or
asynchronous. Pins 45 and 46 carry the HoldAck and HoldReq signals, respectively;
these connect to pins 14 and 134 of the processor. HoldAck is an output pin for the
processor and an input pin to the network chip. The signal is logic 1 when the processor
relinquishes its external bus to an external bus master, in this case the network chip.
After the processor regains control of the bus, logic 0 is output. Alternatively, HoldReq
is an input to the processor and an output from the network chip. An external bus master,
the network chip, may request the processor bus by placing logic 1 on this pin, the
external bus master relinquishes control by deasserting HoldReq. Data bus signals D0D15 are transmitted from network chip pins 12-23 and 28-31 to processor pins 42-48, 5158, and 62. These data lines are also connected to the edge connector through pins 1-16,
to the Flash ROM through pins 16-19, 24-27, 30-33, and 38-41, and to the SIMM through
pins 2, 4, 6, 8, 20, 22, 24, 26, 49, 51, 53, 55, 57, 61, 63, and 65. Pins 2, 3, 26, 39, 49, 58,
63, 64, 75, and 82 of the network chip are connected to ground; the remainder of the pins
are not used in this design.
Memory:
DRAM SIMM:
System RAM is contained on a 72-pin 16 MB DRAM SIMM. Dynamic random access
memory, DRAM, allows quick access to data in memory.
In addition to the address and data bus signals already mentioned, there are other
connections between the processor and the SIMM. CAS0, CAS1, CAS2, and CAS3 are
the column address selects for bytes 0 through 3 for all of the DRAM banks. These
signals are routed from processor pins 142-145 to pins 40-42 of the DRAM SIMM. The
CAS signals are also connected to the edge connector through pins 44-47. Chip select
signals CS4-CS7 are routed from processor pins 146-148 and 151 to SIMM pins 33-34
and 44-45. These signals determine which memory bank of the SRAM is accessed.
CS4-CS7 are also routed to pins 40-43 of the edge connector. The last connection from
the processor to the SIMM is the DRAM write enable signal, DRAMWE, which indicates
that the write operation is enabled for all DRAM banks. This signal is routed from
processor pin 138 to the SIMM pin 47; this signal is also reflected on the edge connector
pin 48. The remainder of the pins on the SIMM are ground, pins 1, 39, and 72, or have
not been utilized in this design.
Flash ROM:
The system ROM is to be installed on a 4MB Flash chip. A 4MB chip was chosen
because it is large enough to store an image of Linux. Linux was chosen as the operating
system because it is compact and contains all desired operational capabilities.
In addition to the address and data bus signals from the processor, the chip select signal,
CS0, is connected from processor pin 155 to the Flash ROM pin 1. This signal is also
shown at the edge connector, pin 64.
The Flash ROM is programmed through the 403GCX PowerPC processor utilizing a
JTAG connector.
JTAG:
The JTAG will be used to initially program the processor in order for it to have the
capability to program the Flash ROM. The signals TDO, TDI, TMS, and TCK are
connected from processor pins 6-8 and 16 to pins 51-54 of the edge connector. The
JTAG will be connected to the edge connector in order to access these four signals
necessary for programming the processor and Flash ROM. The TDO line carries the test
data out signal, TDI is the test data in signal, TMS is the test mode select signal, and
TCK is the test mode select line.
Board Monitoring/Expandability:
A 96-pin edge connector was added to the board to enable monitoring of signals when the
board is in use, thus facilitating troubleshooting. The connector will also allow increased
functionality. Due to this feature, several signals are routed directly from the processor to
the edge connector and not to any other components on the board. Among these signals
are three chip selects. Signals CS1-CS3 are routed from processor pins 152-154 to the
edge connector pins 61-63. Additionally, signals WBE0-WBE3, OE, and R/W are
routed from pins 122-127 to pins 55-60. As explained in the processor section, WBE0WBE3 are also address lines, A4-A5 and A30-A31, respectively. The OE signal is the
output enable line and the R/W signal is the read, not write, line.
The processor control signals, CInt, Halt, Ready, BusReq, BusErr, and Error are also
routed from the processor to the edge connector. CInt is the critical interrupt line. Halt is
an external signal used to stop the processor on an external event. Activating this signal
causes the processor to become architecturally frozen. Architecturally frozen means that
normal instruction execution stops and all architecture resources of the processor can be
accessed and altered via the JTAG port. Once Halt is deactivated, normal execution will
continue. The Ready signal input allows an external source to control the SRAM wait
timing, meaning, an external device can generate and insert wait states. The BusReq
signal is active while HoldAck is active and the processor has a bus operation pending
and needs to regain control of the bus. BusErr indicates errors during burst cycles or wait
cycles. All other connections to the edge connector are explained elsewhere.