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8. The Basic Bistable Memory Devices
PART III SEQUENTIAL LOGIC
All logic circuits can be classified as either combinational or sequential. A circuit is classified
as combinational if it has the property that its outputs' signals are determined totally by its
external inputs' signals acting at this moment. A circuit is classified as sequential if it has the
property that its outputs are determined not only by its external inputs but also by the past
history of the circuit.
In this part we will analyze the basic bistable memory devices, additional bistable memory devices, popular circuits of sequential logic. The top of the part will be solving of the
problem of sequential logic design.
8. THE BASIC BISTABLE MEMORY DEVICES
Memory or storage devices are fundamental sequential components used in the design of
sequential logic circuits. A sequential logic device that has two and only two stable output
states is called a bistable element, or a latch, or a flip-flop. In this chapter we will present the
most basic forms of the sequential logic circuits.
8.1. Elementary Memory Cell
The elementary bistable memory cell is the main part of every latch and flip-flop. In this section
we will analyze an electrical and logic diagrams of elementary bistable memory cell, operation
and properties of the cell.
+EC
The elementary bistable memory cell is formed by
two stages of resistance amplifier with crossed feedback
R2
R1
from their outputs to inputs.
VT2
VT1
There are two and only two stable states of this
circuit. Let transistor VT1 is ON. Low level on the
collector of this transistor keeps transistor VT2 OFF. High
level on the collector of this transistor keeps VT1 ON. This
state – VT1 ON and VT2 OFF – is stable and it lasts until
the power supply voltage EC is ON.
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8. The Basic Bistable Memory Devices
Another stable state, when VT2 is ON, is possible. In this case low level on the collector
VT2 keeps OFF transistor VT1, and high level on the collector of VT1 keeps ON transistor
VT2. This state – VT1 OFF and VT2 ON – is stable and it lasts until the power supply voltage
EC is ON.
The state when both transistors are OFF is impossible, because the high level on the
collector of the cut off transistor would open another transistor immediately.
The state when both transistors are ON is possible but unstable. Let us analyze this state.
The state is possible when both transistors are slightly open and collector currents of both
transistors are similar. If current of transistor VT1 for a moment increases (the reason can be
even a chaotic motion of electrons), the collector voltage of this transistor decreases. This
slightly closes transistor VT2 and its collector voltage decreases. This still opens the transistor
VT1: its collector current increases and collector voltage decreases. In this manner an
avalanche process develops and its result is one of the two stable states, when VT1 is ON and
VT2 is OFF. With equal probability another stable state could be set.
The collector voltages of transistors of elementary bistable memory cell are always
inverted one with respect to another: there is a high level on the collector of shut off transistor,
and a low level on the collector of saturated transistor.
A circuit with two stable states is memory cell for storage of one bit
of information.
1
According an electrical diagram of elementary bistable memory cell
its logic diagram can be drawn. The cell consists from two inverters with
crossed feedback from their outputs' to their inputs.
1
A bistable memory cell is not a trigger, because its outputs – the
collectors of the transistors – are linked up with inputs – the bases of
transistors. The outputs and inputs of triggers must be separated.
8.2. The Basic S-R Latches
In this section we will analyze two basic S-R latches: the electric and logic diagrams, the
properties, and the methods of description.
+EC
R2
R1
OUT1
IN1
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VT1
VT2
VT3
VT4
OUT2
IN2
8.2.1. An Electric and Logic Diagrams
A bistable memory cell becomes a trigger when the
separated outputs and inputs are formed. It can be
done by adding to each transistor of a bistable
memory cell another parallel transistor with collector load in common with previous transistor.
One input of trigger is named as set input,
8. The Basic Bistable Memory Devices
another – as reset input. The first letters of inputs names gave a name to the trigger: S-R trigger
or S-R latch. The basic S-R latch is the simplest form of sequential circuit. This sequential
device can retain its output state of 0 or 1 as long as power supply voltage is applied.
The outputs of latch are named as Q and Q. The main output Q is the output that repeats
the logic signal in input S. The latch is set, when Q  1, and the latch is reset or cleared, when
Q  0.
Now we will analyze an operating of the circuit. Let input IN1 of the circuit is S input,
and input IN2 is R input. Let S  1, and R  0. The high level in input IN1 saturates VT1 and its
collector voltage (voltage in output OUT1) is low irrespective of state of VT2. This low level
cuts off VT3. A low level in input R (input IN2) cuts off VT4. It means that there is a high level
on the collectors of VT3 and VT4, high level in the input of VT2, and high level in the output
OUT2. So the combination of input signals S  1, and R  0 sets ON VT1 and VT2, sets OFF
VT3 and VT4, and sets high level in output OUT2 and low level in output OUT1. According a
definition output OUT2 is the main or direct output Q, because it repeats the logic signal in
input S. Output OUT1 is inverted output Q.
Example 8.1
Explain, which transistors are ON, and which are OFF when the input signals are as follows: S  0, R  1.
Now we will analyze a situation when after combination SR  10 the input signals S  0,
and R  0 appear. Combination SR  10 sets up VT1 and VT2 in state ON, and VT3 and VT4 in
state OFF. S  0 closes VT1, but collector voltage off VT1 and VT2 (level in output) Q remains
low, because VT2 is saturated by high level on the collectors of VT3 and VT4. So the combination of input signals SR  00 after combination SR  10 does not change the state of SR latch:
the latch remains set with Q  1 and Q  0.
Example 8.2
Explain, which transistors are ON, and which are OFF when the input signals SR  00 appear after
combination SR  01.
We can make a conclusion that there are two active and one passive combination of input
signals. Combination SR  10 is active, it sets the S-R latch (sets Q  1 and Q  0). Combination SR  01 is active, it resets the S-R latch (sets Q  0 and Q  1). Combination SR  00 is
passive, it does not change the state of SR latch.
The last combination of input signals SR  11 ought to be discussed. S  1 and R  1 in
inputs saturate VT1 and VT4 and set low level in both outputs: Q  0 and Q  0. It means that
trigger does not correspond to its definition: a trigger is a device with two and only two stable
states in two inverted one with respect to another outputs. Moreover: when input signals
SR  11 are changed by input signals SR  00, the state of the trigger is indefinite, the trigger
can be set or reset with equal reliability. Therefore the combination of input signals SR  11 is
not normally allowed for S-R latch.
Now we will draw a logic diagram of S-R latch. We can see that S-R latch is made from
two cross-coupled NOR gates. It is basic S-R latch, or S-R NOR latch, or basic NOR latch. The
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8. The Basic Bistable Memory Devices
main or direct output Q of this latch is an output of the gate with input R,
inverted output Q is an output of the gate with input S.
It is necessary to remember, that logic circuit's operation does not
depend on the technology of logic gate: TTL, ECL, MOS TL, CMOS TL
Q or another. Technology determines only parameters of logic circuit – an
1
operation speed, a power consumed, and so on, but not operation of the
R
circuit. The circuits of logic gates fabricated with various technologies
were analyzed in part two of this book. In this third part we will analyze
logic circuits on gates level, which are represented by their logic diagrams, and more complicated logic circuits, represented by function diagrams. Function diagrams are made from function
units, such as latches, flip-flops and other devices, implementing definite logic function.
Graphic symbol of a basic S-R latch (a basic NOR latch) is shown on the
Q picture. NOR gates are basic – simple and cheap – gates in MOS and CMOS
S
Q TL families. The basic gates in TTL families are NAND gates. Applying
R
DeMorgan's theorem we can draw a logic diagram of basic latch from NAND
gates. It is an alternative form of S-R latch. This form of basic latch is often
Q
referred to as an basic SR latch, or basic S-R, or NAND latch. Both of
S

S-R latches are basic latches, but each circuit has a slightly different
characteristic. Remember that inputs of NAND latch are represented in
complemented or inverted form, that is, S and R, or S and R.
Logic 0 is the active signal in inputs of AND and NAND gates,
Q

that strictly determines output signal of these gates. Therefore 0 in input
R
S sets the latch and determines Q  1, 0 in input R resets the latch and
S
S
R
Q
1
S
R
determines Q  1. Combination SR  11 in inputs of a latch is a passive combination that does not change state of latch. Combination SR  00 is
Q normally not allowed for NAND latch combination, because it sets Q  Q  1.
Graphic symbol of a basic NAND latch is shown on the picture.
Q
Example 8.3
Explain, is it possible from input and output signals to distinguish between the box with NOR latch from the box
with NAND latch with inverters in inputs.
8.2.2. Analysis of Basic S-R Latches
The operation of basic S-R latch circuits is very important. If one understands the operation of
basic latch circuits, then more complex memory devices will be easy to understand, since their
operation is quite similar. For this reason, the analysis of S-R latch circuits will be presented in
very thorough manner. To investigate the properties of these latch circuits we will utilize the
following analysis tools: circuit delay model, characteristic equation, Karnaugh map, flow map,
state diagram, algorithm of operation, and timing diagram. The same analysis tools can be used
in design of sequential circuits.
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