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Design Review #1
ECE 6332: VLSI Design
Karen Joseph
Mehdi Kabir
Ashley Brinker
October 5, 2010
Project Description:
After speaking with Professor Calhoun and some research, our group was able to narrow
our interest to two main topics. One of them is to compare and contrast gate leakage techniques. In
our research, we came across several device-level solutions and circuit-level techniques that
minimize the gate leakage current. Since a lot of these techniques are well-developed, we wanted
to focus our project on comparing and contrasting the different techniques in terms of power and
their tradeoff with performance. These reduction techniques include MTCMOS design, high-k
transistors, dual-k transistors, using p-type domino instead of n-type domino, and dynamic Vth.
We, however, feel that a lot of research has already been done in this area and plan to talk to
Professor Calhoun to further develop this topic, if we do chose to work on this.
Another topic of interest was DIBL. Similar to our other topic of interest, we would
compare and contrast different leakage-reduction techniques. In particular, we would look at
different finFET designs and different doping techniques, such as halo doping, graded doping, retrograded doping, etc. Our main concern with this topic was simulation. We are not sure what
software or if we will be able to use spice models to model finFET or doping.
Some of us do not have prior experience with ocean, cadence simulation, or whatever
software we choose to model the circuits. Hence, one of our first goals (prior to the proposal)
would be to determine how we would simulate the circuit designs and familiarize ourselves with
the software. In addition, our topics need to be further developed to clearly state the metrics. We
also need to decide what variables we decide to change and what we decide to keep constant.
After the proposal, we would create a base case for the topic of interest to compare against.
This would clearly state the parameters of interest and those which we decide to keep constant.
After simulating and collecting data for the base case, we would determine the other different cases
to compare against. Depending on how the project goes, we can either go into detail on the existing
techniques or look to developing another.
Publication Summaries:
Yeo, Y., King, T., Hu, C. (April 2003). MOSFET gate leakage modeling and selection guide for
alternative gate dielectrics based on leakage considerations. IEEE Transactions on Electron Devices,
50(4).
This paper explores the effect of scaling down the oxide layer of the MOSFET on the gate
leakage current of the device and suggests a method for analyzing the effects of using alternative
dielectrics to reduce the leakage. Since gate leakage is a product of band-to-band tunneling, the
authors start out with a toy model estimation of the tunneling current. This estimation suggests
that as we decrease the oxide thickness, the gate leakage current will increase exponentially. That is
why the authors suggest using high-κ dielectric materials such as hafnium oxide (HfO2), aluminum
oxide (Al2O3) and silicon nitride (Si3N4), which have dielectric constants which are a magnitude
larger than the conventional silicon dioxide (SiO2). This allows the insulating layer to be thicker
than the conventional SiO2 layer but can still maintain the large capacitance needed as the device is
scaled. Using a new figure-of-merit based on insulator barrier height, dielectric constant and
effective mass of the tunneling electrons, the authors work out the minimum insulator thickness the
materials can be scaled to given a certain gate leakage current. According to their model, materials
such HfO2 and Al2O3 can be scaled down a magnitude smaller than SiO2, given a certain gate leakage
current.
Hisamoto, D., Lee, W. et al. (December 2000). FinFET—A self-aligned double-gate MOSFET scalable
to 20nm. IEEE Transactions on Electron Devices, 47(12).
As MOSFETs are scaled to smaller dimensions, many short-channel effects become more
and more pronounced. One such effect is the drain induced barrier lowering, or DIBL. In a regular
NMOS structure, n-type source and drain wells are placed on top of a p-type substrate, thus creating
a reverse-bias diode between the source-body and drain-body interfaces. Just like a reverse-biased
diode, when the voltage is increased to the device, the depletion region between the p-n interface
gets larger. In short channel devices, this depletion region of drain-body interface can expand into
the channel. The overall effect lowers the threshold voltage and thus increases the sub-threshold
leakage current.
In order to avoid this problem, the authors created a very thin (~10nm) fin structure
between the source and drain. Furthermore, the source, drain and the fin are placed on top of a
layer insulator rather than silicon substrate. To tightly control the threshold voltage, a layer of polySi is placed all around the fin (rather than just on top as in conventional MOSFETs). The authors
showed that as the fin thickness was scaled, the DIBL effect was effectively suppressed. This is
because the thin body of the fin structure prevents the depletion region from expanding too far into
the channel. Furthermore, the fin structure shows better transconductance than conventional
MOSFETs. This suggests that one can achieve better subthreshold swing using this structure than
conventional MOSFET structure.
Roy, K., Mukhopadhyay, S., Mahmoodi, H. (February 2003). Leakage Current Mechanisms and
Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceedings of the IEEE, Vol.
91, No. 2.
This paper explores both causes of leakage and leakage reduction techniques at the processand circuit-level. At the process level, leakage can be reduced by altering parameters such as the
doping profile and length, oxide thickness, junction depth, etc in the transistors. This paper
describes two such process level techniques, retrograde doping and halo doping. Retrograde doping
is used to improve short channel effects (SCE’s) and increase surface channel mobility by creating a
low surface channel concentration followed by a highly doped subsurface region. Halo doping is
another way to control the dependence of threshold voltage on channel length. For example for nchannel MOSFETs, more highly doped p-type regions are introduced near the two ends of the
channel will reduce the charge-sharing effects from the source and drain fields, therefore reducing
the width of the depletion region. Also, reducing the drain and source junction depletion region
width reduces DIBL.
At the circuit level, threshold voltage and leakage current of transistors can be controlled by
altering the voltages of different device terminals. This paper provides four major techniques for
leakage reductions; transistor stacking, multiple Vth, dynamic Vth, and supply voltage scaling. In
transistor stacking, the subthreshold leakage current flowing through the stack of series-connected
transistors reduces when more than one transistor in the stack is turned off. With multiple Vth
technologies, both high- and low-threshold transistors are provided on a single chip. The highthreshold transistors can suppress the subthreshold leakage current while the low-threshold
transistors are used to achieve high performance. Dynamic Vth technique reduces active leakage
power. This is done by dynamic adjustment of frequency through back-gate bias control. Finally,
supply voltage scaling reduces leakage since the subthreshold leakage due to DIBL decreases as the
supply voltage is scaled down.
Drazdziulis, M., Larsson, P. A Gate Leakage Reduction Strategy for Future CMOS Circuit. Department
of Computer Engineering, Chalmer University of Technology.
This paper investigates the tunneling mechanisms that induce various types of gate leakage
and how these different gate leakage currents contribute to the gate-leakage power consumption. It
then proposes a subthreshold leakage reduction approach that can be reduce the gate leakage
currents. This reduction approach is a self-controllable voltage-level (SVL) circuit. This circuit a
chain of diode-connected MOSFETs is placed between the external and virtual supply rails in
parallel with cut-off transistors in the upper and lower parts of the logic circuit. The voltages on the
virtual supply lines can be adjusted by selecting an appropriate number of diodes. Since Vgd will be
equal to the voltage drop across the diode chain, this is lower than Vdd so the reduced voltage drop
across the logic circuit will increase the threshold voltages of the transistors due to DIBL and body
effects and as a result the subthreshold leakage will be reduced. Also, the gate leakage current is
decreased.
R. Guindi and F. Najm, “Design Techniques for Gate-Leakage Reduction in CMOS Circuits,”
Proceedings of the Fourth International Symposium on Quality Electronic Design, p. 61, August 2426, 2003.
This paper discusses techniques to reduce oxide tunneling current in static CMOS circuits.
The variables that are considered in this paper are the applied bias, the transistor type, and the
transistor size. The three regions of operation, (strong inversion, off, and threshold), provide
distinct conditions for the channel of a MOS transistor. However, the gate-leakage current during
threshold and off is significantly less than its gate-leakage current during strong inversion. In their
analysis, they assess the gate-leakage current only during strong inversion and estimate PMOS gateleakage to be 10 times smaller than NMOS gate-leakage current. Since gate area is directly
proportional to the leakage current, their analysis looks at the leakage current for minimum-size
transistor technology.
As an example, the paper compares the NOR and NAND structure. In a NOR-gate, each
active NMOS will leak independent of the other NMOSes and are therefore, considered a ‘worstcase’ structure. A NAND structure of stacked NMOSes leaks less than a NOR structure of parallel
NMOSes. This insight can be used to compare different implementations of the same logic function.
The paper also assessed state-dependent leakage. For example, the leakiest state of a 2-input NAND
is (1,1). State-dependence looks at all the transistors together instead of individually. Statedependent leakage tables can be used for any logic gate to identify inputs that produce the least
leakage current. This way, if signal probabilities are known, the input signals can be assigned in a
way that favors the least leaky state. State-dependent leakage tables can also be used to find the
static standby state with the least gate-leakage. In conclusion, the paper suggests
recommendations for low power application but at the expense of slower circuits.
F. Hamzaoglu, M. Stan, “Circuit-level Techniques to Control Gate Leakag for Sub-100nm CMOS,”
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, August
12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566425].
This paper discusses gate-leakage reduction techniques for CMOS circuits for a single Vdd
and oxide thickness. The paper also discusses the different between gate current and gate leakage,
the current from the power supply due to oxide tunneling. Gate leakage is not zero, even when gate
current is zero and is the area of concern in reducing power consumption. One technique is to use
p-type domino instead of n-type domino. In the analysis, the paper provides a comparison between
an n-type OR gate and p-type AND gate (both with no stack) and between an n-type AND gate and a
p-type OR gate (both with stack). The gate leakage for NMOS is larger than that of a PMOS and this
technique results in a smaller total NMOS width. However, a p-type domino is more affected by
parasitic capacitances and will therefore result in a slightly slower circuit. The paper also compares
n-type and p-type gating for multi-threshold CMOS to control the leakage during sleep.