Download Adjustable Battery-Backup Supervisor for RAM

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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
FEATURES
D Supply Current of 40 µA (Max)
D Battery Supply Current of 100 nA (Max)
D Supply Voltage Supervision Range:
DESCRIPTION
The TPS3613-01 supervisory circuit monitors and controls
processor activity by providing backup-battery switchover
for data retention of CMOS RAM.
− Adjustable
− Other Versions Available on Request
Backup-Battery Voltage Can Exceed VDD
During power-on, reset (RESET and RESET) is asserted
when the supply voltage (VDD or VBAT) becomes higher
than 1.1 V.
D
D Power-On Reset Generator With Fixed 100-ms
Thereafter, the supply voltage supervisor monitors VDD at
the SENSE pin through external feedback resistors and
keeps reset active as long as SENSE remains below the
threshold voltage, VIT.
Reset Delay Time
D Active-High and Active-Low Reset Output
D Chip-Enable Gating: 3 ns (at VDD = 5 V) Max
D
D
An internal timer delays the release of the reset state to
ensure proper system reset. The delay time starts after
SENSE rises above the threshold voltage, VIT.
Propagation Delay
10-Pin MSOP Package
Temperature Range: −40°C to 85°C
When SENSE drops below VIT, reset becomes active
again.
APPLICATIONS
D Fax Machines
D Set-Top Boxes
D Advanced Voice Mail Systems
D Portable Battery-Powered Equipment
D Computer Equipment
D Advanced Modems
D Automotive Systems
D Portable Long-Time Monitoring Equipment
D Point-of-Sale Equipment
The TPS3613-01 is available in a 10-pin MSOP package
and is characterized for operation over a temperature
range of −40°C to +85°C.
Address
Decoder
Power
Supply
0.1 µF
CEIN
Rx
CEOUT
VDD
VBAT
CE
CMOS
RAM
VCC
Address Bus
Backup
Battery
uC
SENSE
Data Bus
TPS3613
MR
Manual
Reset
VOUT
GND
8
RESET
RESET
Ry
CE
CMOS
RAM
VCC
Real−
Time
Clock
VCC
8
16
Switchover
Capacitor
0.1 µF
VCC
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2000−2008, Texas Instruments Incorporated
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*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
PACKAGE INFORMATION
TA
DEVICE NAME
−40°C to +85°C
TPS3613−01DGSR†
† The DGSR passive indicates tape
and reel of 2500 parts.
MARKING
AFK
ordering information application specific versions
TPS361
3 − 01
DGS
R
NOMINAL VOLTAGE‡, VNOM
DEVICE NAME
Adjustable
TPS3613−01 DGS
‡ For other threshold voltages, contact the local TI sales office for
availability and lead-time.
Reel
Package
Nominal Supply Voltage
Functionality
Family
FUNCTION TABLE
SENSE > VIT
2
MR
CEIN
0
VDD > VBAT
0
VOUT
VBAT
RESET
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
RESET
CEOUT
0
1
DIS
VBAT
VBAT
0
1
DIS
0
1
DIS
VBAT
VDD
0
1
DIS
0
1
DIS
VDD
VDD
0
1
DIS
0
1
DIS
VDD
VDD
0
1
DIS
0
1
DIS
VDD
VDD
0
1
DIS
1
0
0
VDD
VDD
1
0
1
0
1
DIS
0
1
DIS
0
VDD
VDD
1
0
0
1
VDD
1
0
1
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
FUNCTIONAL SCHEMATIC
TPS3613
VBAT
+
_
Switch
Control
VOUT
VDD
R
MR
+
_
SENSE
RESET
Logic
+
Timer
Reference
Voltage
or 1.15 V
RESET
RESET
VOUT
CEIN
CEOUT
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
CEIN
5
I
Chip-enable input
CEOUT
6
O
Chip-enable output
GND
3
I
Ground
MR
4
I
Manual reset input
RESET
7
O
Active-high reset output
RESET
9
O
Active-low reset output
SENSE
8
I
Adjustable sense input, assumed to be connect to VDD throught feedback resistences. Call your local contacts
for other application connections.
VBAT
10
I
Backup-battery input
VDD
VOUT
2
I
Input supply voltage
1
O
Supply output
3
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
TIMING DIAGRAM
VDD
VDD
VBAT
1.1V
t
SENSE
VIT
VOUT
t
RESET
t
td
td
td
t
MR
td
t
NOTE: Shaded area in RESET is undefined.
4
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
detailed description
backup-battery switchover
supervisors do not connect VBAT to VOUT when
VBAT is greater than VDD. VBAT only connects to
VOUT (through a 15-Ω switch) when VDD falls
below VIT and VBAT is greater than VDD. When
VDD recovers, switchover is deferred either until
VDD crosses VBAT, or when VDD rises above the
reset threshold VIT. VOUT connects to VDD through
a 1-Ω (max) PMOS switch when VDD crosses the
reset threshold.
VDD − Normal Supply Voltage
In case of a brownout or power failure, it may be
necessary to preserve the contents of RAM. If a
backup battery is installed at VBAT, the device
automatically switches the connected RAM to
backup power when VDD fails. In order to allow the
backup battery (for example, 3.6-V lithium cells)
to have a higher voltage than VDD, these
VDD >VBAT
1
VDD >VIT
1
VOUT
VDD
1
0
0
1
VDD
VDD
0
0
VBAT
VDD − Mode
VIT Hysteresis
VBAT − Mode
VBSW Hysteresis
Undefined
VBAT − Backup-Battery Supply Voltage
Figure 1. VDD − VBAT Switchover
5
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
detailed description (continued)
chip-enable signal gating
The internal gating of chip-enable (CE) signals
prevents erroneous data from corrupting CMOS
RAM during an under-voltage condition. The
TPS3613 uses a series transmission gate from
CEIN to CEOUT. During normal operation (reset
not asserted), the CE transmission gate is
enabled and passes all CE transitions. When
reset is asserted, this path becomes disabled,
preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay
from CEIN to CEOUT enables the TPS3613
device to be used with most processors.
The CE transmission gate is disabled and CEIN is
in high impedance (disable mode) while reset is
asserted. During a power-down sequence when
VDD crosses the reset threshold, the CE
transmission gate is disabled and CEIN
immediately becomes high impedance if the
voltage at CEIN is high. If CEIN is low when reset
is asserted, the CE transmission gate is disabled
when CEIN goes high, or 15 µs after reset asserts,
whichever occurs first. This allows the current
write cycle to complete during power down. When
the CE transmission gate is enabled, the
impedance of CEIN appears as a resistor in series
with the load at CEOUT. The overall device
propagation delay through the CE transmission
gate depends on VOUT, the source impedance of
the drive connected to CEIN, and the load at
CEOUT. To achieve minimum propagation delay,
the capacitive load at CEOUT should be
minimized, and a low-output-impedance driver is
used.
In the disabled mode, the transmission gate is off
and an active pullup connects CEOUT to VOUT.
This pullup turns off when the transmission gate
is enabled.
CEIN
t
CEOUT
15 µs
t
RESET
t
Figure 2. Chip-Enable Timing
6
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
ABSOLUTE MAXIMUM RATINGS
OVER OPERATING FREE-AIR TEMPERATURE (unless otherwise noted)(1)
Supply voltage: VDD(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
MR and SENSE pins(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VDD + 0.3 V)
Continuous output current at VOUT: IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
All other pins, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . +260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation the device must not operate at 7 V for more than t = 1000h continuously.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ +25°C
POWER RATING
DGS
424 mW
DERATING FACTOR
ABOVE TA = +25°C
3.4 mW/°C
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
271 mW
220 mW
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VDD
Battery supply voltage, VBAT
Input voltage, VI
High-level input voltage, VIH
MIN
MAX
UNIT
1.65
5.5
V
1.5
5.5
V
VDD + 0.3
V
0
0.7 x VDD
Low-level input voltage, VIL
V
0.3 x VDD
V
Continuous output current at VOUT, IO
300
mA
Input transition rise and fall rate at MR, ∆t/∆V
100
ns/V
1
V/µs
Slew rate at VDD or Vbat
Operating free-air temperature range, TA
−40
+85
°C
7
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
ELECTRICAL CHARACTERISTICS
OVER RECOMMENDED OPERATING CONDITIONS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD − 0.2 V
IOH = −20 µA
IOH = −80 µA
IOH = −120 µA
IOH = −1 mA
VDD − 0.3 V
CEOUT
VDD = 1.8 V,
VDD = 3.3 V,
VDD = 5 V,
VOUT = 1.8 V,
Enable mode
CEIN = VOUT
VOUT = 3.3 V, IOH = −2 mA
VOUT = 5 V, IOH = −5 mA
VOUT − 0.3 V
CEOUT
Disable mode
VOUT = 3.3 V, IOH = −0.5 mA
VOUT − 0.4 V
RESET
High-level output voltage
RESET
RESET
CEOUT
VOL
Low-level output voltage
Enable mode
CEIN = 0 V
Power-up reset
voltage (see Note 1)
VOUT
Battery-backup mode
RDS(on)
VDD to VOUT on-resistance
VBAT to VOUT on-resistance
VIT
Negative-going input threshold voltage
(see Note 2)
Vhys
Hysteresis
IIH
IIL
High-level input current
II
Input current
IDD
VDD supply current
IBAT
VBAT supply current
VDD − 0.4 V
V
VOUT − 0.2 V
0.2
VOUT = 1.8 V, IOL = 1.0 mA
0.2
VOUT = 3.3 V, IOL = 2 mA
VOUT = 5 V, IOL = 5 mA
0.3
VDD > 1.1 V or VBAT > 1.1 V,
IOL = 20 µA
0.4
0.4
VDD – 200 mV
V
VBAT − 20 mV
VBAT – 113 mV
0.6
1
8
15
1.15
1.17
1.1 V < VIT < 1.65 V
12
VBSW (see Note 3)
VDD = 1.8 V
MR = 0.7 x VDD, VDD = 5 V
55
SENSE
VDD = 1.15 V
VOUT = VDD
VOUT = VBAT
VOUT = VDD
VOUT = VBAT
Disable mode,
−33
−76
−110
−255
−25
25
40
40
−0.1
Ω
V
mV
0.1
0.5
Ilkg
CEIN leakage current
VI < VDD
±1
Ci
Input capacitance
VI = 0 V to 5 V
5
(1) The lowest voltage at which RESET becomes active. tr,(VDD) ≥ 15 µs/V.
(2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals.
(3) For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT
8
V
VDD − 150 mV
1.13
VDD = 5 V
V
VDD – 50 mV
VDD = 5 V
VBAT = 3.3 V
MR = 0 V,
UNIT
VDD − 0.4 V
Sense
MR
MAX
IOL = 400 µA
IOL = 2 mA
IOL = 3 mA
VDD = 1.8 V,
VDD = 3.3 V,
VDD = 5 V,
IO = 8.5 mA,
VDD = 1.8 V, VBAT = 0 V
IO = 125 mA,
VDD = 3.3 V, VBAT = 0 V
IO = 200 mA,
VDD = 5 V,
VBAT = 0 V
IO = 0.5 mA,
VBAT = 1.5 V, VDD = 0 V
IO = 7.5 mA,
VBAT = 3.3 V, VDD = 0 V
Normal mode
Low-level input current
TYP
IOH = −400 µA
IOH = −2 mA
IOH = −3 mA
RESET
VOH
MIN
VDD = 1.8 V
VDD = 3.3 V,
VDD = 5 V,
µA
nA
µA
µA
µA
pF
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
TIMING REQUIREMENTS AT RL = 1 MΩ, CL = 50 PF, TA = −40°C TO +85°C
PARAMETER
tw
Pulse width
TEST CONDITIONS
SENSE
VIH = VIT + 0.2 V,
VIL = VIT − 0.2 V
MIN
TYP
MAX
UNIT
µs
6
SWITCHING CHARACTERISTICS AT RL = 1 MΩ, CL= 50 PF, TA = −40°C TO +85°C
PARAMETER
td
Delay time
tPLH
Propagation (delay) time,
low-to-high-level output
VSENSE ≥ VIT + 0.2 V,
MR ≥ 0.7 x VDD,
See timing diagram
50% RESET to 50% CEOUT
50% CEIN to 50% CEOUT,
CL = 50 pF only (see Note 5)
tPHL
Propagation (delay) time,
high-to-low-level output
SENSE to RESET
MR to RESET
Transition time
(1)
TEST CONDITIONS
VDD to VBAT
VOUT = VIT
VDD = 1.8 V
VDD = 3.3 V
VDD = 5 V
VIL = VIT − 0.2 V,
VIH = VIT + 0.2 V
VSENSE ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
VIH = VBAT + 0.2 V,
VIL = VBAT − 0.2 V,
VBAT < VIT
MIN
60
TYP
100
MAX
140
15
UNIT
ms
µs
5
15
1.6
5
1
3
2
5
0.1
1
ns
µs
µs
3
µs
Assured by design
9
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
rDS(on)
IDD
VIT
Static drain-source on-state resistance (VDD to VOUT)
vs Output current
3
Static drain-source on-state resistance (VBAT to VOUT)
vs Output current
4
Static drain-source on-state resistance (CEIN to CEOUT)
vs Input voltage at CEIN
5
Supply current
vs Supply voltage
6
Input threshold voltage at RESET
vs Free-air temperature
7
High-level output voltage at RESET
r DS(on)
10, 11, 12,
13
Low-level output voltage at RESET
vs Low-level output current
14, 15
Low-level output voltage at CEOUT
vs Low-level output current
16, 17
High-level output voltage at CEOUT
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VDD to VOUT)
vs
OUTPUT CURRENT
1000
VDD = 3.3 V
VBAT = GND
900
TA = 85°C
800
TA = 25°C
700
TA = 0°C
TA = −40°C
600
500
50
75
100
125
150
IO − Output Current − mA
Figure 3
10
175
200
− Static Drain-Source On-State Resistance − Ω
− Static Drain-Source On-State Resistance − m Ω
VOL
8, 9
vs High-level output current
r DS(on)
VOH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VBAT to VOUT)
vs
OUTPUT CURRENT
20
VBAT = 3.3 V
17.5
15
TA = 85°C
12.5
TA = 25°C
TA = 0°C
10
7.5
5
2.5
TA = −40°C
4.5
6.5
8.5
10.5
12.5
IO − Output Current − mA
Figure 4
14.5
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
30
40
35
I DD − Supply Current − µ A
TA = 25°C
30
25
20
TA = 0°C
15
TA = −40°C
10
20
VDD Mode
VBAT = GND
or
TA = 25°C
TA = 0°C
TA = 85°C
15
TA = −40°C
10
5
ICEOUT = 5 mA
VDD = 5 V
5
VBAT Mode
VBAT = 2.6 V
25
TA = 85°C
0
0
0
1
2
3
4
VI(CEIN) − Input Voltage at CEIN − V
5
0
1
2
3
4
VDD − Supply Voltage − V
5
6
Figure 6
Figure 5
INPUT THRESHOLD VOLTAGE AT RESET
vs
FREE-AIR TEMPERATURE
1.001
VIT − Input Threshold Voltage at RESET − V
rDS(on) − Static Drain Source On-State Resistance
(CEIN to CEOUT) − Ω
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(CEIN to CEOUT)
vs
INPUT VOLTAGE AT CEIN
1
0.999
0.998
0.997
0.996
0.995
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80
TA − Free-Air Temperature − °C
Figure 7
11
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
5.1
VDD = 5 V
VBAT = GND
VOH − High-Level Output Voltage at RESET − V
VOH − High-Level Output Voltage at RESET − V
6
5
TA = −40°C
TA = 25°C
4
TA = 0°C
3
2
TA = 85°C
1
0
−35
−30
−25
−20
−15
−10
−5
IOH − High-Level Output Current − mA
Expanded View
5
TA = −40°C
4.9
4.8
4.7
TA = 85°C
4.6
VDD = 5 V
VBAT = GND
4.5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0
0
IOH − High-Level Output Current − mA
Figure 9
Figure 8
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
3.35
V(CEIN)= 3.3 V
VDD = 5 V
Enable Mode
3
TA = −40°C
2.5
TA = 25°C
TA = 0°C
1.5
1
TA = 85°C
0.5
0
−150 −130 −110 −90 −70 −50 −30
−10
IOH − High-Level Output Current − mA
Figure 10
12
VOH − High-Level Output Voltage at CEOUT − V
VOH − High-Level Output Voltage at CEOUT − V
3.5
2
TA = 25°C
TA = 0°C
V(CEIN) = 3.3 V
VDD = 5 V
Expanded View
Enable Mode
3.30
TA = −40°C
3.25
TA = 25°C
TA = 0°C
TA = 85°C
3.20
3.15
3.10
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5
IOH − High-Level Output Current − mA
Figure 11
0
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3.5
3
VOH − High-Level Output Voltage at CEOUT − V
VOH − High-Level Output Voltage at CEOUT − V
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
TA = −40°C
2.5
TA = 25°C
TA = 0°C
2
1.5
TA = 85°C
1
Disable Mode
V(CEIN) = Open
VDD = 1.65 V
0.5
0
−4.5 −4 −3.5
−3 −2.5
−2 −1.5
−1
−0.5
0
V(CEIN) = Open
VDD = 1.65 V
3.4
3.3
TA = −40°C
3.2
TA = 25°C
TA = 0°C
3.1
TA = 85°C
3
2.9
2.8
2.7
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1
IOH − High-Level Output Current − mA
0
IOH − High-Level Output Current − mA
Figure 13
Figure 12
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
3.5
500
VOL − Low-Level Output Voltage at RESET − mV
VOL − Low-Level Output Voltage at RESET − V
Expanded View
Disable Mode
VDD = 3.3 V
VBAT = GND
3
2.5
TA = 0°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = −40°C
0.5
0
0
5
10
15
20
IOL − Low-Level Output Current − mA
Figure 14
25
Expanded View
TA = 85°C
VDD = 3.3 V
VBAT = GND
400
TA = 25°C
300
TA = 0°C
200
TA = −40°C
100
0
0
1
2
3
4
IOL − Low-Level Output Current − mA
5
Figure 15
13
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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
LOW-LEVEL OUTPUT CURRENT
VOL− Low-Level Output Voltage at CEOUT − mV
VOL− Low-Level Output Voltage at CEOUT − V
3.5
Enable Mode
V(CEIN) = GND
VDD = 5 V
3
2.5
TA = 85°C
2
TA = 25°C
TA = 0°C
1.5
TA = −40°C
1
0.5
V(CEIN) = GND
VDD = 5 V
Enable Mode
Expanded View
120
TA = 85°C
100
TA = 25°C
80
TA = 0°C
60
TA = −40°C
40
20
0
0
0
10 20 30 40 50 60 70 80 90
IOL − Low-Level Output Current − mA
Figure 16
14
140
100
0
1
2
3
4
IOL − Low-Level Output Current − mA
Figure 17
5
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3613-01DGS
ACTIVE
MSOP
DGS
10
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3613-01DGSG4
ACTIVE
MSOP
DGS
10
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3613-01DGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3613-01DGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS3613-01DGSR
Package Package Pins
Type Drawing
MSOP
DGS
10
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
5.3
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS3613-01DGSR
MSOP
DGS
10
2500
358.0
335.0
35.0
Pack Materials-Page 2
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