* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download Development OF PROTOTYPE Digital LLRF system at RRCAT
VHF omnidirectional range wikipedia , lookup
Oscilloscope wikipedia , lookup
Time-to-digital converter wikipedia , lookup
Television standards conversion wikipedia , lookup
Broadcast television systems wikipedia , lookup
Direction finding wikipedia , lookup
Opto-isolator wikipedia , lookup
Telecommunication wikipedia , lookup
Signal Corps (United States Army) wikipedia , lookup
Oscilloscope types wikipedia , lookup
Battle of the Beams wikipedia , lookup
Valve RF amplifier wikipedia , lookup
Tektronix analog oscilloscopes wikipedia , lookup
Cellular repeater wikipedia , lookup
Oscilloscope history wikipedia , lookup
Radio transmitter design wikipedia , lookup
Mixing console wikipedia , lookup
Analog-to-digital converter wikipedia , lookup
Wien bridge oscillator wikipedia , lookup
Interferometric synthetic-aperture radar wikipedia , lookup
Index of electronics articles wikipedia , lookup
Phase-locked loop wikipedia , lookup
Analog television wikipedia , lookup
Single-sideband modulation wikipedia , lookup
DEVELOPMENT OF PROTOTYPE DIGITAL LLRF SYSTEM AT RRCAT Nitesh Tiwari*, Pritam S. Bagduwal, Dheeraj Sharma, Shoubhik Chakraborty, Mahendra Lad, and P.R. Hannurkar Raja Ramanna Centre for Advanced Technology, Indore, India Abstract RF field is used in accelerator to accelerate the charge particles. The beam parameters depend highly on the stability of the RF field. Due to dynamic beam loading conditions the variations in RF parameters of accelerating structures needs to be controlled precisely, hence low level RF feedback control system plays vital role. Considering revolutionary development in the field of digital electronics and inherent advantages of digital systems, digital LLRF control system work was taken up. The digital LLRF system consists of two major units namely RF processing and digital processing. RF processing unit uses I/Q modulator for amplitude and phase control. This unit provides synchronized clock using 16 pre-scalar and also performs up conversion and down conversion for synchronized LO and IF generation respectively, along with required amplification and filtering. Digital processing unit takes down converted IF signal with appropriate sampling rate for I/Q detection. To extract the amplitude and phase information I/Q data is digitally filtered and processed using CORDIC algorithm in FPGA. I/Q modulator is used for controlling the amplitude and phase of RF field. Prototype development of digital LLRF control system for 325MHz, 650MHz is in progress. Digital LLRF system at 505 MHz has been installed in one RF station of Indus-2 RF system. In this paper development of prototype Digital LLRF system at RFSD, RRCAT and results are presented. INTRODUCTION Amplitude and phase of the RF fields inside the RF cavity should be kept stable under the required limits for proper operation of any particle accelerator. Low Level RF (LLRF) feed back loops are indispensable part of RF system of any particle accelerator. LLRF loops controls and maintenances the required amplitude and phase stability seen by the beam in the RF cavity. LLRF control system can either be conventional analog or digital. Digital System provides flexibility, easier vector sum, extensive diagnostic, advanced exceptions, good repeatability and reduced long time drift errors compared to analog system. Looking at the advantages of Digital system development Digital Low Level RF system, (DLLRF) for 325 MHz and 650MHz is also taken up along with 505.8MHz RF system. Block diagram of a typical DLLRF system is shown in the Figure 1. DLLRF system can broadly be split in to two parts. Figure 1: Typical Digital LLRF scheme. Purpose of front end RF signal processing is to generate the synchronized signal and down convert the RF to Intermediate Frequency (IF). This IF signal is than digitally processed and control signal is generated to control the amplitude and phase using analog I/Q modulator. In this paper we will describe about the both processing unit along with the results of prototype system. RF SIGNAL PROCESSING RF processing is required to make the RF signal compatible with digital hardware. RF processing involves amplitude and phase control of RF signal using I/Q modulator, down conversion of RF signal to IF using mixers and generation of the synchronized clock and LO signal for sampling frequency and IF generation respectively. I/Q Modulator In order to correct the amplitude and phase error in control loop a modulator is required to correct the amplitude and phase of the RF signal. Voltage controlled attenuator and voltage control phase shifter are common amplitude and phase corrector used in conventional feedback loops but this requires two separate correctors for amplitude and phase and their operating range is also limited. Instead I/Q modulator AD8345 is used to control the phase and amplitude of RF signal. Block diagram of I/Q modulator is shown in Figure 2. RF signal processing. Digital signal processing. Figure 2 Block Diagram of I/Q modulator ___________________________________________ *[email protected] AD8345 accurately splits the external LO signal into two quadrature components through the polyphase phase splitter network. This Inphase and Quadarture phase LO components are mixed with the baseband I and Q differential input signals. Finally, the outputs of the two mixers are combined in the output stage to provide 50 Ω output drive. Amplitude and phase of this output signal is governed by the differential base band I and Q signal. Down Conversion and synchronized Clock Generation. Direct digital processing of high frequency RF signal is not possible because of the limitation of available digital hardware. High frequency RF signal is down converted to intermediate frequency (IF). Large Q or small bandwidth of the RF cavity used in particle accelerators enables us to bring RF to IF without loosing any amplitude and phase information. On the basis of RF cavity bandwidth, controller algorithm and available hardware IF is chosen. For 325 MHz, 650 MHz and 505.8 MHz system cosen IF frequencies are 20.3 MHz, 40.6 MHz and 31.6 MHz respectively. Clock and RF signal should be synchronized with each other to ensure the proper amplitude and phase detection of RF signal. To achieve this synchronization clock and LO is derived from the RF signal it self. Scheme of down conversion and clock generation is shown in Figure 3 IF Amp. Out to ADC IF In LO In LPF Out to mixer 2 BPF Figure 4: Amplification and filtering scheme for LO and IF Low pass filter is used to remove harmonics ( Nxf IF ) in the out put of IF amplifier. Band pas filter is required at the out put of LO amplifier to remove harmonics and other sidebands. DIGITAL SIGNAL PROCESSING RF signal is brought down to IF where it can be processed digitally to detect the amplitude and phase information from IF and implement the feedback loops algorithm. Digital I/Q Detection Digital I/Q detection scheme is used to detect amplitude and phase information of RF from down converted IF signal. Samples of IF signal are taken 90⁰ apart and separation of consecutive samples gives I and Q component. This can be achieved by sampling the RF signal with a clock whose frequency is four times that of the RF signal. As shown in Figure 5. Figure 5: Digital IQ sample In general, the relation between sampling frequency and RF signal frequency for I/Q detection is Where, fs = sampling frequency. fRF = RF signal frequency Figure 3: Down conversion and clock generation scheme After separating the I and Q signals characterization of digital I Q detection is done and results are presented below in Figure 5 Amplification and filtering of RF signals Mixers are used for LO and IF signal generation due to higher insertion loss of mixers out input to the next stage becomes small and results in nonoptimized utilization of components. Therefore for optimum use of mixer 2 (of Figure 3) and ADC, amplification of LO and IF signal is required. Two RF power amplifiers at LO and IF are used to give this required amplification. Non linearity of these amplifiers introduces the harmonic in LO and IF signal which could lead to erroneous I Q detection. Implementation of proper filter is done remove this unwanted side band. Amplifier and the required kind of filter is shown in Figure 4 (a) (b) Figure 5: Detection of amplitude and phase modulated waveform using I/Q detection. In Figure 5 (a) pink waveform is amplitude modulated IF signal and green waveform is the digitally detected amplitude signal. Close correspondence between detected amplitude and envelope of IF is obtained. Purple waveform in Figure 5 (b) is the detected phase of sinusoidal phase modulated waveform. Input IF signal is sampled by the ADC at a rate of 25.3 MHz, 13.25 MHz and 32.5 MHz for 505.8, 325 and 650 MHz RF system respectively to give the ‘I’ and ‘Q’ components of the IF signal. Digital Controller Controller is used to generate the control signal for I/Q modulator after comparing the detected RF signal with set value. Controller is implemented in the vertex4 FPGA and one 100MSPS ADCs for I/Q detection and two 120MSPS DACs are used for generation of control signal. A typical controller flow diagram is shown in Figure 6. Figure 7: Digital rack in station 3 of Inuds-2 RF system. Amplitude and phase stability of better than ±0.5% and 1º has been successfully achieved. Results of amplitude and phase stability at 310 kV gap voltage is shown in Figure 8 Figure 6: Controller flow diagram. Digitally detected ‘I’ and ‘Q’ components of IF signal are converted in to the amplitude and phase using CORDIC algorithm. This amplitude and phase information is than compared with set amplitude and phase value and control amplitude and phase signals are generated. Control amplitude and phase signals are than converted in to I and Q format again by using CORDIC. This control I/Q signal through single to differential conversion is fed to I/Q modulator to control the amplitude and phase of main RF signal. Control algorithm is written in VHDL. DIGITAL LLRF RACK A prototype of 505.8 MHz Digital RF system has been developed. All the parts of Digital LLRF RF systems are assembled in two 19”, 3U sub racks. One of two unit is RF processing unit which has all the RF components like mixers, amplifiers, filters, circulators etc. In other 3U unit all digital components like FPGA board, single to differential converter, ADC and DAC are housed along with I/Q modulator. Photograph of DLLRF control rack installed in Inud-s2 is shown in Figure 7. Figure 8: Amplitude and phase stability of Inuds-2 DLLRF. With Digital LLRF system implemented in station 3 of Indus-2 RF system and since than machine is regularly being operated at 100mA 2.5 GeV. And phase stability of 0.8º and amplitude stability of With only slight modification in RF front end and clock generation same system can be used for 325 and 650 MHz as well. REFERENCE [1] Mahendra Lad, Nitesh Tiwari, Pritam S. Bagduwal and P. R. Hannurkar “Commissioning & Optimization of Indus-2 RF System for 2GeV/100mA” InPAC-11, IUAC New Delhi, Feb15-18, 2011. [2] Lawrence Doolittle, “Low-Level RF Control System Design and Architecture,” APAC, RRCAT, Indore, India, 2007. [3]Shoubhik Chakraborty*, Dheeraj Sharma, Pritam Singh Bagduwal, Nitesh Tiwari, Mahendra Lad, P.R. Hannurkar ,” I/Q Detection Scheme for Indus2 RF system”, HPRFM,2013