Download Power Consumption

Prélude
1
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Le Boléro de Maurice Ravel,
la recette originale d’une addiction.
En 1927, quand la très célèbre
danseuse Ida Rubinstein demanda une
pièce de ballet à Maurice Ravel, celui-ci
dut résoudre un formidable problème:
http://fr.wikipedia.org/wiki/Bol%C3%A9ro_(Ravel)
Comment créer et retenir l’attention
du public pendant 17 minutes sur une
musique de ballet?
Ida Rubinstein
Le tempo: 2 mesures répétées 169 fois.
La solution de Maurice Ravel est
devenue l’œuvre classique la plus
jouée au monde.
Parce qu’elle utilise un mécanisme
d’addiction implacable.
2
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
La mécanique d’un succès
Maurice Ravel propose d’abord un thème simple compris de tous.
Avant que le public ne se lasse, il propose une nouvelle variante, en
ajoutant un instrument. Il prend le soin de soutenir la musique par un
tempo particulièrement explicite.
Par ce tempo, le public comprend vite qu’une nouvelle variante va arriver
et en devine l’instant. Mieux, il apprend à l’attendre. Il l’attend sans se
rendre compte d’ailleurs que le volume augmente. Le public suit le rythme
et se refuse inconsciemment à envisager une fin, une fin pourtant
inéluctable.
L’orchestre s’époumone, quelques sons discordants et en quelques notes
la musique s’éteint.
18, c’est le nombre de variantes que le public a appris à attendre avec
impatience.
3
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Un succès qui ne peut être eternel
Mais la recette de ce succès contient sa fin.
Il n’est pas possible de répéter cette mécanique à l’infini.
La musique s’arrête, non pas par manque d’inspiration mais
parce qu’il n’est pas possible d’augmenter encore le volume…
4
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
La mécanique d’un succès
Maurice Ravel a utilisé une méthode simple qui se décompose en
quelques points clés:
• Proposer quelque chose de simple, facilement compréhensible.
• Anticiper un besoin de renouveau en proposant juste à temps une
variante plus attractive.
• Augmenter le volume pour satisfaire l’oreille.
• Utiliser une cadence rigoureuse pour créer l’attente et ne pas décevoir.
5
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
La loi de Moore ?
La microélectronique est liée à la loi de Moore.
Elle doit son succès à un mécanisme très similaire au Boléro de Ravel.
• Un thème simple, le circuit intégré, compris de tous.
• Un tempo implacable.
• De nouvelles fonctions offrant des variantes toujours plus attractives.
• Avec des performances toujours plus grandes.
• Et cela à un prix similaire.
La loi de Moore serait-elle en fait la loi de Maurice ?
6
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Un Soupir…
7
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Power and Energy Management
ECOFAC 2010
Yves Leduc
Texas Instruments France
Challenge de la conception low power
d’un point de vue industriel…
8
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
High Level Agenda
Bill
Heat
Consumption
Waste
9
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Power I$ a Concern
Sun “Black Box”
Systems:
Power consumption could be simply too much.
- Data centers spend twice the money:
1 to power the servers
1 to cool the server room
.. 100 MW
- Desk-top computers need fan
Fan is noisy
Reliability issue
.. 100 W
- Mobile phones cannot dissipate more than
.. W
10
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Power I$ a Concern
ICs:
Power consumption could be also too much.
- Some package needs heat sink or fan
- ICs could run hot and cannot accept new functionalities
- Die stacking is limited by power dissipation capability
- Current density could be too high for the wiring
11
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Power I$ a Concern
Home, office:
- Standby of household appliances
- Low profile cheap appliances in activity
waste our money… [ in silence ]
12
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Energy I$ a Concern
Portable systems:
It hurts.
- Mobile phones, portable computers, .. must be charged regularly
- Pacemakers need battery to be replaced
- Energy harvesting systems search for scarce energy
- Batteries are heavy, expensive, not reliable…
-…
13
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Energy I$ a Concern
- Standby of household appliances
- Low profile cheap appliances in activity
Abuse of precious resources all around the world.
14
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Energy I$ a Concern
Last but not least,
should be
be green.
green, of course
world MUST
Doc NASA
15
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
No Brute Force Solutions
Energy ?
Batteries.
Fuel cells.
Energy harvesting.
Little hope for a significant breakthrough soon.
They have a small 20% efficiency. 80% heat? Alas…
An ultra low power niche…
Heat Dissipation ?
Silicon carbid.
Fluidics to evacuate heat.
Running hot, the heat dissipation is more efficient.
Far to be in low cost high volume production.
Expensive! Limited efficiency! Dependability?
Power Consumption ?
Lower operating voltages.
Still no solution to lower voltages in the mV range without
speed degradation and good enough noise margin.
16
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Moore’s Law
We have to offer more applications to preserve our
business.
As our IC’s are at the limit of the power dissipation
or of the energy consumption, we MUST reduce them
to get a chance to add a new application.
There is no alternative.
17
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
A Realistic Solution: Energy Aware Design
Energy   Power  dt
Power Dissipation AND/OR Energy Consumption
could be too much.
In both cases, LIMITING the energy
consumed by the system is the solution.
It is all about EFFICIENCY.
18
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Tracking Efficiency Everywhere
Specifications,
Constraints,
Expectations,
Nice to have
…
Power Plant
Power Distribution
Voltage Conversion
External Voltage Regulation
PCB Routing
IC Package
losses
Internal Voltage Regulation
losses
IC Routing
losses
Modules
losses
Meaningful Results
losses
losses
19
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Room for Improvement Everywhere
Efficiency is a design care all along the supply chain
from the power plant to the expected output.
We will review a few area where designers are at work
and where innovation is needed.
CAUTION
WOMEN
WORK
MEN ATAT
WORK
20
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Power Distribution
There are a few ways to distribute
electrical power.
We tap power from
• Electrical outlet
• Primary / secondary battery
• Inductive coupling
• and a few others…
http://upload.wikimedia.org/wikipedia/commons/b/b5/New_York_utility_lines_in_1890.jpg
21
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Electrical Outlet
AC-DC Adapter:
transformer or high voltage electronics.
Wall wart power adapter
A small transformer, such as a plug-in « wall wart »" power adapter
commonly used for low-power consumer electronics devices, may be as low
as 20% efficient, with considerable energy loss even when not supplying
any power to the device. Though individual losses may be only a few watts,
it has been estimated that the cumulative loss from such transformers in US
alone exceeded 32 TWh in 2002.
Standby losses must be tracked as a serial killer.
Reference and recommended reading:
http://www.efficientpowersupplies.org/pages/NRDC_power_supply_report.pdf
22
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
[ Interlude ]
1 W all around the year ?
during 1 hour
during 1 day
during 1 year
1 instance
1 million instances
0.001 kWh
0.024 kWh
8.8
kWh
1.0
24.0
8.8
MWh
MWh
GWh
32 TWh in US?
for 1 person
110
kWh
12 W per person all around the year [*]
<<<< LOSSES
[*] cumulative consumption: home, office, ..
23
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
The Importance of the Scale Effect
12 W
with 1 kW at ≈ 0.1 €
all around the year ?
i.e a bill of 110 kWh each year per person
during 1 year
1 instance
300 million instances
11.0 €
3.3 G €
<<<< LOSSES
It does not hurt too much ?
This is a good driver
24
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Standby and Idle Mode Power Consumption
Standby is activated when an equipment is “turned off” but the user wants a
quick start. In analog, there is no particular difficulty at the exception. For
example, of the potential risk of a popping noise in earphones or loudspeakers.
In digital, there is a cost associated to save machine states in appropriate
registers the states. In software, disk drive or non volatile memories are used to
make a snapshot of the system. This potential source of subtle bugs cannot be
underestimated. Systems may be in standby mode all around the year with a
power consumption ideally at zero.
Idle mode. The system must insure a quick wake-up. This mode is much more
complex to manage in mobile equipment where significant energy savings are
expected. A part of the system, as small as possible, remains active and is
responsible for the quick wake-up. State machines managing the idle mode are
often very complex, desing of the parts remaining active are challenging.
25
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Standby Power Consumption
Regulation authorities are driving the power reduction
There is no severe technical obstacle to power reduction but there is a
COST BARRIER to smash.
All products should be designed to minimize the standby power consumption.
Regulation authorities have triggered the momentum. Now that this is started,
the effort is in the development of low cost techniques.
Forgetting the standby power consumption is a BUSINESS KILLER.
Customers are becoming sensitive to this specification, although they are not
willing to pay more. Being the best on this aspect is becoming smoothly a
strong BUSINESS DIFFERENTIATION.
26
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Idle Power Consumption
Mobile applications are the most active drivers
All techniques to reduce losses in a portable device are rapidly implemented.
There is a significant R&D effort world-wide on this topic.
Leakages in advanced IC technologies impact significantly idle power
consumption. This is a formidable challenge that industry is fighting
actively on a daily basis.
27
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Battery Charger and Battery Management
It is all about battery electrochemistry, metrology and energy management
Efficiency
charger itself is not the main concern
as it is plugged to an external source.
Precision and Metrology
how to estimate precisely the
remaining energy in an aging battery
idle mode consumption is a severe
requirement (battery gauge..)
Safety
how many are forgetting their charger
on an electrical outlet?
Integration
http://www.maxim-ic.com/app-notes/index.mvp/id/680
how to mix power electronics with
digital and analog applications
28
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
A Typical Example: the USB Battery Charger
There are a lot of reasons to
prefer ONE single good charger
to a set of cheap solutions.
The battery may
be also charged
from any USB master.
Nokia Travel Charger AC-6
For a design point of view, the USB link is a source of headaches to maintain
a good conversion efficiency. But the USB is also an ideal data link to exchange
precious information back and forth!
29
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Inductive Coupling
Coupling, a Cordless World
Efficiency is an obvious design care.
New and very exciting developments to come!
Palm Touchstone
Palm Touchstone
http://www.gizmodo.fr/wp-content/uploads/2009/06/22touchstone-teardown-rm-eng.jpg
30
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
The Root Causes of the Power Consumption
• The application !
Search for the right algorithms in the right architecture!
• The active power.
 CV2f
 represents the activity of the IC. Capacitance C is correlated to the
complexity. Higher speed (f) is requiring higher voltage (V2).
• The static power.
Leakages
Leakages are larger in advanced process which are used for the
largest applications.
31
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Operating Voltage
Operating voltage is an important factor in the power consumption I
• Limit overdesign !
• Clean supplies: power AND ground
• Use efficient voltage regulators
32
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Overdesign
The root causes of overdesign are related to a poor analysis of the
market or of the customer requirements, on a loosely defined product
or a loose design.

The system is targeting too many applications.
We have to verify that the most demanding targets
are realistic.

A system is often overspecified to compensate for
the weakness of the analysis.

Designers are tempted to “build” too larger design margins
Overdesign has a MAJOR impact to the size and the power consumption of
IC modules. Design margins are necessary but should be justified by solid
statistical analysis.
33
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Limit Power Supply Voltage
FMAX depends on the gate delay which depends directly on the current
in the CMOS gates which depends on the supply voltage. Choose the
smallest operating voltage suited to reach specified performances.
CMOS gate delay may be approximated in many ways. This is the
Taur-Nin model [*] :
Gate Delay  C load


V
th
 0.7 


VSupply 

[*] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices.
Cambridge University Press, 1998.
34
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Power Supply Noise Impact on IC’s Performances
This is a deadly MISTAKE.
Package is blocking high frequencies.
Supplies must be decoupled internally
using integrated bypass capacitors.
10%
6%
8%
8%
6%
10%
4%
12%
Fmax 130nm
Fmax 90nm
Vdrop 90nm
2%
0%
14%
16%
voltage undershoot
It is important to stress that,
despite a common belief, external
bypass capacitors are not effective
on all the supply noise bandwidth.
speed increase
Power supply noise limits the IC maximum operating frequency.
0.0μF 0.2μF 0.4μF 0.6μF 0.8μF 1.0μF
core capacitance
[ Freescale 2006 ]
Another belief is that a larger bypass
capacitance provides automatically a better decoupling. The power
distribution network is a complex RLC structure and is prone to resonances.
35
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Clean Supplies
Bad supplies cause IR drop, therefore losses but also produces ringing. Both
have to be compensated by larger supply voltages, an additional power
consumption.
The art or science of decoupling the supplies was the distinctive characteristic
of the good electronic engineer.
In the microelectronics era, it was stated that this is the reserved domain of
the PCB design. It WAS indeed true in the TTL era. This is not true anymore.
…
Each power supply distribution strip is
bypassed with a 100 nF capacitor at the
top and bottom. This should provide
sufficient bypassing, but in case of
suspected problems, you may want to
place a 100 nF bypass capacitor at
each TTL package.
…
36
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Each power supply distribution strip is
bypassed with a 100 nF capacitor at the
top and bottom. This should provide
sufficient bypassing, but in case of
suspected problems, you may want to
place a 100 nF bypass capacitor at each
TTL package.
37
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Impedance of a Power Supply Network
Power Supply Impedance
Normalized Magnitude
NB: Noise bandwidth
depends on the
slopes of signals
10
No Bypass Caps
1 Bypass Cap on PCB
BWnoise  0.35 / slope
An example of [rough]
hierarchical bypassing
Rtarget
1
TTL era
0.1
10KHz
100KHz
1MHz
MHz
10MHz
100MHz
1GHz
tens of MHz
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Frequency
GHz
38
Bypassing techniques
Bypassing techniques are more sophisticated that
what we have presented.
This is a science. Bypassing strategy, modeling and
simulations are possible.
But as EDA tools are lagging, brute force simulations
are overflowed by the complexity of the designs. This
is therefore also an art.
Good decoupling not only guarantees a correct
functionality but increases the speed that a circuit is
able to reach without increasing the supply voltage!
This is a distinctive area for differentiation and
therefore a confidential topic.
39
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Voltage Converter and Regulation
Power management is a “system in the system”.
With supply switches, Voltage converters and regulators act as the actuators
of the system’s power management.
DC-DC converters and linear voltage regulators are the typical solutions.
Currently, at the exception of low power ICs, the vast
majority of the voltage regulation modules are not
perfectly integrated as a few external devices still
resist to a low cost integration.
We have to distinguish the voltage converter which has the main function to
convert the voltage with a minimum of losses and the voltage regulator, which
has to regulate the output voltage.
Both are expected to minimize losses as far as possible.
40
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Linear Voltage Regulators
Vsupply
Rregulator
feedback
Vregulated
 x Vregulated
Vreference
Load
Losses  Vsupply  Vregulated  
Efficiency 
Vregulated
Vsupply
Vregulated
Rload
 100%
[ neglecting the regulation! ]
The voltage regulator is a kind of bidirectional filter.
Low frequency current noise for instance is kicked back to the input.
Therefore, linear voltage regulators must be included in the modeling of the
power supply network. Models should include their non linear behavior!
41
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Voltage Converters
Two major categories:
• Step-down and step-up DC-DC converters using LC tanks
• Switched Capacitors DC-DC converters (e.g. voltage doubler,…)
The energy density in LC elements is usually
not compatible with integration of LC tanks.
Integrated solutions are now proposed in some
low power mobile applications.
Switched capacitors converters are limited to smaller power.
42
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
DC-DC Converters using LC Tanks
C
One example of Step-up converter
(aka Boost Converter)
Vout
D
Vbat
S
Tip: the hydraulic ram and boost
converter are based on a similar idea.
L
Hydraulic Ram
In hydraulic analogy, there is
no “inductor”. The water has a
significantC mass which could
store kinetic energy.Vout
S
D
In electricity
the mass of the
electron is not significant.Vbat
A
L
dedicated inductor stores the
“kinetic energy” of the
electrical current.
43
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Hydraulic
DC-DC
Boost
RamConverter
C
Vout
S
D
Vbat
L
air
C
water out
D
waste water
S
feed pipe
L
water in
44
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
DC-DC Converters
An example of a step-down & step-up
converter [ aka Buck-Boost or SEPIC ]
IN
OUT
As DC-DC Converters are based on an energy exchange between
the potential energy stored in the capacitor and the kinetic energy
stored in the inductor, there is no dissipation but the dissipation
due to parasitic resistances, control circuitry and switching scheme
inaccuracies.
Efficiency is quite good excepted in low current regime.
DC-DC converters are among the important modules which are
profiting from a healthy R&D work of labs and industry.
45
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
The Power Distribution Network [ aka PDN ]
From external supply (battery, …) to the internal modules, all the chain
must be carefully designed, modeled and simulated.
It is impossible to simulate the system at the transistor level.
The PDN is including highly non linear modules and resists to accurate
linear approximation. It is very difficult to realize a good
decoupling to limit noise at an acceptable level.
For the power consumption estimation, the modeling and simulation are quite
simple. The major issue to get the best compromise between a simple but
inefficient architecture and a costly more efficient solution.
System partition, IC processes, Power Management, PCB complexity and
cost are the major factors to consider.
A good PDN is the 1st condition to keep power consumption under control!
46
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
The PDN “Consumers”
From specifications, IC processes and current know-how, the voltage of
each modules is chosen to the best values.
Analog modules are powered by a dedicated network. Supply noise is the
major concern. They are traditionally considered as the “victims” although
some class D amplifiers for example could be considered as “aggressors”.
Analog modules are traditionally powered on/off by control signals.
Fast digital I/O (like DDR3) are powered by another dedicated network.
They are truly “aggressors” for all other modules. Decoupling is needed!
Digital modules are powered by a set of dedicated networks. Each network
may be switched on or off to limit power consumption despite high transistor
leakages. Voltages may be chosen separately. For SRAM modules in retention
mode, the voltage may be lowered to keep the information stored in the array
while limiting the power consumption.
Internal Busses and Clocks. Heavily loaded, they are significant contributors
to the power consumption of a digital IC.
47
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
The Power Down Issue
IC modules may be tricky as the power consumption could depend
on the value of external voltages or on external loads.
There are a few mistakes to avoid.
• Internal floating nodes.
large current
floating node, erratic voltage
≈ON
Hi Z
≈ON
• I/O nodes. Loosely defined system may connect 2 ICs in a wrong way.
Hi Z
Hi Z
VDD

VSS
Hi Z
VSS
OK
48
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
A Power Up Issue
The IC, of course, has a global reset. Hardware or Software?
Let’s imagine that a system engineer decides that a software reset is enough.
When supplies are activated, the IC is waiting for a software reset.
So far so good...
The IC is powered on, but its internal bus is idle. The software reset
is supposed to be transmitted through the bus to position a control bit
somewhere. This control bit will eventually reset the bus? Perhaps not…
Bus driver at 0
Bus driver at 1
VERY large current
BUS
SHORT
CIRCUIT
FLOATING
BUS, erratic voltage
≈ON
Hi Z
32 bits
≈ON
Supply is OVERLOADED !!!
49
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Soft Floating Node: the Hidden Killer of Analog ICs
Voltage could be
as large as VTn
due to small
leakages in
drain junctions.
OFF
Wp
Due to mismatches, VTp of
this
transistor could be a few tens
of mV smaller than the driver.
Current is significantly larger.
Wp
10 pA
1 μA
10 nA
Wn
10 Wn
?
Due to mismatches, VTn of this
transistor could be a few tens
of mV smaller than the driver.
Current is significantly larger.
Solution:
3 .. 4 orders of magnitude
OFF
Voltage is 0
ON Wp
10 pA
10 pA
10 pA
ON
Wn
Wp
OFF!
10 Wn
50
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Power Management in Large ICs
In large ICs like microprocessors, DSPs or SoCs, the power management
represents a significant design effort. Power management is often shared
by dedicated hardware, embedded software and application.
There are at least 4 operating modes:
- active mode
off
idle
- idle mode
active
- standby mode
- off mode
standby
There are several techniques used together to limit the power consumption
in each mode. Statistics modeling and simulation are worth to be used.
51
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Active Mode
For the thermal management, this mode is of course the most
demanding.
Active mode drains the maximum current from the supplies.
Many techniques are used to keep the power consumption to a
minimum.
[ These techniques will be described later ]
52
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Idle Mode
Parts of the system are stopped but their information is retained in a fast
access memory (SRAM, Flash, ..). System is reactivated from time to
time to refresh synchronization with external links. The system is
supposed to wake up extremely quickly.
This mode could be the major contributor to the energy consumption
of the system for 3 reasons:
- This system is mainly operating in idle mode (e.g. phones)
- Real time clock and counters are running.
- Process leakage.
A good design of the system architecture is key to keep the power
consumption to a reasonable value.
53
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Standby Mode
The system (or part of a system) is stopped but its information
is retained in a fast access memory (SRAM, Flash, ..).
The system needs some time to start-up to resynchronize to
external links like RF, ADSL…
All combinatorial logic is switched off or at least the clocks are
stopped. SRAM are in a retention mode with a supply maintained
at a minimal retention voltage.
There is no activity. The system is waiting for a software or a
hardware on/off command.
Leakage control is the main issue.
[ It will be described later ]
54
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Off Mode
Although the system is still physically connected to the
external supply, it is not supposed to drain any significant current.
Previous state of the system may be stored in some non volatile
memory (disk drive, flash memory..).
There is no activity. The system is waiting for a hardware on/off
command.
Floating nodes are the traditional killers of the Off Mode esp. in
mixed signal modules.
Hi Z
Hi Z
55
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Active Power
P =  CV2 f + leakages
The product  f corresponds to the activity of the system.
Architecture and algorithms must be tuned.
Supply voltage V is obviously important. Limit overdesign at least!
C is the capacitance of active wires, 2 solutions:
• Process scaling
• 3D-IC
“More Moore”
“More than Moore”
In the recent CMOS processes, leakages cannot be ignored anymore!
56
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
High Importance of Algorithms and Architecture
There are more expectations to reduce active power by selecting at high
level the best algorithms or to use the best hardware solutions.
HARDWARE or SOFTWARE?
Application specific hardware is always much
More efficient. But it is obviously restricted to
low level designs by the lack of reconfigurability.
FPGA offers some of the expected reconfigurability but performances and cost
are deceiving. It exacerbates THE problem of 2D circuits: the weakness of the
connection system.
Software solutions are very poor performers in speed and power efficiency.
Their reconfigurability makes them nevertheless a successful choice.
57
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Active Power by Parallelization
The major contributor is the system architecture. This is where
efforts should be directed first.
A few hints: system architecture, algorithm, data move…
Parallel architecture should be preferred,
although there is not yet really satisfactory
parallelization scheme of serial algorithms
Example: what is the more efficient bus?
1 wire at 1.024 Gbits/s
or
1024 wires
at 1 Mbits/s
58
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Prefer Parallel Solutions, a Simple Example
What is the more efficient bus?
1 wire at 1.024 Gbits/s
1024 wires
at 1 Mbits/s
Active power Consumption is proportional to: #transitions * C * V2
[ C of 1 wire ! ]
1 high speed signal
Active power: lower
[Static power: higher]
1024 low speed signals
lower VDD
59
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Parallel Solutions ? Not so Simple !
Some applications are obviously parallel. For cost pressure, they have
been painfully serialized making real-time software pathetically complex.
The power reduction targets are now pushing to parallel processing.
- Data transfer, memory, … are making parallel processing very complex.
- Cost is another major barrier to parallelization.
- Many algorithms are serial by nature. Parallelization is more than
challenging. Breakthroughs are still regularly announced…
- Multicore processors are replacing single core processor.
60
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Active Power:
w’ = w / λ
l’ = l / λ
e’ = e / λ
rchannel = … (e/εox) * l / w
cgate
rc’ = r c / λ
cg’= cg / λ
(εox/e) * w * l
=
Process Scaling
rc’cg’ = rccg / λ^2
w
w’ = w / λ
l’ = l / λ
e’ = e
rc’ = rc
cg’= cg / λ^2
e
rc’cg’ = rccg / λ^2
l
[ This is not as good for the connections ]
61
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Active Power:
3D-IC “More than Moore”
2D - IC
3D - IC
Shorter wires
Lower capacitances
Die 3
It is all about system
partitioning, architecture,
business model, cost…
>1000’s Through Silicon Vias / mm2
Die 2
One Chip
Die 1
62
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Active Power:
Data Transfer
LIMIT the transfer of the data !
Significant improvements could be obtained during the design of the high
level architecture! SoCs may take profit of differentiated structures.
This is a hot subject although a significant breakthrough is still to be found!
One example among
MANY proposals:
Time Triggered Architecture
[ aka TTA ]
http://en.wikipedia.org/wiki/Transport_triggered_architecture
63
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Data Transfer, Minimize Voltage
• It is important to choose efficient solutions. Overdesign should be avoided!
CV2f
Do not underestimate capacitive coupling between wires!
High-Level Interconnect Delay and Power Estimation
A. Courtay, O. Sentieys, J. Laurent, and N.Julien
Journal of Low Power Electronics Vol. 4, 21–33, 2008
64
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Data Transfer, Be Smart
•To reduce power, adaptive techniques may also be applied, e.g.
CV2f
CRC
CRC
BER
feedback supply control
Always the right supply. Never higher!
But this is costly…
65
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Active Power:
the Clocks
Clocks are the fastest, the busiest and the most loaded signals of a system.
• Gated clocks are now well supported by EDA tools and do not represent
a design challenge anymore: clocks are distributed only to modules in activity.
• Clock rates are chosen statically or dynamically to respond to the desired
throughput of the IC modules. Clock domains and voltage domains partition
system and IC.
• In some applications, asynchronous logic is preferred. Clock is then used only
as time keeper.
Real time clock is a low speed and precise clock used for time keeping. Very
often, the power consumption of a real time clock is reduced to a bare minimum.
Real time clock may be used in idle mode as system clock. Jitter is a killer.
66
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Active Power:
DVFS
Dynamic Voltage and Frequency Scaling, aka DVFS is the current solution to
put the active power consumption of an IC under control!
There are a few reasons to modulate the speed of an application.
Under hardware control:
• Limit power consumption by running at the smallest supply voltage
• Keep the operating temperature of an IC under control
Under software control:
• Limit power consumption by running an application at the right frequency
67
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Adaptive Dynamic Voltage and Frequency Scaling
Under the control of the hardware, the voltage may be tuned finely, with a
relatively fine granularity, to maintain the operation with a minimal supply.
This is a dynamic calibration of the performances instead to the traditional
calibration of the supply voltage to the specified value. Design is done for typical
process parameters with Adaptive DVFS insuring the functionality at the process
corners. Design is more aggressive, sizes are smaller, parasitic capacitances
are smaller, great factor diminishing the power consumption.
On a mobile terminal for instance, the power consumption is a concern per se.
All tasks do not need to run at the same speed. It is therefore interesting to
limit the operating frequency to the minimum and reduce the supply voltage
accordingly. The granularity of Adaptive DVFS may be as small as a module.
On a portable computer, the processor[s] may be heavily loaded and
temperature could reach critical limits. Slowing down the core and diminishing
the supply is an efficient way to bring back the IC to a reasonable temperature.
DVFS and Adaptive DVFS are adding more complexity as modules may run
asynchronously. Under the control of the application software they are a potential
source of bugs.
68
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Static Power:
Voltage Supply?
To reduce the static power consumption, it is tempting to reduce the supply voltage:
PStatic  VSupply I Leakage
Vsupply reduction
Reduce
ILeakage !! ?
Gate Delay  C load


 0.7  Vth 

Vsupply 

To keep performances, threshold
voltage should follow the reduction
of supply voltage!
I ds  I ds0
PStatic  VSupply I Leakage
W
e
L
 Vth

 n kT q



 Vds 

 
 
kT
q
1  e 





Leakage is exponentially
dependant on the reduction
of the threshold voltage.
69
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Reducing Static Power:
Reduce leakage!
Off mode: the ultimate solution is the power switch.
In Standby or Idle mode where data retention is mandatory, 3 solutions:
1. Use high threshold voltage devices where they are not impacting critical paths.
2. Use low supply voltage in retention mode (in SRAM, …)
3. Use dynamic threshold voltage control by back gate biasing (body effect)
Vbackgate
Vth
well
70
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Leakages in Nanometric Technologies
Large Variability!
• High LEAKAGES
• Highly UNPREDICTABLE

Device Simulation of Random Dopant Effects in
Ultra-small MOSFETs Based on Advanced Physical Models
Toriyama, S.; Hagishima, D.; Matsuzawa, K.; Sano, N.;
Simulation of Semiconductor Processes and Devices,
International Conference on Physical Models, Sept. 2006
71
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
New Transistors ?
[1]
LETI
[5]
Hot activity on new concepts!
Freescale
[2]
FD SOI FET [1], Double gate FET,
FinFET [2], Junctionless Nanowire Transistor [3],
Graphene Transistor [4], Carbon Nanotube [5] …
[3]
With a major target:
Improving the ratio ( Ion/Ioff )
Tyndal
None of them are reducing leakages to zero…
[4]
MIT
72
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Let’s Face It. Leakage is a Reality.
Leakage is THE problem.
Energy
management
Power management
cannot be ignored.
Be aggressive.
smart.
Solution
below ?
73
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Conclusion,
No Simple and Definitive Solution
We can safely state that there is no single solution
to power consumption reduction.
A continuous effort is required.
[ Way to success is narrow.. ]
Power consumption is the other
problem of the XXI century.
74
Yves Leduc, Texas Instruments France,
ECOFAC March 2010
Thank you for your attention !
75
Yves Leduc, Texas Instruments France,
ECOFAC March 2010