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Characteristics of fabrication processes, pixel designs and simulations A. Dorokhov 09/05/2017 1 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Monolithic active pixel sensors substrate/EPI substrate or/and epitaxial layer (p-type) charge collecting electrode (s) (nwell) particle chip is fabricated in CMOS technology: readout electronics fabricated next to charge collecting electrode at the same substrate -> 9/05/2017 choice of proper fabrication process is important A. Dorokhov, IPHC, Strasbourg, France 2 Fabrication of MAPS in CMOS process Low resistive substrate/epitaxial layer (<10 Ohm cm): not easy (or not possible) to deplete detector volume MAPS development : AMSxx, XFABxx technology High resistive substrate/epitaxial layer (~>1 kOhm cm), easier to deplete detector volume Twin/Double well process: one can use simple circuitry in pixel-> only NMOS transistors are allowed first MAPS detector for particle experiment (STAR at RICH), EUDET : AMS technology Triple/quadruple well process -> can use advantage of NMOS and PMOS in the pixel volume ALICE tracker upgrade, CBM tracker: TOWER technology In order to help understanding of operation, get new ideas, verify the performances of the MAPS detector simulation of the sensing elements and readout circuit is needed: device simulation with TCAD and Spectre simulation (Cadence) 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France 3 TCAD device simulation of pixel Pwell Nwell layout geometry of one pixel MIMOSIS0 chip, transistors are inside Pwell 18um EPI of 10 Ohm cm (low resistivity) Bias=1V Bias=40V well exclusion area due to symmetry simulate only one quarter of rectangular pixel Depletion zone comparable, at 1 V and 40V of bias for different substrates Bias=1V Bias=20V Bias=40V TOWER 18um EPI depletion 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France 4 TCAD device simulation different EPI Bias=1V Bias=20V Bias=40V TOWER 18um EPI TOWER 25um EPI TOWER 30um EPI 5 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 6 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 7 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 8 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 9 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Conclusions for presented example of comparison high resistive substrate and low resistive Low resistive substrate: 1. Almost no depletion 2. Leakage current is smaller High resistive substrate: 1. Helps a lot to deplete pixel volume 2. Leakage current is larger 3 .capacitance almost not changed 4 . going from pixel pitch 26.88x30.24 to 22x22 does not change much leakage, capacitance and depletion volume, because we do not have full depletion, only the depletion fraction is much larger (x ~2) 10 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France TCAD device simulation of different pixel geometry 40um of 600 Ohm cm Si, 22x22um^2 pitch surface of Nwells and Pwell exclusions are independent on shape (circular, octagonal or square) circular Nwell, circular PWell exclusion octagonal Nwell, circular PWell exclusion circular Nwell, square PWell exclusion octagonal Nwell, square PWell exclusion 11 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 12 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 13 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 14 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Results of TCAD device simulation 15 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France Conclusions for presented example of comparison different Nwell and Pwell exclusion shapes 1. The shape of charge collecting diode has marginal influence<few % 2. The shape of Pwell exclusion has small influence (<10%) 16 9/05/2017 A. Dorokhov, IPHC, Strasbourg, France