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CENG3480_B1
Digital System Clock
Reference: Chapter11 of High speed
digital design , by Johnson and Graham
Clock distributions (v.9a)
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Setup time and Time margin
 Setup time: The time that the input data
must be stable before the clock transition of
the system occurs.
 Timing margin measures the slack, or
excess time, remaining in each clock cycle
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Protects your circuit against signal cross-talk,
miscalculation of logic delays, and later minor
changes in the layout.
Depends on both time delay of logic paths and
clock interval.
Clock distributions (v.9a)
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Example to show the importance of time margin
 A 2-bit ring counter
 Initially A,B =0 ; A=001100110
 What is B?
A
B
Clock distributions (v.9a)
Ans: 011001100
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A 2-bit ring counter example (Cont’d)
 The result is ok when the clock is slow.
 But we may have problems when the clock is too fast. (see
next page)
Clock distributions (v.9a)
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
May cause problem if
TCLK is too short
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Exercise B4.1
 Given:
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CLK1=CLK2=20MHz,
FF clock-to-Q output delay=8ns;
setup time for FF is 5ns;
Gate delay G is 10ns;
Q1 Q2 are 0 initially.
 Questions:
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Find time margin.
How many delay G gates can you insert between A and B without creating error?
A
B
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Clock Skew

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The clock does not reach at FF1, FF2 at the same time
E.g. Clock skew =(TC1,max - TC2,min) =1 ns,
a positive skew when TC2,min happens earlier than TC1,max, FCLK0 cannot be
too high.
CLK0
TCLK1
TC1,max= latest TC1arrival time
delay1
TCLK2
TC2,min= earliest TC2 arrival time
delay2
Set t=0 here
Skew (T C1,max - T C2,min)
A positive skew
Source
clock:CLK0
Clock distributions (v.9a)
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Clock skew

Clock source
CLK1
CLK2
TFF+TG
Time t=0 T T
c2 c1
Tsetup Tclock
Skew (T C1,max-T C2, min)
FF1
FF2
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Clock skew (at FF1)
 Due to the problem when the synchronous clock
does not arrive at various components at the same
time.
 The latest possible arrival time for a pulse coming
through gate G is
Tslow = TC1,max + TFF,max + TG,max
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Tslow= slowest arrival for pulse from G
TC1,max =Max. delay of path C1
TFF,max =Max. delay, clock to Q of FF1
TG,max =Max. delay of G, including trace delay
Clock distributions (v.9a)
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Clock Skew (at FF2, the next cycle)
 The arrival time required by FF2 is
Trequired = TCLK + TC2,min - Tsetup
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Trequired=elapsed time by which data from G must arrive
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TCLK=interval between clocks; clock period
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TC2,min =Minimum delay of path C2
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Tsetup =worst-case setup time required by FF2, data at
D1 must arrive at least Tsetup before CLK2
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Clock Skew (combining delay & setup requirements)
 Data from G must arrive before Trequired to properly set FF2. So,
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Trequired – Tslow > 0, hence Trequired > Tslow, therefore
TCLK + TC2,min - Tsetup > TC1,max + TFF,max + TG,max
TCLK > TFF,max + TG,max + Tsetup + (TC1,max - TC2,min) + Tsome_margin
 Example: assuming
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TFF,max = 6ns
Delay between Flip-flops, TG,max + Tsetup = 5ns + 3ns = 8ns
clock skew =(TC1,max-TC2,min) =1ns, a positive skew when TC2,min happens
earlier than TC1,max.
Timing margin Tsome_margin = 4ns (make sure the circuit is reliable)
Total = 18ns ==> Fmax= 55.5MHz
Use clock frequency =55MHz would be safe.
Clock distributions (v.9a)
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Exercise: B4.2
 Given:
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TFF,max = 7ns
TG,max= 5ns
Tsetup =4ns
Timing margin Tmargin =3ns
FCLK =40MHz
 What is the biggest time skew allowed?
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Strategies to reduce clock skew

Two main strategies:
1. Locate all clock inputs close together; but it is difficult to
implement in a large circuit.
2. Drive them from the same source & balance the delays

Due to physical limitation, strategy 2 is often used
1. Spider-leg distribution network
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use a power driver to drive N outputs.
Use load (R) termination to reduce reflection if the traces are long
(distributed circuit). Total load =R/N.
E.g. line impedance=75 , N=3, total load=25.
Two or more driver outputs in parallel may be needed.
2. Clock distribution tree.
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Spider leg Distribution Network
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Clock distribution tree
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Delay adjustment
 The simplest clock adjustment is fixed delay.
 Fixed delay:
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Delay line by transmission line: short delays 0.1-5ns,
10% variation, accurate.
Gate delays 0.1-20ns, 300% variation, not accurate.
Lumped-circuit delay (RC)
• Figure 11.10: 0.1->1000ns, variation 5-20%, accurate.
 Adjustable delays
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Delay line directly printed on PCB; delay may vary
with temperature
Insert a RC circuit between two buffers
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Selectable delay adjustment (using jumper)
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Selectable delay adjustment (using jumper)
 Jumper block will have
bigger Capacitance
 Use direct solder is better by
more difficult to tune
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Low Impedance Clock Distribution Line
 Three means to reduce reflection pulse heights
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Slow the rise & fall time of the driver
Lower the capacitance of each tap
Lower the characteristic impedance of the clock distribution line
 Must also try to minimize the parasitic capacitance of the
connector and PCB
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Differential Distribution
 Can survive tougher noise environment
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Better signal size (lower amplitude: half)
Differential Balance
 ECL signal system is better than TTL
Clock distributions (v.9a)
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Clock Signal Duty Cycle
 Ideal duty cycle: 50%
 Falling edge of an ideal clock signal bisects successive
rising edge
 Average DC value lies halfway between Hi & Lo states
 Keeping symmetry is difficult because asymmetry
response to rising and falling edge
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Different propagation delays TLH & THL
 Long chain of identical gates will distort the pulse width,
positive pulse may emerge shorter (and vice versa)
 Two clever tricks:
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Inverts the clock signal at every stage (balance the distortion)
Use analog circuit to reshape the waveform
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Analogue circuit to reshape the clock
 Tuning is difficult
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Cancelling Parasitic Capacitance
 When new device is added to a multi-drop line, the parasitic
capacitance may cause clock phase shift (a function of the
parasitic Capacitance)
 Use a negative reactance to cancel the effect
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works at a particular frequency only
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Clock Generators (Oscillators)
 Seldom design our own
 Comes in hermetically sealed package
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A thick film hybrid circuit on a substrate
 More important to understand the requirements
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Frequency Specifications
 Frequency (Hertz, KHz, MHz, GHz)
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Nominal operating frequency or centre frequency
Higher frequency is synthesis by filtering and enhancing harmonics of
the crystal’s fundamental operating frequency
 Stability
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Consolidates variations due to temperature, manufacturing processes,
operating voltage and aging
In parts per million (ppm); one-hundred ppm = 0.01 %
 Aging
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In ppm/year
Younger crystal ages faster
 Voltage sensitivity
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Allowed Operating Conditions
 Temperature
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Typically 0 – 70oC
Cause Frequency change
Temperature drift is not linear
 Input voltage
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Like Vcc spec. for IC
 Shock
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Refers to mechanical (not electrical) shock
In units of G’s
Apply shock tests in both polarities along all three geometric axes
 Vibration
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Similar to shock, violently shakes the oscillator
Shock & vibration tests are essential to military or similar products
 Humidity
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Hermetically sealed package can easily work at any condition
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Electrical Parameters
 Output type
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TTL, CMOS or ECL (10K or 100K) outputs
 Maximum loading
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Excess load may cause drift
 Duty Cycle
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More difficult to guarantee at higher frequency
 Rise and fall times
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Common practice: 10-90% are given in ns
 Input current
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In milliamps
A function of the Frequency; higher the frequency, more
energy is required
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Mechanical Configuration
 DIP
 Half DIP
 Surface mount
Manufacturing Issues
 Solderability
 Cleaning
 Package leak rate
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Reliability
 Functional screening (how many did manufacturer
test)
 Aging at accelerated temperature
Bells and Whistles
 Differential outputs
 Enable
 Voltage controlled oscillator (adjust frequency
electronically)
 Tuning
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Other Issues
 Clock Jitter
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Clock oscillator contains a high frequency amplifier
that may resonate
This high frequency signal may appear as noise and
appears at the output in the form of clock jitter
(superimpose of base signal and higher frequency
components)
May cause malfunction
Can use measuring technique and feedback system to
control the effect
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 Need to control Power supply stability
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Supply variation will affect the frequency and will
appear as noise
 Laying clock signal lines also need special
attention
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Cause lots of noise (cross talk due to high frequency)
Must try to specify, demand special treatment and lay
out the clock distribution network first
Use thicker line or isolation grid to make bigger
separation from other signals
Use a separate layer
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Answer for B4.1
 Clock cycle is (T) 1/20Mhz = 50 ns
 Time margin = T- clock_to_Q+ setup_time delay_G

= 50ns – 8ns-5ns-10ns=27ns
 Since each delay is 10ns, so you may add 2
more (totally 3 between A and B).
Clock distributions (v.9a)
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Answer: B4.2
 TCLK > TFF,max + TG,max+ Tsetup + (TC1,max-TC2,min) +Tmargin
 TFF,max = 7ns
 TG,max= 5ns; Tsetup =4ns
 Timing margin Tmargin =3ns
 FCLK =40MHz => TCLK =25ns
 Max. Time skew (TC1,max-TC2,min)> TCLK -(TFF,max + TG,max+Tsetup+Tmargin )
=25ns- (7ns+5ns+4ns+3ns)= 6ns.
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