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Transcript
International Journal of Electrical and Electronics
Engineering Research (IJEEER)
ISSN 2250-155X
Vol. 3, Issue 2, Jun 2013, 249-260
© TJPRC Pvt. Ltd.
SWITCHING FREQUENCY HARMONIC SELECTION FOR SINGLE PHASE
MULTILEVEL CASCADED H-BRIDGE INVERTERS
G. SUDHA RANI1 & RASOOL AHEMMED. SK2
1
M.Tech Student, Department EEE, K L University, Vaddeswaram, Guntur District, Andhra Pradesh, India
2
Assistant Professor, Department EEE, K L University, Vaddeswaram, Guntur District, Andhra Pradesh, India
ABSTRACT
This paper presents a single phase multilevel cascaded H-Bridge inverters are used wherein the output waveform
has several voltage levels leading to a better and more sinusoidal voltage waveform. As the number of voltage levels reach
infinity, the output THD approaches zero. As a result, a lower total harmonic distortion (THD) is obtained. This is
proposed, by using MATLAB simulations.
KEYWORDS: Switching Frequency Selection, Separate dc Sources (SDCSs), Number of H-Bridge Inverters, Total
Harmonic Distortion
INTRODUCTION
Pulse width modulation (PWM) control strategies development concerns the development of techniques to reduce
the total harmonic distortion (THD) of the current. It is generally recognized that increasing the switching frequency of the
PWM pattern reduces the lower-frequency harmonics by moving the switching frequency carrier harmonic and associated
sideband harmonics further away from the fundamental frequency component. While this increased switching frequency
reduces harmonics, resulting in a lower THD by which high quality output voltage waveforms of desired fundamental r.m.s
value and frequency which are as close as possible to sinusoidal wave shape can be obtained. Higher switching frequency
can be employed for low and medium power inverters, whereas, for high power and medium voltage applications the
switching frequency is of the order of 1 kHz.
A multilevel inverter is more recent and popular type ofpower electronic converter that synthesizes a desired
output voltage from several levels of dc voltages as inputs. If sufficient number of dc sources is used, a nearly sinusoidal
voltage waveform can be synthesized. In comparison with the hard-switched two-level pulse width modulation inverter,
multilevel inverter offers several advantages such as, its capabilities to operate at high voltage with lower dv/dt per
switching, high efficiency and low electromagnetic interference.
The general concept involves utilizing a higher number of active semiconductor switches to perform the power
conversion in small voltage steps. Nowadays, multilevel inverters have achieved increasing contribution in highperformance applications. Recently, for high-performance power application, multilevel converters are widely used such as
staticvar compensators, drives and active power filters. The advantages of multilevel inverters are good power quality, high
voltage capability and low switching losses.
The topologies of multilevel Inverters are classified into three types, that is, the flying capacitor, diode clamped
and cascaded multilevel inverters. Among these inverter topologies, the cascaded H-bridge multilevel inverters require the
least number of total main components. The general function of this multilevel inverter is to synthesize a desired voltage
from several separate dc sources (SDCSs), which may be obtained from batteries, fuel cells, or solar cells. These
250
G. Sudha Rani & Rasool Ahemmed. Sk
techniques take advantage of special properties available in multilevel inverter to minimize total harmonic distortion and
increase output voltage. A multilevel converter has several advantages over a conventional two-level converter that uses
high switching frequency pulse width modulation (PWM).
A cascaded multilevel inverter has several advantages they are, when compared with diode-clamped and flyingcapacitors inverters, it requires the least number of components to achieve the same number of voltage levels and
optimized circuit layout and packaging are possible because each level has the same structure and there are no extra
clamping diodes or voltage-balancing capacitor and Soft-switching techniques can be used to reduce switching losses.
SINUSOIDAL PULSE – WIDTH MODULTION
In sinusoidal PWM instead of maintaining the width of all pulses the same as in the case of multiple phase
modulation, the width of each pulse is varied in proportion to the amplitude of a sine wave evaluated at the center of same
pulse. The gating signals as shown in Fig 1. are generated by comparing a sinusoidal reference signal with a triangular
carrier wave of frequency fc. This sinusoidal pulse width modulation (SPWM) is commonly used in industrial applications.
The frequency of reference signal fr determines the inverter output frequency fo, and its peak amplitude Arcontrols
the modulation index M, and then in turns the rms output voltage V o .Comparing the bidirectional carrier signal Vcrwith
two sinusoidal reference signals Vr and -Vrshown in figure 1a produces gating signals g1 and g4, respectively, as shown in
Fig1b. The instantaneous output voltage is Vo = Vs(g1 – g4). However, g1 and g4can not be released at the same time. The
number of pulses per half cycle depends on the carrier frequency. Within the constraint that two transistors of the same arm
(Q1 and Q4) cannot conduct at the same time, the instantaneous output voltage is shown in Fig 1c. The same gating signals
can be generated by using unidirectional triangular carrier wave as shown in Fig 1d. The output voltage is Vo = Vs(g1 – g4).
The SPWM, which is most commonly used, suffers from certain drawbacks like low fundamental output voltage.
Figure 1: Sinusoidal Pulse-Width Modulation
Switching frequency Harmonic selection for Single Phase Multilevel Cascaded H-Bridge Inverters
251
Three Level H-Bridge Inverter with Sinusoidal PWM
Figure 2 Shows the Simulink Model of three levelH bridge inverter with sinusoidal PWM technique. Figure 3
shows the output voltage waveform of the single phase three level H bridge inverter with sinusoidal PWM technique. From
Figure 3 it is observe the dv/dt of three level H-bridge inverter with sinusoidal PWM is 800 V. The FFT analysis of output
voltage wave form is shown in Figure 4. In this figure it is observed that the dominant harmonic is shifted to high
frequency zone and its frequency is 5950 and 6250 Hz.
Figure 2: Simulink Model of Three Level H Bridge Inverter with Sinusoidal PWM
Figure 3: Output Voltage Waveform of Three Level H-Bridge Inverter with Sinusoidal PWM
Figure 4: Spectrum Analysis of Output Voltage of Three Level H-Bridge Inverter with Sinusoidal PWM
252
G. Sudha Rani & Rasool Ahemmed. Sk
CASCADED MULTILEVEL INVERTER
A cascaded multilevel inverter consists of a series of H-bridge single-phase, full-bridge inverter units. Figure 5
Shows the basic structure of a single-phase cascaded inverter with SDCSs. The ac terminal voltages of different level
inverters are connected in series. Unlike the diode-clamp or anflying-capacitors inverters, the cascaded inverter does not
require any voltage-clamping diodes or voltage-balancing capacitors.
Each inverter level can generate three different voltage outputs, +Vdc, 0, and -Vdc , by connecting the dc source to
the ac output side by different combinations of the four switches, S1, S2, S3, and S4. Using the top level as the example,
turning on S1 and S4 yields 𝑣𝑎4 = +𝑉𝑑𝑐 . Turning on S2 and S3 yields 𝑣𝑎4 = −𝑉𝑑𝑐 . Turning off all switches yields 𝑣𝑎4 = 0.
Similarly, the ac output voltage at each level can be obtained in the same manner. If NSis the number of dc sources, the
output phase voltage level is m=NS+ 1. Thus, a five-level cascaded inverter needs four SDCSs and four full bridges.
Controlling the conducting angles at different inverter levels can minimize the harmonic distortion of the output voltage.
Figure 5: Single-Phase Multilevel Cascaded H-Bridge Inverter
The output voltage of the inverter is almost sinusoidal, and it has less than 5% total harmonic distribution (THD)
with each of the H-bridges switching only at fundamental frequency. If the phase current ia , as shown in below Figure 6, is
sinusoidal and leads or lags the phase voltage 𝑣𝑎𝑛 by 90o , the average charge to each dc capacitor is equal to zero over one
cycle. Therefore, all SDCS capacitor voltages can be balanced. By connecting the sufficient number of H-bridges in
cascade and using proper modulation scheme, nearly sinusoidal output voltage waveform. The number of levels in output
phase voltage is 2s + 1, where s is the number of H-bridges used per phase. Figure 6 shows an 9-level output phase voltage
waveform using four H-bridges. The magnitude of the ac output phase voltage is given by 𝑣𝑎𝑛 = 𝑣𝑎1 + 𝑣𝑎2 + 𝑣𝑎3 +
𝑣𝑎4 .
Switching frequency Harmonic selection for Single Phase Multilevel Cascaded H-Bridge Inverters
253
Figure 6: Output Waveform of 9-Level Phase Voltage

CHB Five level inverter with Sinusoidal PWM

CHB Seven level inverter with Sinusoidal PWM

CHB Nine level inverter with Sinusoidal PWM
CHB Five Level Inverter with Sinusoidal PWM
Figure 7 shows the Simulink Model of five level CHB inverter with phase shifted carrier sinusoidal PWM
technique.
Figure 7: Simulink Model of Five Level CHB Inverter with Phase Shifted Carrier Sinusoidal PWM
254
G. Sudha Rani & Rasool Ahemmed. Sk
Figure 8 shows the output voltage waveform of five level CHB inverter with phase shifted carrier sinusoidal
PWM. From Figure 8.it is observed that the dv/dt of five level CHB inverter is 400 V.
Figure 8: Output Voltage Waveform of Fivelevel CHB Inverter
The FFT analysis of output voltage waveform is shown in Figure 9. From this figure it is observed that the
dominant harmonic is shifted to further high frequency zone and its frequency is 12050 and12650Hz
Figure 9: Spectrum Analysis of Output Voltage of Five Level CHB Inverter
CHB Seven Level Inverter with Sinusoidal PWM
Figure 10 shows the Simulink Model of seven level CHB inverter with phase shifted carrier sinusoidal PWM
technique.
Figure 10: Simulink Model of Seven Level CHB Inverter with Phase Shifted Carrier Sinusoidal PWM
Switching frequency Harmonic selection for Single Phase Multilevel Cascaded H-Bridge Inverters
255
The seven level CHB inverter with phase shifted carrier sinusoidal PWM output voltage waveform is shown in
Figure 11. From Figure 11 it is found that the dv/dt of seven level inverter is 266.66V.
Figure 11: Output Voltage Waveform of Seven Level CHB Inverter
The FFT analysis of output voltage wave form is shown in Figure 12. In this figure it is observed that the
dominant harmonic is shifted to further high frequency zone and its frequency is 17950 and 18650 Hz
Figure 12: Spectrum Analysis of Output Voltage of Seven Level CHB Inverter with Phase Shifted Carrier
Sinusoidal PWM
CHB Nine Level Inverter with Sinusoidal PWM
Figure 13 shows the Simulink Model of nine level CHB inverter with phase shifted carrier sinusoidal PWM
technique.
Figure 13: Simulink Model of Nine Level CHB Inverter with Phase Shifted Carrier Sinusoidal PWM
256
G. Sudha Rani & Rasool Ahemmed. Sk
The nine level CHB inverter with phase shifted carrier sinusoidal PWM output voltage waveform is shown in
Figure 14. From Figure 14 it is found that the dv/dtof nine level inverter is 200 V.
Figure 14.Output Voltage Waveform of NinelevelCHB Inverter
The FFT analysis of output voltage wave form is shown in Figure 15.In this figure it is observed that the dominant
harmonic is shifted to further high frequency zone and its frequency is 23850 and 24550 Hz.
Figure 15: Spectrum Analysis of Output Voltage of Nine Level CHB Inverter
No. of Levels
Three level H bridge inverter with Sinusoidal PWM
CHB Five level inverter with Sinusoidal PWM
CHB Seven level inverter with Sinusoidal PWM
CHB Nine level inverter with Sinusoidal PWM
Switching
Frequency in HZ
3050
3050
3050
3050
Dominant Harmonic
Frequency
6050 & 6150
12050 & 12650
17950 & 18650
23850 & 24550
Table I Effect of voltage levels and switching frequency on dominant harmonic. From the above table it is
observed that by fixing the switching frequency and when we increase the number of levels the dominant harmonic
frequency will increase. To use multilevel inverter in place of three level inverter, first we need to find a dominant
frequency for the given switching frequency in three level inverter.
CONCLUSIONS
This paper takes up the commonly used multilevel inverters and proposes a control scheme. Here, we are reducing
THD values for different levels of inverter i.e., for 3rd, 5th,7th, 9th. Furthermore, as the number of voltage levels reach
infinity and the output THD approaches zero.
REFERENCES
1.
MUHAMMAD H. RASHID, “Power Electronics-Circuits,Devicesand Applications”.
257
Switching frequency Harmonic selection for Single Phase Multilevel Cascaded H-Bridge Inverters
2.
L.UMANAND, “Power Electronics-Essentials and Applications”.
3.
J. Kumar, B. Das and P. Agarwal, Member, IEEE“SelectiveHarmonic Elimination Technique for a Multilevel
Inverter”, Proceedings of the Fifteenth National Power Systems Conference (NPSC), IIT Bombay, December
2008.
4.
H. S. Patel and R. G. Hoft, “Generalized harmonic elimination and voltage control in thyristor converters: Part Iharmonic elimination”, IEEE Transactions on Industrial Applications, Vol. 9, May/June 1973, pp. 310-317.
5.
H. S. Patel and R. G. Hoft, “Generalized harmonic elimination and voltage control in thyristor converters: Part IIvoltage control technique”,IEEE Transactions on Industrial Applications, Vol. 10, Sept./Oct. 1974, pp. 666-673.
6.
J.A. Mohammed, “Single Phase Inverter Optimum Solving SHEPWM Equations for Single Phase Inverter Using
Resultant Method”, Engineering & Technology, Vol. 26, No. 6, 2008, pp. 660-670.
7.
L. Li, D. Czarkowski, Y. Liu and P. Pillay, “Multilevel selective harmonic elimination PWM technique in seriesconnected voltage inverters”, Proceedings of Industry Applications Conference, Vol. 2, Oct 1998, pp. 1454-1461.
8.
N. Benaifa, H. Bierk, M. A. Rahim and E. Nowicki, “Analysis of Harmonic Reduction for Synchronized Phaseshifted
Parallel
PWM
Inverters
with
Current
Sharing
Reactors”,
Available
Online:
faculty.kfupm.edu.sa/EE/ahrahim/publications/Conference/106.EPC07-Nacer-PID497117.pdf.
9.
D.G. Holmes and T.A. Lippo, “Pulse Width Modulation for Power Converters- Principles and Practice”, IEEE
press Series on power engineering,Wiley Interscience Publication, 2003.
AUTHOR’S PROFILE
G. SUDHARANI was born in Rajahmundry, Andhra Pradesh, India on August 23 rd 1990. She received B.Tech
degree in Electrical and Electronics Engineering from Sasi Institute of Technology and Engineering, T.P.Gudem, affiliated
to JNTU University Kakinada, Andhra Pradesh, India in May 2011. She is currently Pursuing M.Tech in Power Electronics
and Drives at K L University, Vaddeswaram, and Guntur Dist., India.
RASOOLAHEMMED. SK was born in Nellore, Andhra Pradesh, India on November 20 th 1986. He received
B.Tech degree in Electrical and Electronics Engineering from Audisankara College of Engineering and Technology,
258
G. Sudha Rani & Rasool Ahemmed. Sk
Nellore, affiliated to JNTU University Hyderabad, Andhra Pradesh, India in May 2008 and Masters (M.Tech) in Power
Electronics and Drives from K.L.University, Vaddeswaram, Guntur Dist., India in May 2011. He is currently working as
Asst. Prof in K L University in Electrical and Electronics Engineering.