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Final Simulations to
Test AC Settling
TIPL 4405
TI Precision Labs – ADCs
Created by Luis Chioye, Art Kay
Presented by Peggy Liska
1
Agenda
1. SAR Operation Overview
2. Select the data converter
3. Use the Calculator to find amplifier and RC filter
4. Find the Op Amp
5. Verify the Op Amp Model
6. Building the SAR Model
7. Refine the Rfilt and Cfilt values
8. Final simulations
9. Measured Results
10. SAR Drive Calculator Algorithm
2
Expand the acquisition time to check settling
T
T
50.00m
50.00m
Verror
End of tacq
Adjusted End of tacq
Voltage (V)
Voltage (V)
actual end of tacq
0.00
0.00
Vacq A:(1.29u; 0)
Vconv A:(1.29u; 0)
Verror A:(1.29u; -30.020287u)
-50.00m
1.00u
The error is less than ½
LSB (-30uV). Will this
circuit work?
Don’t count on luck! The
signal isn’t really settled.
-50.00m
1.50u
Time (s)
2.00u
1.00u
1.50u
Time (s)
tacq change in simulation only to test for
marginal design. Not adjusted in real circuit.
3
Look at Op Amp Settling
T
1.00
Vacq
0.00
1.00
Vconv
0.00
100.00m
Verror
-100.00m
5.05
Amplifier settled to ½ LSB
or better after tacq ends.
Vopa
4.95
1.00u
1.50u
Time (s)
2.00u
4
Check settling for multiple cycles
T
1.00
Vacq
0.00
1.00
Vconv
Always discard
the first cycle.
Make sure that
settling is consistent
from cycle to cycle.
0.00
100.0u
Verror
-100.0u
5.05
Vopa
4.95
0.00
2.50u
Time (s)
5.00u
5
AC Input Signal Simulation Example
ADS8860 Input Model
Voa
-
+
V
Vcsh
+
Csh55p
-
+
tconv
tacq
tconv
+
tacq
+
Vref = 5V
tacq = 290ns
tconv=710ns
Vin _FS =5V
LSB = 5V / 2^16 = 76.3uV
1/2_LSB = 38.15uV

R6 96
AINM
PROBLEM:
• The phase shift introduced by the
amplifier and the RC circuitry make it
difficult to estimate the error or settling
signal
-
+
-

R2 22
VCVS1 1
+
+
+
Vdd 5.3
Csh+
55p
C4 4p
U1 OPA320
C5 4p
Vin
R8 96
C1 1n
+
++
R1 22
-
-
tconv

AINP
tacq

-
Vflt
Vacq
Vconv
6
Results for an AC Simulation: What about error
T
1.00
Vacq
0.00
1.00
Vconv
0.00
4.50
Vfilt
484.91m
4.50
Vin
500.00m
4.50
Vsh
0.00
0.00
50.00u
Time (s)
100.00u
7
AC Input Signal Simulation Example
T
2.60
2.57
Vin
Output
Vfilt
2.57
2.56
Output
Phase Shift
Vfilt
Vin
2.55
2.55
Vsh
2.53
Vsh
2.54
1.20u
1.60u
2.00u
2.50
0.00
1.00u
2.00u
3.00u
4.00u
PROBLEM:
• The phase shift introduced by the amplifier and
2.40u
2.80u
the RC circuits
make
it
difficult
to estimate the
Time (s)
settling error in the sample and hold
5.00u
Time (s)
6.00u
7.00u
8.00u
9.00u
3.20u
10.00u
8
AC Input Simulation Example
+
-
+

-
V
Verror
-
+
-
+
+
Vconv
-
+
tconv
tacq
R8 96
Csh+
55p
C4 4p
AINP
R2 22
VCVS1 1
+
+
-
C5 4p
C1 1n
U1 OPA320
Vdd 5.3

tconv
+
+
Vin
VCVS1 1
+
+
ADS8860 Input Model – phase shift only
Vflt
++
Vcsh

tacq
Vacq
R1 22
-
V
R6 96
AINM
-
+
Csh55p
R2 22
Vin
tconv
VCVS1 1
+
+
-
C5 4p
Vdd 5.3
Csh+
55p
C4 4p
U1 OPA320
tacq

R8 96
AINP
C1 1n
++
R1 22
-
Vflt
-
S/H switching with
conversions
ADS8860 Input Model
Voa
Csh55p
R6 96
-
+
V
Videal
“Ideal” signal
Sees phase shift without
sample and hold
AINM
9
AC Input Signal Simulation Example
“Ideal” Signal from
non-switching S/H
Phase difference no longer
present
“Ideal” Signal from
non-switching S/H
Sampled Signal
Sampled Signal
Solution:
• The “Ideal” Signal generated from non-switching
S/H has same phase as the Sampled Signal;
allowing the calculation of settling errors
10
Check the error for AC simulations
Place the cursor at the end of
an acquisition cycle. Generate
a legend. The error should be
less than ½ LSB.
Check the error at
multiple locations
T 4.50
Vsh
0.00
0.00
50.00u
Time (s)
100.00u
11
Agenda – next video…
1. SAR Operation Overview
2. Select the data converter
3. Use the Calculator to find amplifier and RC filter
4. Find the Op Amp
5. Verify the Op Amp Model
6. Building the SAR Model
7. Refine the Rfilt and Cfilt values
8. Final simulations
9. Measured Results
10. SAR Drive Calculator Algorithm
12
Thanks for your time!
Please try the quiz.
13