Download Low-Impedance Busbar Differential Protection Modeling

Low-Impedance Busbar Differential Protection
Modeling and Simulation Using ATP/EMTP
Alfredo Pianeta Escudero, Kleber Melo e Silva, Felipe Vigolvino Lopes
Department of Electrical Engineering (ENE)
University of Brası́lia, Brazil
[email protected], {klebermelo, felipevlopes}@unb.br
Abstract—This paper describes the modeling of a numerical
low-impedance busbar protection scheme by using the MODELS
language available in the software ATP. The instantaneous valuesbased differential protection algorithm was implemented, taking
into account external fault detection and zone selection logics. The
relay model also includes the data acquisition systems and signal
conditioning modules. The well known tripping logics 1-out-of-1
and 2-out-of-2 were used, which has been widely implemented
in numerical relays commercially available. Aiming to validate
the relay model, simulations of both internal and external faults
on a 230 kV substation with double busbar single breaker
arrangement were carried out using the ATP. The obtained
results reveal this type of modeling is useful for studies regarding
busbar differential protection schemes, as long as it provides
a closed loop simulation, allowing the evaluation of the relay
algorithm during power system operational conditions not readily
available in actual records.
Index Terms—Busbar protection, CT saturation, differential
protection, ATP, MODELS language.
I. I NTRODUCTION
Busbars play an major role in the power system operation,
as it is the point of connection of several power apparatus such
as lines and transformers. Among faults in electric systems,
those in busbars are cause of great concern for utilities, as they
typically lead to widespread blackouts [1], [2]. Therefore, studies regarding busbar protection functions by using simulation
platforms have aroused the interest of utilities, as it allows the
analysis of system operational conditions not readily available
in actual records.
In the open literature, the Electromagnetic Transients Programs (EMTP) have been shown to be a proper alternative
for modeling and simulating protective relays [3], [4], since
they use more thorough models of the system components and
provide suitable environments to link user-defined numeric
relay models. Most of the researches are focused on transmission lines protection modeling [5]-[8]. Besides, it was also
reported the use of EMTP to model the percentage differential
protection of power transformers and the high-impedance
differential protection of busbars [9], [10]. However, lowimpedance differential busbar protection has not been reported
yet. Therefore, this work aims to model a phase segregated
This work was supported by the Brazilian National Research Council
(CAPES).
low-impedance instantaneous values-based busbar differential
protection using the MODELS language of the Alternative
Transients Program (ATP).
In the proposed model, the data acquisition system, signal
conditioning module, external fault detection logic and zone
selection function were implemented [11], [12]. In order
to distinguish internal from external faults, the well known
tripping logics 1-out-of-1 and 2-out-of-2 were taken into account, which have been widely implemented in commercially
available busbar differential protection relays [13]. Several
fault scenarios were simulated in ATP, including adverse ones,
such as cases of external faults with severe current transformer
(CT) saturation, as well as external-to-internal evolving faults.
The obtained results validate the implemented relay model and
illustrate how it is useful for protection relays tests.
II. F UNDAMENTALS OF B USBAR D IFFERENTIAL
P ROTECTION
Numerical low-impedance busbar differential relays are
based on the Kirchhoff’s current law. Basically, these relays
compare the operating current iop with the restraining current
ires , in order to distinguish between internal and external
fault to the protection zone [13]. Fig. 1 shows an example
of the differential busbar protection (ANSI 87B) connection
in a simplified busbar arrangement, where the protection zone
is defined by the location and polarities of the CTs.
In this paper, instantaneous current values are used, providing very short tripping time (fast operation) of the busbar
Transformer 1
Transformer 2
CT4
CT5
Busbar
Protection Zone
87
CT1
Line 1
CT2
Line 2
CT3
Line 3
Figure 1. Differential protection zone of a simple busbar configuration.
k=1
where n is the number of network elements connected to the
busbar and ik represents the instantaneous current of the k-th
element.
Ideally, the relay must operate whenever iop exceeds a
minimum threshold current imin and a percentage K of ires :
iop > imin AND iop > K · ires
(3)
The threshold imin aims to prevent false trip for load
current, CT measurement errors, switching transients and
leakage currents provided by equipments such as surge arresters, auxiliary power transformers and voltage transformers.
Although these equipments are inside the busbar protection
zone, the currents flowing through them are not taken into
account to calculate iop and ires [11]. The percentage K, in
turn, is related to the relay sensitivity, so that the smaller the
value of K, the greater the relay sensitivity. Also, analyzing
(2), one can note that ires consists of a positive signal, but that
may be zero at some instants, since the monitored currents are
sinusoids, what can lead the relay to misoperate. In order to
overcome this drawback, instead of ires , its smoothed version
i∗res is traditionally used in (3), which is computed as shown
in the Appendix.
Aiming to improve the protection scheme reliability, the
trip command is issued only if the operating condition (3)
is fulfilled during a certain period of time, typically chosen
as 3 or 4 ms, regarding the CT time to saturate [13]. In
this paper, the two well known tripping logics are taken
into consideration: 1-out-of-1 and 2-out-of-2. Basically, (3)
is monitored in real time and a counter counts how many
times such condition is fulfilled during consecutive 4 ms along
the evaluated signals. Thus, if there is one count soon after
the fault inception, a trip signal is generated. This type of
operation is named 1-out-of-1 tripping logic (fast operation
mode). Also, if two counts are verified during a period smaller
than 8 ms at any period of the evaluated signals, the trip
command is also generated. This type of operation is named
2-out-of-2 tripping logic. Fig. 2(a) illustrates the behavior of
iop , i∗res and the trip commands generated by the 1-out-of-1
and 2-out-of-2 logics for an internal fault.
In case of an external fault, i∗res quickly increases, whereas
iop remain unchanged with the value almost equal to zero. If
this condition is verified during a specific period of time (e.g.,
4 ms) lesser than the CT time to saturate, an external fault is
detected, toggling the state of an external fault flag EF . Once
EF is set to 1 (one), the 1-out-of-1 logic is inhibited for a
period of time (secure operation mode), typically set to 150
1-out-of-1 2-out-of-2
operation operation
25
Current (pu)
4 ms
20
iop
4 ms
*
K.ires
t≤8 ms
15
10
5
Internal
Fault
Inception
0
1-1
2-2
70
80
90
100
110
Time (ms)
120
130
140
(a)
4 ms
10
5
4 ms
4 ms
15
Current (pu)
differential protection scheme. Traditionally, for busbars with
more than two network elements, numerical percentage differential relays compute the instantaneous values of iop and ires
as follows [13]:
n X (1)
iop = ik ,
k=1
n
X
ires =
|ik | ,
(2)
t>8 ms
No 2-out-of-2
operation
iop
*
K.ires
External
Fault
Inception
0
1-1
2-2
EF
70
80
90
100
110
Time (ms)
120
130
140
(b)
Figure 2. Tripping logics evaluation for: (a) an internal fault; (b) an external
fault with CT saturation.
ms, in such a way that the trip command can only be issued
by the 2-out-of-2 logic during this time [13].
An external fault with CT saturation is shown in Fig 2(b).
Even with the increase of iop due to the CT saturation, no
false trip signal is issued. In fact, being EF set to 1 (one), the
fast mode operation is inhibited and, since there are no double
counts along the signals, the 2-out-of-2 logic is not fulfilled.
III. A NALYZED P OWER S YSTEM D ESCRIPTION
Fig. 3 shows the 230 kV test power system evaluated in
this paper. The system consists of a double-bus arrangement
with single breaker and five switches in each branch, among
which one is a bypass switch used during circuit breaker
maintenances. Four perfectly transposed transmission lines
180 km long and two power transformers are connected to the
busbars, which are in turn connected by a bus coupler circuit
breaker that remains closed during the normal power system
steady-state regime. The ATPDraw interface was used to
model and simulate the test power system, whose parameters
are presented in Tables I and II. Power systems around the
busbar arrangement were represented by Thevenin equivalent
circuits connected to the remote terminals of each branch,
whose parameters are shown in Table III.
Current signals at each branch were taken from the CT
model C800 1200-5 [15], taking into account the saturation
characteristic. The secondary currents in each branch were
used as inputs of the differential protection functions implemented using the MODELS language. A time-step of 1µs
was used and a sampling frequency fs equal to 1920 Hz was
simulated, i.e. 32 samples/cycle for 60 Hz systems.
BUS 1
D1CB (NC)
CVTB1
D1TL2 (NO)
D1TF1 (NC)
D2TL1 (NO)
D2TL2 (NC)
D2TF1 (NO)
CTCB1
D1TF2 (NO)
D1TL3 (NC)
D1TL4 (NO)
D2TF2 (NC)
D2TL3 (NO)
D2TL4 (NC)
CCB
D1TL1 (NC)
CTCB2
D2CB (NC)
BUS 2
CVTB2
D4TL1
D4TL2
D4TF1
D5TL3
D4TF2
D3TL4
CBTL4
D5TF2
D3TL3
CBTL3
D5TF1
D3TF2
CBTF2
D5TL2
CBTF1
D5TL1
FAULT
D3TF1
CBTL2
D3TL2
CBTL1
D3TL1
D5TL4
D4TL3
D4TL4
CTTLP
CTTLP
CTTFP
CTTFP
CTTLP
CTTLP
CTBP
CTBP
CTBP
CTBP
CTBP
CTBP
FAULT
CVTTL
TL2
CVTTL
TF1
CTTFP
CTTLP
CVTTL
TL2RCB
I
TL1RCB
Transmission
Line 2 EQ
Transmission
Line 1 EQ
CTTFP
TF1RCB
Transformer 1
EQ
TL3
TF2
I
CTTLP
CVTTL
CVTTL
CVTTL
TL1
CTTLP
CVTTL
TF2RCB
TL4
CTTLP
CVTTL
TL3RCB
Transformer 2
EQ
Transmission
Line 3 EQ
TL4RCB
Transmission
Line 4 EQ
Figure 3. Single-line diagram of the evaluated double busbar single breaker arrangement.
TABLE I.
Z0 (Ω/km)
T RANSMISSION LINES PARAMETERS
Z1 (Ω/km)
0.532 + j1.541
B0 (µS/km)
0.098 + j0.510
TABLE II.
2.293
B1 (µS/km)
3.252
P OWER TRANSFORMER PARAMETERS
Transformer
S (MVA)
Primary (kV)
Secondary (kV)
TF1
TF2
450
150
500 (Y)
230 (Y)
230 (Y)
69 (∆)
Among the five disconnecting switches (DS) used in each
branch, besides the bypass switch, two DSs are used as busbar
selector switches and the two others, which operate normally
close (NC), which are used to isolate the circuit breaker during
its maintenance. This type of busbar arrangement provides
great operational flexibility and security, allowing the circuit
breaker maintenance without interrupting the energy supply.
However, as a consequence, the protection logic becomes more
complex, since the busbar can assume different configurations.
Therefore, the protection zones should be self-adapted in
accordance with the busbar configuration.
Under normal operating conditions, to distribute the load
uniformly throughout the busbar, some network elements are
connected to the bus 1 and other ones to the bus 2. For example, consider the test power system shown in Fig. 3. One can
see that the transmission line 1, transformer 1 and transmission
line 3 are connected to the bus 1. Such a connection is done
through the selector switches D1TL1, D1TF1 and D1TL3,
respectively, which operate normally closed (NC). Thus, the
protection zone Z1 encompasses line 1, transformer 1 and line
3, unless the selector switches D1TL1, D1TF1 and D1TL3
open and D2TL1, D2TF1 and D2TL3 close, which in turn
operate normally open (NO). By doing so, these equipments
are included in the protection zone Z2 . The same analysis
suits for the network elements connected to the bus 2, which
TABLE III.
S OURCE E QUIVALENTS
Source
Voltage (pu)
Z0 (Ω)
Z1 (Ω)
Line1
Line2
TF1
TF2
Line3
Line4
1.006 0◦
1.006 − 5◦
1.006 − 5◦
1.006 0◦
16.07 + j25.04
18.41 + j28.69
28.07 + j43.74
5.52 + j8.61
18.42 + j28.69
16.07 + j25.04
12.05 + j18.78
13.39 + j20.89
18.71 + j29.16
4.02 + j6.26
13.39 + j20.87
12.05 + j18.78
1.006 − 10◦
1.006 4◦
normally belong to the protection zone Z2 , but can be included
in the protection zone Z1 by operating properly the respective
selector switches.
Usually, each network element is connected to only one bus,
thereby the protection zones Z1 and Z2 are well-defined. Also,
a check-zone zone Z12 is typically used. It includes all the
elements connected to the busbar and supervises the operation
of both protection zones Z1 and Z2 , in such a way that the
Z1 and Z2 trip commands are issued to the associated circuit
breakers only if the check-zone also detects an internal fault.
Otherwise, if Z12 inhibits the operation of zones Z1 and Z2 .
In this paper, in order to implement the adaptive zone
selection, it was considered that each zone has a flag associated
with each CT, indicating whether the measured current should
be considered to compute the operation and restraint currents:
n
X
ZF
Z
F
iop = fk · i k ,
(4)
k=1
F
iZ
res =
n
X
,
fkZ · iF
k
(5)
k=1
where n is the total number of network elements connected to
ZF
F
the busbar; iZ
op and ires are operating and restraint currents of
the Zone Z and phase F , respectively; iF
k is the instantaneous
current value of the k-th zone Z and phase F and fkZ is the
zone selection flag.
TABLE IV.
A SSIGNMENT OF LOGIC STATES OF FLAGS
Branch
fk1
fk2
fk12
TL1
((D1TL1) AND (CBTL1 OR D5TL1))
OR ((PB) AND (CBTL1 OR D5TL1))
((D2TL1) AND (CBTL1 OR D5TL1))
OR ((PB) AND (CBTL1 OR D5TL1))
(CBTL1) OR (D5TL1 AND CCB)
TL2
((D1TL2) AND (CBTL2 OR D5TL2))
OR ((PB) AND (CBTL2 OR D5TL2))
((D2TL2) AND (CBTL2 OR D5TL2))
OR ((PB) AND (CBTL2 OR D5TL2))
(CBTL2) OR (D5TL2 AND CCB)
TF1
((D1TF1) AND (CBTF1 OR D5TF1))
OR ((PB) AND (CBTF1 OR D5TF1))
((D2TF1) AND (CBTF1 OR D5TF1))
OR ((PB) AND (CBTF1 OR D5TF1))
(CBTF1) OR (D5TF1 AND CCB)
TF2
((D1TF2) AND (CBTF2 OR D5TF2))
OR ((PB) AND (CBTF2 OR D5TF2))
((D2TF2) AND (CBTF2 OR D5TF2))
OR ((PB) AND (CBTF2 OR D5TF2))
(CBTF2) OR (D5TF2 AND CCB)
TL3
((D1TL3) AND (CBTL3 OR D5TL3))
OR ((PB) AND (CBTL3 OR D5TL3))
((D2TL3) AND (CBTL3 OR D5TL3))
OR ((PB) AND (CBTL3 OR D5TL3))
(CBTL3) OR (D5TL1 AND CCB)
TL4
((D1TL4) AND (CBTL4 OR D5TL4))
OR ((PB) AND (CBTL4 OR D5TL4))
((D2TL4) AND (CBTL4 OR D5TL4))
OR ((PB) AND (CBTL4 OR D5TL4))
(CBTL4) OR (D5TL1 AND CCB)
Coupling
Never
P B AND CCB
P B AND CCB
Never
Never
Never
TABLE V.
C IRCUIT B REAKER T RIPPING L OGIC
TL1 [(Z1 AND D1TL1) OR (Z2 AND D2TL1)]AND Z12 AND CBTL1
TL2 [(Z1 AND D1TL2) OR (Z2 AND D2TL2)]AND Z12 AND CBTL2
TF1 [(Z1 AND D1TF1) OR (Z2 AND D2TF1)]AND Z12 AND CBTF1
TF2 [(Z1 AND D1TF2) OR (Z2 AND D2TF2)]AND Z12 AND CBTF2
TL3 [(Z1 AND D1TL3) OR (Z2 AND D2TL3)]AND Z12 AND CBTL3
TL4 [(Z1 AND D1TL4) OR (Z2 AND D2TL4)]AND Z12 AND CBTL4
MODEL
NORM
MODEL
87B
MODEL
Smoothed
MODEL
Trip
GROUP
Circuit
Breaker
MODEL
CBStatus
MODEL
Setflags
In Table IV, all the expressions used to assign the logical
status of the flag fkZ of each zone are presented. Variables
CBTL1, CBTL2, CBTF1, CBTF2, CBTL3, CBTL4 and CCB
represent the logical status of the circuit-breakers of lines,
transformers and busbar coupling in the test power system.
They are set to 1 (one) when the circuit-breaker is closed
and set to 0 (zero) when it is open. Therefore, from (5), one
can verify that the CT secondary currents are only taken into
account for a given protection zone if the element is connected
to the correspondent bus.
There is another variable named ’Paralleled Buses’ (PB),
which is used in the logics shown in Table IV. This variable
is set to 1 (one) if both selector DSs of any network element
close simultaneously for transfer of the said network element
between buses, resulting a current that is not measured by
either zone may flow out of one bus into the other. This upsets
the current balance in both of the zones and may lead to a
false trip of both buses. Aiming to overcome this drawback,
whenever PB is set to 1 (one), both zones are expanded to
encompass the entire busbar [16], such as the check-zone does.
In case of the evaluated system, PB can be set as follows:
P B = (D1T L1 AN D D2T L1) OR (D1T L2 AN D D2T L2) OR
(D1T F 1 AN D D2T F 1) OR (D1T F 2 AN D D2T F 2) OR
(D1T L3 AN D D2T L3) OR (D1T L4 AN D D2T L4).
Table V shows the tripping logic of each circuit breaker
of the evaluated power system, in which Z1 , Z2 and Z12
represents the trip status of the protection zones.
IV. M ODELING OF D IFFERENTIAL BUSBAR PROTECTION
USING THE MODELS LANGUAGE
Fig. 4 shows the block diagram of the low-impedance busbar
differential protection scheme implemented in MODELS [17],
whose modules are described next.
MODEL
DSStatus
MODEL
DSBP
Figure 4. Model Block Diagram in ATPDraw.
A. Samples Normalization
This module deals with the current signals conditioning, so
that it can be divided into the following submodules:
• Auxiliary transformers: Receive as input the secondary
currents of the CTs. Its main function is to convert and
restrict the signals to suitable voltage levels for the A/D
converter treatment, that typically is ± 10 V.
• Analog Anti-Aliasing Filter: The filter is used to remove
the high frequency components to prevent the aliasing
effect in the sampling process. Here, it was used a
2nd Butterworth low-pass filter, which was implemented
through the resident function LAPLACE.
• Sample-and-Holder(S/H): This module samples the simulated current signals with a rate of 32 samples per cycle,
i.e. a sampling frequency fs equal to 1920 Hz. Therefore,
S/H is implemented in MODELS by setting the command
TIMESTEP MIN to 520.833 µs.
• A/D Converter: This module emulates the quantization
process of the samples in binary words of 16 bits as
described in [8].
• TAP: In order to deal with CTs with different current
ratios, this module normalizes the current samples to per
unit of the primary nominal current of those CT with the
highest current ratio [12], [14].
B. CB and DS states
This module gets the state of all the CBs and the bus selector
DSs of each network element connected to the busbar.
C. Set Flags
This module defines the flag of the protection zone fkZ ,
taking into account the tripping logics described in Table IV.
D. Relay 87B
In this module, the instantaneous normalized current values
are received with the associated enabling flags in order to
calculate the operating and restraint currents for Z1 , Z2 and
Z12 using (4) and (5), respectively.
E. Smoothed restraint current
Aiming to maintain the restraint current stable and without
oscillations, thereby misoperation of the differential protection
during external faults with CT saturation is avoided, it was
applied the filtering strategy described in [13] and [18], which
emulates the behavior of a charging and discharging of a
capacitor with a time constant τ of 60 ms, as described in
the Appendix.
F. Trip Logic
This module uses the tripping logics described in [13], such
that the logics 1-out-of-1 and 2-out-of-2 were implemented,
providing both sensibility for internal faults and security
for external faults with CT with saturation. Besides, it was
implemented an external fault detection logic, which inhibits
the operation of 1-out-of-1 tripping logic for 150 ms (secure
operation mode).
G. Circuit Breaker
This block was modeled by means of ideal switches controlled by MODELS, where the opening condition is active,
only when a tripping signal is received. The ideal switch does
not have a opening logic when the current equal or very
close to zero, therefore it was implemented. The interrupting
time for this model is 50 ms, corresponding to 3 cycles of
the fundamental frequency of 60 Hz. Then, each pole of the
breaker opens only when the current crosses by zero [6].
V. S IMULATIONS AND R ESULTS
The performance of the proposed model was evaluated for
both internal and external faults. All the figures were plotted
using the PlotXY/ATPDraw interface. Therefore, to better distinguish between the response of the 1-out-of-1 and 2-out-of-2
tripping logics, different scale factors were used in plotting.
Also, legends are presented at the bottom of each figure
using the following nomenclature: current signals are shown as
IXZφ, where X represents either the operating current (OP)
or restraint current (RS), respectively; Z represents either the
protected zone 1 (Z1) or zone 2 (Z2), respectively; φ assumes
A, B or C according to the system phases. Moreover, the
following notation is used for tripping signals: TY φZ, where
φ and Z are the same codes described before and T assumes
either 11 or 22 to represent the tripping logics 1-out-of-1 and
2-out-of-2, respectively.
A. Internal Fault
An internal AG fault at Bus 1 (Z1 ) was considered in 80
ms. Fig. 5 shows the waveforms of the operating and restraint
currents for the phase A and B elements of the Z1 . Because of
space limitations, the Phase C is not shown, the behavior is the
same of the phase B. As can be seen, for the healthy phases,
the restraint current increases and the operating current remain
unchanged with value near zero, so that the external fault
detection logic is fulfilled, thereby EF is asserted 4 ms after
the fault is detected. Still, the operating and restraint currents
increase simultaneously for the faulted phase, so that both 1out-of-1 and 2-out-of-2 tripping logics issue a trip, wherein
1-out-of-1 provides the fast trip just 4 ms after the fault is
detected. For the sake of simplicity, only the response of the
Z1 are shown, but all the phase elements of the Z2 detect
external fault. On the other hand, the elements of the checkzone respond as the same way as Z1 elements, allowing the
trip command is sent to the breakers, that open approximately
3 cycles after (Fig. 6).
B. External Fault
In case of an external AG fault was simulated at 80 ms,
no trip command was activated, so that both protection zones
remain stable (Fig. 7). In fact, for external faults, unless
CT saturates, only the restraint current increases thereby the
external fault detection logic is fulfilled.
Phase A
20
10
0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPAZ1
0,15
0,20
0,15
0,20
[s]
0,25
m:IRSZ1A
Phase B
0,6
0,4
0,2
0,0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPBZ1
1,5
[s]
0,25
m:IRSZ1B
External Fault Z1
1,0
0,5
0,0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:FXTAZ1
0,15
m:FXTBZ1
0,20
[s]
0,25
[s]
0,25
m:FXTCZ1
TRIP 1-out-of-1 AND 2-out-of-2
1,5
1,0
0,5
0,0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:T11AZ1
m:T11BZ1
0,15
m:T11CZ1
0,20
m:T22AZ1
m:T22BZ1
Figure 5. Internal AG fault in B1 at 80 ms.
m:T22CZ1
CBTL1
2000
[A]
1300
1,5
1,0
600
-100
0,5
-800
-1500
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
c:CBTL1A-BL1A
0,15
c:CBTL1B-BL1B
0,20
[s]
0,25
c:CBTL1C-BL1C
0,05
(file BusDiffProtModels.pl4; x-var t)
CBTL3
2000
[A]
1300
0,0
0,00
0,10
m:FXTAZ1
0,15
m:FXTBZ1
m:FXTCZ1
0,20
m:FXTAZ2
m:FXTBZ2
[s]
0,25
m:FXTCZ2
0,5
0,0
600
-0,5
0,00
-100
0,05
(file BusDiffProtModels.pl4; x-var t)
0,5
0,10
m:T11AZ1
0,15
m:T11BZ1
m:T11CZ1
0,20
m:T11AZ2
m:T11BZ2
m:T22AZ2
m:T22BZ2
[s]
0,25
m:T11CZ2
-800
-1500
0,00
0,0
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
c:CBTL3A-BL3A
0,15
c:CBTL3B-BL3B
0,20
[s]
0,25
c:CBTL3C-BL3C
CBTF1
12
-0,5
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
[kA]
0,10
m:T22AZ1
0,15
m:T22BZ1
m:T22CZ1
0,20
[s]
0,25
m:T22CZ2
Figure 7. External AG fault in TL1 at 80 ms.
6
0
Phase A
16
-6
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
c:CBTF1A-BT1A
0,15
c:CBFT1B-BT1B
0,20
[s]
0,25
8
CCB
6000
[A]
4000
4
2000
0
0,00
0
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPAZ1
0,05
0,10
0,15
0,20
(file BusDiffProtModels.pl4; x-var t)
c:CBCCBA-BCCA
c:CBCCBB-BCCB
c:CBCCBC-BCCC
[s]
0,15
0,20
[s]
0,25
0,15
0,20
[s]
0,25
0,15
0,20
[s]
0,25
0,20
[s]
0,25
[s]
0,25
m:IRSZ1A
Phase B
10
-2000
-4000
0,00
12
c:CBTF1C-BT1C
0,25
5
Figure 6. Internal AG fault in B1 at 80 ms, current through Zone 1 CBs.
C. External Fault with CT Saturation
In case of external faults with CT saturation, the operating
current does not remain stable with value near zero. In fact,
the operating current may be greater than the restraint current
during the saturation period, what may leads to a false trip
command issuing. Therefore, the external fault detection logic
must be performed to block the fast operation mode through
the 1-out-of-1 tripping logic, guaranteeing the security of the
protection scheme as a whole.
In Fig. 8 is depicted the performance of the Z1 elements for
an ABC external fault with CTs saturation. One can see that
the EF flag is set approximately 4 ms after the fault inception,
blocking the 1-out-of-1 tripping logic. When the CT saturation
takes place, the operating current becomes erroneously greater
than the restraint current, so that the operation condition (3)
is fulfilled. However, since two consecutive saturation periods
do not occur before 8 ms, the 2-out-of-2 tripping logic is not
fulfilled and the protection scheme remain stable.
D. Evolving Fault
An external AG fault in the TL1 was simulated at 80 ms
that evolve to an internal ABG busbar fault at 110 ms on the
Bus 1. Initially the external fault detection logic of both Z1
and Z12 are asserted, thereby the 1-out-of-1 tripping logic is
blocked during 150 ms (secure operation mode). Then, after
0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPBZ1
m:IRSZ1B
Phase C
15
10
5
0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPCZ1
m:IRSZ1C
External Fault Z1
1,5
1,0
0,5
0,0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:FXTAZ1
0,15
m:FXTBZ1
m:FXTCZ1
TRIP 1-out-of-1 AND 2-out-of-2
0,5
0,0
-0,5
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:T11AZ1
m:T11BZ1
0,15
m:T11CZ1
0,20
m:T22AZ1
m:T22BZ1
m:T22CZ1
Figure 8. External ABC fault in TL1 at 80 ms, with CT saturation.
the internal fault initiates, a trip command is issued by the
2-out-of-2 logic two consecutive half-cycle of 4 ms each
separated by 8 ms is detected, as shown in Fig. 9.
Phase A
15
R EFERENCES
10
5
0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPAZ1
0,15
0,20
[s]
0,25
0,15
0,20
[s]
0,25
0,15
0,20
[s]
0,25
m:IRSZ1A
Phase B
20
10
0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPBZ1
m:IRSZ1B
Phase C
0,9
0,4
-0,1
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:IOPCZ1
m:IRSZ1C
External Fault Z1
1,5
1,0
0,5
0,0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:FXTAZ1
0,15
m:FXTBZ1
0,20
[s]
0,25
[s]
0,25
m:FXTCZ1
TRIP 1-out-of-1 AND 2-out-of-2
1,5
1,0
0,5
0,0
0,00
0,05
(file BusDiffProtModels.pl4; x-var t)
0,10
m:T11AZ1
m:T11BZ1
0,15
m:T11CZ1
0,20
m:T22AZ1
m:T22BZ1
m:T22CZ1
Figure 9. External AG fault with CT saturation in TL1 at 80 ms evolving to
an internal ABG in Bus 1 at 110 ms.
VI. C ONCLUSIONS
In this paper it was presented the modeling and simulation of a low-impedance busbar differential protection with
MODELS language. Different ATPDraw simulations were
carried out in a 230 kV power system to test the proposed
implementation. The results reveal a good performance for
both internal and external faults, even in cases of external
faults with CT saturation and evolving faults. With the use of
proposed zone selection can be achieved a robust and flexible
implementation of protection zone supervision, associated with
the CB and DS status. An important advantage of this type
of modeling lies in the fact it provides the evaluation of the
relay algorithm during power system operational conditions
not readily available in actual records, guaranteeing the correct
operation of the relay software.
[1] Paul M. Anderson, Power System Protection, Piscataway, New Jersey,
USA: IEEE Press Series on Power Engineering, 1999.
[2] Cigré TB431, Modern Techniques for protecting busbars in HV networks,
Cigré Study Committee B5, working group B5.16, Sibui, Romania, 2010.
[3] Cigré Working Group B5.17, ”Relay Software models for use with
electromagnetic transient analysis programs,” Tech. Rep., 2006.
[4] W. G. C. of the System Protection Subcommittee of the IEEE PSRC,
”Software Models for Relays”, IEEE Transactions on Power Delivery,
vol. 16, no.2, Apr 2001.
[5] C.-H. Kim, M.-H. L , R. K. Aggarwal, and A. T. Johns, ”Educational
use of emtp models for the study of a distance relaying algorithm for
protecting transmission lines, IEEE Transactions on Power Systems. vol.
15, no. 1, Feb 2000.
[6] K. M. Silva, W. L. A. Neves, and B. A. Souza, ”Emtp applied to evaluate
three-terminal line distance protection schemes,” IPST: International
Conference on Power Systems Transients, Lyon, 2007.
[7] X. Luo and M. K. Zunovic, ”Interactive protection system simulation
using atp models and c++”. Transmission and Distribution Conference
and Exposition, Dallas, Texas, USA, May 2006.
[8] Perez, S. G. A. Modeling Relays for Power System Protection Studies.
PhD Thesis University of Saskatchewan, Saskatoon, Canada, 2006.
[9] K. A. Tavares and K. M. Silva, ”Modeling and Simulation of the Differential Protection of Power Transformers in EMTP Softwares,” DPSP:
International Conference on Developments in Power System Protection,
Birmingham, UK, 2012.
[10] M. T. S. Alvarenga, P. L. Vianna and K. M. Silva, ”High-Impedance Bus
Differential Protection Modeling in ATP/MODELS,” Engineering. vol. 5,
pp. 37-42, 2013.
[11] K. Behrendt, D. Costello, and S. E. Zocholl, ”Considerations for using
high-impedance or low-impedance relays for bus differential protection,”
Schweitzer Engineering Laboratories, Inc., Pullman, Washington USA,
Tech. Rep., 2010
[12] H. J. Altuve and E. O. Schweitzer, Modern Solutions for Protection,
Control and Monitoring of Electric Power Systems. Pullman, USA:
Schweitzer Engineering Laboratories, Inc., 2010, pp 155-173.
[13] G. Ziegler, Numerical Differential Protection: Principles and Applications, 2nd ed. Berlin, Germany: Siemens, 2012.
[14] A. Guzmán, B. Quin and C. Labuschagne, ”Reliable Busbar Protection
with Advanced Zone Selection,” IEEE Transactions on Power Delivery,
vol. 20, pp. 625 - 629, April 2005.
[15] IEEE Power System Relaying Committee, EMTP reference models
for transmission line relay testing, Rep. no. WGD10, 2004. [Online].
Available: http://www.pes-psrc.org
[16] IEEE Power & Energy Society, Power System Relaying Committee.
IEEE Guide for Protective Relay - Applications to Power System Buses,
New York, 2009.
[17] L. Dube, Models in ATP: Language Manual, 1996.
[18] A. Kumar and P. Hansen, Digital buz-zone protection, IEEE Computer
Applications in Power, vol. 6, pp. 2934, 1993.
VII. A PPENDIX
The pseudocode of i∗res computation is presented next:
input : ires Zφ , with Z(1 or 2) and φ(A, B or C), τ
output: i∗res Zφ
var : A0 ires Zφ , Max ires Zφ ,t Max ires Zφ
if Max ires Zφ < ires Zφ then
Max ires Zφ = ires Zφ ;
t Max ires Zφ = t;
A0 ires Zφ = ires Zφ ;
else
Max ires Zφ =
A0 ires Zφ × [1 − (60/τ ) × (t − t Max ires Zφ )];
end
i∗res Zφ = Max ires Zφ