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Download Test Method Improvement Approach for VDM++ Specification
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Test Method Improvement Approach for VDM++ Specification Soyeon Lee, Yoichi Omori, Shigeru Kusakabe, Keijiro Araki Graduate School of Information Science and Electrical Engineering Kyushu University Abstract We discovered the problems of VDM++ testing from the development process of FeliCa. To solve these problems, we apply the existing test methods toward VDM++ specification. Also, the framework will be constructed to support these methods. For eradicating contradiction and ambiguity from the software's specification and improving quality of products, formal method was introduced into the development process of FeliCa(Contactless IC chip technology developed by Sony). In this process, the model described by VDM++ was generated and then it was tested statically and dynamically by interpreter of IFAD VDM++ Toolbox. However, absence of consequent policies for testing, and lack of basic libraries were discovered as a problem that should be solved in this process. In this research, we propose the test method for VDM++ and set up the ground for extracting test cases automatically from formal description. This research is aimed at improving the test process for formal specification and making the whole process more efficient. First, we inspected the character of VDM++. VDM++ has three main characters. VDM++ is (1) a formal language for describing specification (2) a model-based language for confirming intended behavior (3) an object-oriented language that has class as a unit. To make the most of these characters, we investigated the existing test methods that fit VDM++. As a result of investigation, we selected equivalence partitioning, boundary value analysis, and cause-effect graph. In order to apply these three methods to VDM++ specification, the framework for VDM++ test will be constructed.
