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VS
. Megapixel Mobile Camera Module
PRELIMINARY DATA
Features
H x V active pixels . m pixel size, / inch optical format RGB Bayer color filter array Integrated
bit ADC Integrated digital image processing functions, including defect correction, lens
shading correction, image scaling, demosaicing, sharpening, gamma correction and color
space conversion Embedded camera controller for automatic exposure control, automatic
white balance control, black level compensation, / Hz flicker cancelling and flashgun support
Fully programmable frame rate and output derating functions Up to fps SXGA progressive
scan Low power fps VGA progressive scan ITUR BT. YUV YCbCr with embedded syncs,
YUV YCbCr , RGB , RGB , Bayer bit or Bayer bit output formats bit parallel video interface,
horizontal and vertical syncs, MHz max clock Twowire serial control interface Onchip PLL, .
to MHz clock input Analog power supply, from . to . V Separate I/O power supply, . or . V
levels Integrated power management with power switch, automatic poweron reset and
powersafe pins Low power consumption, ultra low standby current Tripleelement plastic lens,
F ., Horizontal field of view . x . x .mm fixed focus camera module with embedded passives
wire FPC attachment with boardtoboard connector, mm total length pin ITU shielded socket
options
Description
The VS is an SXGA CMOS color digital camera featuring low size and low power
consumption targeting mobile applications. This complete camera module is ready to
connect to camera enabled baseband processors, backend IC devices or PDA engines.
Applications
Mobile phone PDA
Ordering codes
Part number VSPLP VSQKP Description SMOP VGA x, flex SMOP VGA x, socket
February
Rev
/
www.st.com
This is preliminary information on a new product now in development or undergoing
evaluation. Details are subject to change without notice.
Contents
VS
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System architecture .
.......................................
. . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video pipe . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor functions . . . . . . . . . . .
..........................
Operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . Streaming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode transitions .
...........................................
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sensor mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Image size. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cropping module. . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zoom. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . Frame rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . Horizontal mirror and vertical flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. Video pipe setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Context
switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ViewLive Operation. .
..............................................
Output data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line / Frame Blanking Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . YUV data
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . YUV . . . . . . . . . . . . . . . . . . .
....................................
/
Rev
VS
Contents
RGB and Bayer bit data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manipulation of
RGB data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dithering . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bayer bit. . . . . . . . . . . . . . . . . . . . . . . . . . .
............................
Data synchronization methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prevention of
false synchronization codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode ITU compatible . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . Mode Logical DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . VSYNC and HSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . Horizontal synchronization signal HSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vertical
synchronization VSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pixel clock PCLK . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master / Slave operation of PLCK. . .
..................................
Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initial power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum
startup command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host communication IC control interface . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed
overview of the message format . . . . . . . . . . . . . . . . . . . . . . . . Data valid . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start S and Stop P conditions . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Types of messages .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random location, single data write . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . Current location, single data read . . . . . . . . . . . . . . . . . . . . . . .
.......
. Random location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple location
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple location read stating from
the current location . . . . . . . . . . . . . .
Rev
/
. . . . . . . . . . . . . . . . . . . . . . . . . External clock . . . . . . . . . . . . . . . . DC electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC slave interface . . . . . Low level control registers . . .
. . / Rev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents VS . . . . . . . . . . Electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . Package mechanical data . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . User interface
map . . . . . . . . . . Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . Parallel data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple location read starting
from a random location . . . . . Chip enable . . . Optical specifications . . . . . . . . . . . . . . . . . . . .
..........................................................................
. . . . . . . . . . . . Register map . . .
. . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical current consumption . . . . . . . . . . . .
. . . . . . . . Table . . . . . . Table . . . . . . . . Table . . . . . . . . Table . . Table . . . . . . Table . Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exposure controls . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . Table . . . . . . Host interface manager status Read only. . . . Pipe setup bank . . . . . . . .
. . . Sensor setup. . . . . . ViewLive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . Table . . . . . . Table . . . . . . . . . . . . . . . . . . . .
. . Pipe RGB To YUV matrix manual control . . . . . . . . . . . . . . . . Table . . . . . . . . . . . White
balance control parameters . . . . . . . . . . . . . . . . . . . Supply specifications . . . . . . . . . . . . . . . .
. . . . Output formatter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. Table . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . Table . . . . . . . . . . . . . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device
parameters read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .Sensor mode SXGA fps. . . . . . . Table . . . . . . . Pipe RGB to YUV
matrix manual control . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table . . . . . . . . . . . External clock .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host interface manager control. . . . . . Fade to
black . . . . . . . . . . . .Sensor mode VGA fps . . . . . . Pipe gamma manual control . . . . Table . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .embedded synchronization code definition . . . .
Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table . .
. . . . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video timing control .
. . . . . . . Table . . . . Scythe filter controls . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . Table . . . Typical current consumption . . . . . . . . . . . . . . . . . . .
. . . Flash status . . . Table . Absolute maximum ratings . . . . . . . . . . . Peaking control . . . . . .
..........................................................................
. . . . . . . . . . . . . . . . . . . . . . . . . Image stability read only . . . . . . . . . . . Table . . . . . . .
Demosaic control . . NoRA controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VS List of tables
List of tables Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITU
embedded synchronization code definition even frames. . . . . . . . . . . . . . . . . . . . . Mode . . . .
. . . . . . . . . . . . . . . . . . . . . . Pipe setup bank . . . . . . . . . . . Table . . . . . Table . . . . . . . . . . . . .
. . . . . . . . . . . . . Viewlive status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS signal description
of pin flex connector . . . . . . . . . . . . . . . . . . . . . . Flash control . Pipe Gamma manual control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Colour matrix dampers . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . Table . DC electrical characteristics . . . . Video timing parameter host
inputs . . Jack filter controls . . . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . Power management . . . . . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . .
. . . Static frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . Table . . . . . . Optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . Table
. . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Run mode control . . . . .
. . . . . . . . . . Table . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table . . . . . . . . . . . . . . . . Lowlevel control registers . . . . . . . . . . . . . . . . . . . . . Serial
interface voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table . . . . . . . . . . . . . . .
. . . Table . . . . . . . Rev / . . . . . . . . . . . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . Parallel data interface timings. . . . . . . . . . Frame dimension parameter
host inputs . . . . . . Automatic Frame Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table . . . . . . . ITU embedded synchronization code
definition odd frames. . . . . . . . Mode setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.....
. . . . . . . . . . . . . . . . . .List of tables Table . . . . . . . . . . . . VS Document revision history . . . .
. . . . . . . . . . . . . / Rev . . . .
. . Figure . . . . YUV format encapsulated in ITU stream . . bit data multiple location write . .
Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package outline FPC module VSPLP. . . . . . . . . . .
. . . . bit index. . . . . . . . . . . ITU frame structure with even codes . . . . . . Write message . . . . .
. . . . . . . . . . . . Figure . . . . . . . . . Figure . . . .VS List of figures List of figures Figure . . . .
Figure . . . . . . . . . . . . . . . . SDA/SCL rise and fall times . . . . . . . . VS simplified block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit data
random index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed
overview of message format. . . Package outline FPC module VSPLP . . . . . SDA data valid .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure . . . . . . . . Mode frame
structure VGA example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure . . Figure . . . . . . . Current location. . . . . . . . . . . . . . Timing specification . . . . . . . . . . .
. . . . . . . . . . . . . . . . HSYNC timing example . . . . . . . . . . . single write . . . . . . . . . . . . . . . . . .
. . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . Figure . . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure . . . . .
. . . . Bayer output . . . . . . . . . . . . . . . . . . . . . . Multiple location read . Figure . . . . . . .
ViewLive frame output format . . . . . . . Figure . . . . . . . . . Figure . . . . Figure . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QCLK options . . . Figure
. . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal register index space. . .
. . . . . . . . RGB and Bayer data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . bit index. . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . .
Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . . Figure . . . Mode frame structure VGA
example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure . . . . . . . . . . .
. . Y Cb Cr data swapping options register x bYuvSetup . . . . . . . . . . Figure . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . Figure . . . . . . Parallel data
output video timing. . . . . . . . . . . . . . . . . . Read message . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . Multiple location read starting from a random location . . . . . Package
outline socket module VSQKP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. Random location. . . Figure . . . . . . . . . . . . . . . . . . . VSYNC timing example . . . Package
outline socket module VSQKP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . single read . . . . . . . . . . . Standard Y Cb Cr data order . . . . . . . . . . Data
acknowledge . . . . . . . . . . . . . . . . Figure . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . Power up sequence . . . . . . . . . Voltage
level specification . . . . . . . . . . . . . . Rev / . . . . . . . . . . . . . . . . . . . Device addresses . . . . . .
Figure . . . . . . . . . . . . . . . . . . . . . . . . . single data read . . . . . . . . . . . . START and STOP
conditions . . . . . . . . . . . Crop controls . . . . . . . . . . . . . . . . . Qualification clock . State
machine at power up and user mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure . . . .
V and .Overview VS . YUV frame format. The VS camera module uses STs nd generation
SmOP packaging technology the sensor. The integrated PLL allows for low frequency
system clock. to . V single supply camera or as a . a digital image processor and camera
control functions. with ITUR BT. The device contains an embedded video processor and
delivers fully color processed images at up to frames per second SXGA and up to fps VGA.
The video data is output over an bit parallel bus in RGB. m CMOS Imaging process.
particularly mobile phone applications. It also includes a wide range of image enhancement
functions. The VS is controlled via an IC interface. The VS is capable of streaming SXGA
video up to fps. Typically. V or . the VS can operate as a . V analog power supply. An input
clock is required in the range . designed to ensure high image quality. V and a digital supply
of either . V dependant on interface levels required. Overview Description The VS is a SXGA
resolution CMOS imaging device designed for low power systems. The VS requires an
analogue power supply of between . lens and passives are assembled. it integrates a
highsensitivity pixel array. YCbCr or bayer formats. V interface / . V interface and requires a .
tested and focused in a fully automated process. V to . MHz to MHz. these include Automatic
exposure control Automatic white balance Lens shading compensation Defect correction
algorithms Demosaic Bayer to RGB conversion Colour space conversion Sharpening
Gamma correction Flicker cancellation NoRA Noise Reduction Algorithm Intelligent image
scaling / Rev . and flexibility for successful EMC integration. V supply camera. Manufactured
using ST . It supports both . allowing high volume and low cost production.
Pad VS signal description of pin flex connector Table Pad name GND HSYNC VSYNC SCL
CLK SDA VDD AVDD PCLK CE D D GND D D D D D D FSO I/O PWR OUT OUT IN IN I/O
PWR PWR OUT IN OUT OUT PWR OUT OUT OUT OUT OUT OUT OUT Analogue ground
Horizontal synchronization output Vertical synchronization output IC clock input Clock input .
Table . V Analogue supply .MHz to MHz IC data line Digital supply . V OR .. V Pixel
qualification clock Chip enable signal active HIGH Data output D Data output D Digital
ground Data output D Data output D Data output D Data output D Data output D Data output
D Flash output Description The package details and electrical connections of the pin socket
device are shown in Figure and Figure . Rev / .VS Electrical interface Electrical interface The
VS FPC board to board connector has electrical connections which are listed in Table . V to .
the package details of the flex connector are shown in Figure andFigure .
The external host communicates with this microprocessor over an IC interface. VS simplified
block diagram Clock Generator IC Interface IC SDA SCL CLK CE VDD GND RESET VREG
Microprocessor Video Timing Generator Statistics Gathering FSO AVDD GND SXGA Pixel
Array Video Pipe VSYNC HSYNC PCLK D . The whole system is controlled by an embedded
microprocessor that is running firmware stored in an internal ROM. Realtime information
about the video data is gathered by a statistics engine and is available to the microprocessor.
Operation A video timing generator controls a SXGAsized pixel array to produce raw bayer
images. The microprocessor does not handle the video data itself but is able to control all the
functions within the video pipe.System architecture VS System architecture The simplified
block diagram of VS is shown in Figure . The video pipe contains a number of different
functions explained in detail later. At the end of the video pipe data is output to the host
system over an bit parallel interface along with qualification signals. / Rev . The analogue
pixel information is digitized and passed into the video pipe. VS includes the following main
blocks SXGAsized pixel array Video timing generator Video pipe Statistics gathering unit
Clock generator Microprocessor Figure . The processor uses this information to perform
realtime image control tasks such as automatic exposure control.
NoRA The noise reduction module implements an algorithm based on the humanvisual
system and adaptive pixel filtering that reduces perceived noise in an image whilst
maintaining areas of high definition. Note The interline period is not guaranteed consistent for
all derating ratios. AntiZipper The demosaic process produces an RGB frame with a noise
signal at pixel frequency. This is designed to reduce the peak output data rate of the device
by spreading the data over the whole frame period and allowing a subsequent reduction in
output clock frequency. By default the antivignette setting matches the lens used in this
module and does not need to be adjusted.x to x the input number of pixels and lines. Gain
and offset This function is used to apply gain and offset to data coming from the sensor
array. Gamma is user adjustable. As a general rule the allowable derating factor is equal to
the square of the scaling factor. Sharpening This module increases the high frequency
content of the image in order to compensate for the lowpass filtering effects of the previous
modules.VS System architecture . Crop This function allows the user to select an arbitrary
Window Of Interest WOI from the SXGAsized pixel array. It YUV conversion This module
performs color space conversion from RGB to YUV. in both the horizontal and vertical
domain. Derating The VS contains an internal derating module. Demosaic This module
performs an interpolation on the Bayer data from the sensor array to produce a sRGB data.
Defect correction This function runs a defect correction filter over the data in order to remove
defects from the final output. Antivignette This function is used to compensate for the radial
rolloff in intensity caused by the lens. The scaler is capable of downscaling from . Rev / . The
microprocessor applies gain and offset values are controlled by the automatic exposure and
white balance algorithms. Video pipe The main functions contained within the VS video
processing pipe are as follows. It is fully accessible to the user. Dither This module is used to
reduce the contouring effect seen in RGB images with truncated data. To remove this
artefact an antizipper filter is employed. of the bayer image data this is achieved by
samplerate conversion. At this point an antialias filter is applied. This module applies a
programmable gain curve to the output data. The maximum achievable derating factor is x
for an equivalent scale factor of x downscale. This means the host capture system must be
able to cope with use of the sync signals or embedded codes rather than relying on fixed line
counts. Scaler The scaler module performs real time downscaling. in steps of /. This function
has been optimized to attain the minimum level of defects from the system and does not
need to be adjusted. note that the crop size should not be smaller that the output size. It is
used to control the contrast and color saturation of the output image as well as the fade to
black feature.
System architecture
VS
Output formatter This module controls the embedded codes which are inserted into the data
stream to allow the host system to synchronize with the output data. It also controls the
optional HSYNC and VSYNC output signals.
.
Microprocessor functions
The microprocessor inside the VS performs the following tasks Host communication handles
the IC communication with the host processor. Video pipe configuration configures the video
pipe modules to produce the output required by the host. Automatic exposure control In
normal operation the VS determines the appropriate exposure settings for a particular scene
and outputs correctly exposed images. Flicker cancellation The /Hz flicker frequency present
in the lighting due to fluorescent lighting can be cancelled by the system. Automatic white
balance The microprocessor adjusts the gains applied to the individual color channels in
order to achieve a correctly color balanced image. Frame rate control VS contains a firmware
based programmable timing generator. This automatically designs internal video timings,
PLL multipliers, clock dividers etc. to achieve a target frame rate with a given input clock
frequency. Optionally an automatic frame rate controller can be enabled. This system
examines the current exposure status, integration time and gain and adapts the frame rate
based on that. This function is typically useful in lowlight scenarios where reducing the frame
rate extends the useful integration period. This reduces the need for the application of analog
and digital gain and results in better quality images. Dark calibration The microprocessor
uses information from special dark lines within the pixel array to apply an offset to the video
data and ensure a consistent black level. Active noise management The microprocessor is
able to modify certain video pipe functions according to the current exposure settings
determined by the automatic exposure controller. The main purpose of this is to improve the
noise level in the system under low lighting conditions. Functions which strength is reduced
under low lighting conditions e.g. sharpening are controlled by dampers. Functions which
strength is increased under low lighting conditions are controlled by promoters. The fade to
black operation is also controlled by the microprocessor
/
Rev
VS
Operational modes
Operational modes
VS has a number of operational modes. The power down mode is entered and exited by
driving the hardware CE signal. Transitions between all other modes are initiated by IC
transactions from the host system or automatically after timeouts.
Figure .
State machine at power up and user mode transitions
Supplies turnedon amp CE pin LOW Supplies Off Supplies turnedoff
PowerDown
Supplies turnedoff
CE pin LOW Standby Uninitialised CE pin HIGH
State Machine at powerup IC controlled user mode transitions
It is possible to enter any of the user modes direct from the uninitialised state via an IC
command
Stop Mode
Snapshot
Pause Mode
Flashgun
Note Depending on the snapshot exit transition settings the device will revert to RUN or
PAUSE state automatically after snapshot
Run Mode
Host initiated state changes System state changes
Power Down/Up The power down state is entered from all other modes when CE is pulled
low or the supplies are removed. During the powerdown state CE logic
The internal digital supply of the VS is shut down by an internal switch mechanism. This
method allows a very low powerdown current value. The device input / outputs are failsafe,
and consequently can be considered high impedance.
Rev
/
Operational modes During the powerup sequence CE logic
VS
The digital supplies must be on and stable. The internal digital supply of the VS is enabled by
an internal switch mechanism. All internal registers are reset to default values by an internal
power on reset cell.
Figure .
Power up sequence
POWER DOWN standby uninitialised mode
VDD .V/.V AVDD .V CE
tt
t CLK SDA SCL t Constraints t gt ns t gt ns t gt ns t gt TBC ms t gt TBC ms low level
command enable clocks setup commands t
STANDBY mode The VS enters STANDBY mode when the CE pin on the device is pulled
HIGH. Power consumption is very low, most clocks inside the device are switched off. In this
state IC communication is possible when CLK is present and when the microprocessor is
enabled. All registers are reset to their default values. The device I/O pins have a very
highimpedance. Uninitialised RAW The initialize mode is defined as supplies present, the CE
signal is logic and the microcontroller clock has been activated. During initialize mode the
device firmware may be patched. This state is provided as an intermediary configuration
state and is not central to regular operation of the device. The analogue video block is
powered down, leading to a lower global consumption STOP mode This is a low power
mode. The analogue section of the VS is switched off and all registers are accessed over the
IC interface. A run command received in this state automatically sets a transition through the
Pause state to the run mode.
Note
The device must be in Stop mode to adjust output size.
The analogue video block is powered down, leading to a lower global consumption.
/
Rev
Independent of mode. white balance and darkcal systems are stable. Streaming modes
RUN mode This is the fully operational mode. The analogue video block is powered down.
format and reconstruction settings in the relevant pipe setup bank. VS supports the following
flashgun configurations Torch Mode . the array is configured for use with an external
flashgun. . The snapshot mode must not be entered into while viewlive is selected. leading to
a lower global consumption Note The PowerManagement register can be adjusted in PAUSE
mode but has no effect until the next RUN to PAUSE transition. A flash is triggered and a
single frame of data is output and the device automatically switches to Pause Mode. This
mode is used to set up the required output format before outputting any data. The image size
is derived through downscaling of the SXGA image from the pixel array. the user may
manually override the stability flags. The snapshot mode command can be issued in either
Run or Stop mode and the device will automatically return previous state after the snapshot
is taken. according to the set image format parameters and frame rate control parameters. In
running mode the device outputs a continuous stream of images. In normal operation this
frame will be output.the flash output is synchronized to the image stream. Rev / .VS
Operational modes Pause mode In this mode all VS clocks are running and all registers are
accessible but no data is output from the device. In the pulsed mode there are two possible
pulse configurations Single pulse during the interframe period when all image lines are
exposed. Pulsed flash with viewfinder. To reduce the latency to output. Pulsed Mode .
formats and reconstruction settings to be applied to alternate frames of data. Device outputs
a flash pulse synchronized to a single frame in the image stream. ViewLive this feature
allows different sizes. This is suitable for LED flash configurations. This is suitable for SCR
and IGBT flash configurations. There are two options available Pulsed flash with snapshot.
The falling edge of the pulse can be programmed to vary the width of the pulse.user can
manually switch on/off the FSO IO pin via a register setting. while in run mode. Single pulse
over entire integration period of frame. Snapshot mode The device can be configured to
output a single frame according to the size. FLASHGUN mode In flashgun mode. Device
outputs a single frame synchronized to flash. once the exposure. The device is ready to start
streaming but is halted.
This functionality is controlled by the Power management register. Some transitions can
occur automatically after a time out. The users control allows a transition between Stop and
Run. at the state level the system will transition through a Pause state.Operational modes VS
. writing xFF disables the automatic transition to Stop. / Rev . If there is no activity in the
Pause state then an automatic transition to the Stop state occurs. Mode transitions
Transitions between operating modes are normally controlled by the host by writing to the
Host interface manager control register.
To program an input frequency of . MHz. The allowable input range is from . i. The default
input frequency is MHz. parallel output data is synchronized to the input clock.e. In slave
configuration. The external clock should be a DC coupled square wave.MHz to MHz. The VS
may be configured as a master or slave device. the input clock is the same frequency and
phase as the output PCLK. the numerator can be set to and the denominator to . The VS
contains an internal PLL allowing it to produce accurate frame rates from a wide range of
input clock frequencies. The input clock frequency must be programmed in the registers. The
clock signal may have been RC filtered.VS Clock control Clock control Input clock The VS
requires provision of an external reference clock. Rev / . In normal master operation the input
clock can be a different frequency to the output PCLK and all output clock configuration is
based on the internal PLL. The clock input is failsafe in power down mode.
the full array is readout and the max frame rate achievable is fps SensorModeVGAanalogue
binning . The output image size can be chosen from one of preselected sizes or a manual
image size can be input. Note that by default the interline blanking data is not qualified by the
PCLK and therefore is not captured by the host system.the full array operates and a
technique of analogue binning is used to output VGA at up to fps
SensorModeVGAsubsampled . The user can set a start location and the required output size.
Cropping module The VS contains a cropping module which can be used to define a window
of interest within the full SXGA array size. or a scaled output.Frame control VS Frame control
Sensor mode control The VS device can operate its sensor array in three modes controlled
by register SensorMode within Mode setup. depending on sensor mode. SensorModeSXGA .
/ Rev . The image size can be either the full output from the sensor. Each line consists of
embedded line codes if selected.the array is subsampled to output VGA at up to fps Image
size An output frame consists of a number of active lines and a number of interframe lines.
Figure shows the example with pipe setup bank. active pixel data and interline blank data.
if the output size selected equals the sensor mode size then no pan can take place. up and
down when the output size selected is smaller than the sensor size selected. and
uwDesiredFrameRateDen any desired frame rate between and fps can be selected for the
SXGA sensor mode and between and fps for a VGA sensor mode. right. Rev / .VS Figure .
The pan step size in both the horizontal and vertical directions are selectable. Crop controls
Sensor array horizontal size Frame control uwManualCropHorizontalStart
uwManualCropVerticalStart Cropped ROI Sensor array vertical size
uwManualCropVerticalSize uwManualCropHorizontalSize FFOV Zoom It is possible to zoom
between the sensor size selected and the output size if the output size selected equals the
sensor mode size then no zoom can take place. Frame rate control The VS features an
extremely flexible frame rate controller. The zoom step size in both the horizontal and vertical
directions are selectable and zoom controlled with the commands zoomin. zoomout and
zoomstop. To program a required frame rate of . fps the numerator can be set to and the
denominator to . Using registers uwDesiredFrameRateNum. Pan It is possible to pan left.
QQVGA RGB then switch to capture an image e. SXGA YUV with no need to stop streaming
or enter any other operating mode. Pipe setup bank and Pipe setup bank. allow different
gamma settings to be used for each pipe setup. Horizontal and vertical flip Pipe RGB to YUV
matrix manual control and Pipe RGB to YUV matrix manual control. Image controls Contrast.
it is possible to control which pipe setup bank is used and to switch between banks without
the need to stop streaming. Context switching In normal operation. control the operations
shown below. i. by default the Pipe setup bank is used.Frame control VS Horizontal mirror
and vertical flip The image data output from the VS can be mirrored horizontally or flipped
vertically or both.. / Rev . the control of this pipe can be loaded from either of two possible
setups Pipesetupbank and Pipesetupbank. RGB. Pipe gamma manual control and Pipe
Gamma manual control. For example this function allows the VS to stream an output
targeting a display e.. to configure PipeSetupBank to QQVGA and PipeSetupBank to SXGA
the sensor mode must be set to SXGA. Color saturation. the change will occur at the next
frame boundary after the change to the register has been made.g.e. etc. The register Mode
setup allows selection of the pipe setup bank. image size zoom control pan control Crop
control Image format YUV . It is important to note the output size selected for both pipe
setups must be appropriate to the sensor mode used. Video pipe setup The VS has a single
video pipe. allow different RGB to YUV matrixes to be used for each pipe setup..g.
When ViewLive is enabled the output data switches between Pipe setup bank and Pipe
setup bank on each alternate frame. Figure . ViewLive frame output format Frame output
Active Video Pipe setup bank Interline Blanking Interframe Blanking Active Video Pipe setup
bank Interline Blanking Interframe Blanking Rev / .VS Frame control ViewLive Operation
ViewLive is an option which allows a different pipe setup bank to be applied to alternate
frames of the output data. The controls for VIewLive function are found in the register bank
where the fEnable register allows the host to enable or disable the function and the
binitialPipeSetupBank register selects which pipe setup bank is output first.
Cb and Cr components as shown in Figure . Standard Y Cb Cr data order HSYNC SIGNAL
EAV Code START OF DIGITAL ACTIVE LINE F X Cb F Y Y Cr Y Cb Y Cr Y Cb Y Cr Y data
packet The VS bYuvSetup register can be programmed to change the order of the
components as follows / Rev .Output data formats VS Output data formats The VS supports
the following data formats YUV YUV RGB RGB encapsulated as RGB zero padded Bayer bit
Bayer bit The required data format is selected using the bdataFomat control found in the pipe
setup bank registers. ITU defines the order of the Y. Line / Frame Blanking Data The values
which are output during line and frame blanking are an alternating pattern of x and x by
default. The various options available for each format are controlled using the bRgbsetup
and bYuvSetup registers found in the Output formatter control registers. YUV data format
YUV data format requires bytes of data to represent adjacent pixels. Figure . These values
may be changed by writing to the BlankDataMSB and BlankDataLSB registers in the Output
formatter control bank.
Figure .. It is possible to reverse the overall bit order of the component through a register
programming.........VS Figure . Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel YUV F X F
Y Pixel .. In this output mode the output data per pixel is a single byte.... YUV format
encapsulated in ITU stream START OF DIGITAL ACTIVE LINE EAV Code F X D D D D D D
D D D D F Y ....... Output data formats Y Cb Cr data swapping options register x bYuvSetup
Components order in byte data packet st nd rd Y Cb Y Cr Cb Y Cr Y Y Cr Y Cb Bit Cb first
Bit Y first th Cr Y Cb Y DEFAULT YUV The ITU protocol allows the encapsulation of various
data formats over the link... dependent on detection of a code or code respectively.... The
following data formats are also proposed encapsulated in ITU protocol YUV . Note False
synchronization codes are avoided in the LSByte by adding or subtracting a value of
one.luminance data channel This is done as described in Figure .. where Pixeln Yn See
Output formatter control for user interface control of output data formats. Rev / ........
Therefore the output PCLK and data rate is halved...
In each of these modes bytes of data are required for each output pixel. Figure . correctly
exposed and white balanced. RGB and Bayer data formats RGB data packing Bit Bit B B B B
R R R R R G G G second byte RGB packed as RGB Bit Bit G G G B first byte G B B B B R R
R R G G G second byte RGB zero padded Bit Bit first byte B B B R R R R G G G G B first
byte second byte Bayer bit Bit b b Bit b b b b b b b b second byte first byte / Rev . The
encapsulation of the data is shown in Table .Output data formats VS RGB and Bayer bit data
formats The VS can output data in the following formats RGB RGB encapsulated as RGB
RGB zero padded Bayer bit Note Pixels in Bayer bit data output are defect corrected. Any or
all of these functions can be disabled.
This is enabled through the DitherControl register. dependent on detection of a code or code
respectively. Note False synchronization codes are avoided in the LSByte by adding or
subtracting a value of one. Therefore the output PCLK and data rate is halved. Bayer output
START OF DIGITAL ACTIVE LINE EAV Code F X D D D D D D D D D D D D F Y Pixel
where Pixel Pixel Pixel Pixel bit Bayer F X L L L L L L L L L L L L F Y S S S S S S S S S S S
S B B B B B B B B B B BB LSBn Bayer n Rev Pixel / . Figure . Bayer bit The ITU protocol
allows the encapsulation of various data formats over the link.VS Output data formats
Manipulation of RGB data It is possible to modify the encapsulation of the RGB data in a
number of ways swap the location of the RED and BLUE data reverse the bit order of the
individual color channel data reverse the order of the data bytes themselves Dithering An
optional dithering function can be enabled for each RGB output mode to reduce the
appearance of contours produced by RGB data truncation. In this output mode the output
data per pixel is a single byte. It is possible to reverse the overall bit order of the individual
bayer pixels through a register programming. The following data formats are also proposed
encapsulated in ITU protocol RAW bit bayer Truncated from bit DPCM encoded from bit This
is done as described in Figure .
/ Rev . When embedded codes are selected each line of data output contains additional
clocks before the active video data and after it. . The final byte in the sequence depends on
the mode selected. Prevention of false synchronization codes The VS is able to prevent the
output of xFF and/or x data from being misinterpreted by a host system as the start of
synchronization data. This function is controlled the bCodeCheckEnable register. x.
Embedded codes The embedded code sequence can be inserted into the output data stream
to enable the external host system to synchronize with the output frames. Mode ITU
compatible The structure of an image frame with ITU codes is shown in Figure . The code
consists of a byte sequence starting with xFF. Synchronization codes are embedded in the
output data Via the use of two additional synchronization signals VSYNC and HSYNC Both
methods of synchronization can be programmed to meet the needs of the host system. Two
types of embedded codes are supported by the VS Mode ITU and Mode . The
bSyncCodeSetup register is used to select whether codes are inserted or not and to select
the type of code to insert.Data synchronization methods VS Data synchronization methods
External capture systems can synchronize with the data output from VS in one of two ways .
x.
blanking Line end . ITU embedded synchronization code definition odd frames Name
Description Line start .blanking byte sequence FF C FF DA FF EC FF F SAV EAV SAV
blanking EAV blanking Rev Line blanking period / .blanking Line end . Table .VS Figure
.active Line start .blanking byte sequence FF FF D FF AB FF B Table .active Line end . ITU
embedded synchronization code definition even frames Name SAV EAV SAV blanking EAV
blanking Description Line start .active Line start . By default all frames output from the VS are
EVEN. ITU frame structure with even codes Line Data synchronization methods SAV Frame
of image data EAV D Line SAV AB Frame blanking period EAV B The synchronization codes
for odd and even frames are listed in Table and Table . It is possible to set all frames to be
ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in
theOutput formatter control register bank.active Line end .
Data synchronization methods
VS
Mode
The structure of a mode image frame is shown Figure . Figure . Mode frame structure VGA
example
FS Line
LS
Frame of image data
LE
Line Frame blanking period
FE
For mode , the synchronization codes are as listed in Table . Table . Mode embedded
synchronization code definition
Name LS LE FS FE Line start Line end Frame Start Frame End Description byte sequence
FF FF FF FF
/
Rev
Line blanking period
VS
Data synchronization methods
Mode Logical DMA channels
The purpose of logical channels is to separate different data flows which are interleaved in
the data stream, in the case of the VS this allows the identification of the pipe setup bank
used for an image frame. The DMA channel identifier number is directly encoded in the byte
mode embedded sync codes. The receiver can then monitor the DMA channel identifier and
demultiplex the interleaved video streams to their appropriate DMA channel. The bChannelID
register can have the value to . The DMA channel identifier must be fully programmable to
allow the host to configure which DMA channels the different video data stream use.
Logical channel control
The channel identifier is a part of Mode synchronization code, upper four bits of last byte of
synchronization code. Figure . illustrates the synchronization code with logical channel
identifiers. Figure . Mode frame structure VGA example
bit embedded mode sync code
F
F
DC LC
DMA Channel Number Valid channels to
Line code x Line Start x Line End x Frame Start x Frame End
VSYNC and HSYNC
The VS can provide two programmable hardware synchronization signals VSYNC and
HSYNC. The position of these signals within the output frame can be programmed by the
user or an automatic setting can be used where the signals track the active video portion of
the output frame regardless of its size.
Horizontal synchronization signal HSYNC
The HSYNC signal is controlled by the bHSyncSetup register. The following options are
available
enable/disable select polarity all lines or active lines only manual or automatic
Rev /
Data synchronization methods
VS
In automatic mode the HSYNC signal envelops all the active video data on every line in the
output frame regardless of the programmed image size. Line codes if selected fall outside
the HSYNC envelope as shown in Figure . Figure . HSYNC timing example
hsync
hsync
BLANKING DATA
ACTIVE VIDEO DATA
EAV Code
FF XY
SAV Code
FF XY D D D D D D D D
EAV Code
D D FF XY
If manual mode is selected then the pixel positions for HSYNC rising edge and falling edge
are programmable. The pixel position for the rising edge of HSYNC is programmed in the
bHSyncRising registers. The pixel position for the falling edge of HSYNC is programmed in
the bHSyncFalling registers.
Vertical synchronization VSYNC
The VSYNC signal is controlled by the bSyncSetup register. The following options are
available
enable/disable select polarity manual or automatic
In automatic mode the VSYNC signal envelops all the active video lines in the output frame
regardless of the programmed image size as shown in Figure .
/
Rev
the pixel position for VSYNC rising edge is programmed in the bVsyncRisingPixel registers.
The following options are available enable/disable select polarity select starting phase
qualify/dont qualify embedded synchronization codes enable/disable during horizontal
blanking Rev / . VSYNC timing example Data synchronization methods BLANKING V V
ACTIVE VIDEO vsync BLANKING V V ACTIVE VIDEO If manual mode is selected then the
line number for VSYNC rising edge and falling edge is programmable.VS Figure . Pixel clock
PCLK The PCLK signal is controlled by the Output formatter control register. Similarly the
line count for the falling edge position is specified in the bVsyncFallingLine registers. The
rising edge of VSYNC is programmed in the bVsyncRisingLine registers. and the pixel count
is specified in the bVsyncFallingPixel registers.
with the associated qualifying pclk clock. byte per pixel Bayer Bit Data Pix Pix Pix PCLK
Data Pix Pix Pix YUV PCLK / Rev .n PCLK Data Pixlsb Pixmsb Pixlsb Pixmsb Pixlsb RGB
RGB PCLK Data Pixlsb Pixmsb Pixlsb Pixmsb Pixlsb Bayer Bit PCLK bit data output formats.
Figure .n Yn Cbn. QCLK options data Negative edge Positive edge PCLK Negative edge
Positive edge Noneactive level .High D D D VS The YUV.n Yn Crn.Data synchronization
methods Figure . bytes per pixel Data YCbCr Cbn. RGB and bayer timings are represented
on Figure .Low Noneactive level . The output clock rate is effectively halved for the bayer bit
and YUV modes where only one byte of output data is required per pixel. Qualification clock
bit data output formats .
PCLK is independent of the input clock frequency and does not have a determined phase
relation to the input clock. but a retiming stage is used to resync the output to the input
clock.VS Data synchronization methods Master / Slave operation of PLCK In normal
operation VS acts as a master. In this output mode. derating is not possible. Rev / . the VS
uses clocks generated from the internal PLL. In SLAVE operation the input clock frequency is
the same as the output clock frequency and the output data is guaranteed with a certain
phase relationship to the input clock. Internally.
Apply VDD . . . .before any commands can be sent to the VS. The I/O are enabled by writing
the value x to the DIOEnable register xC found in the Low level control registers Section. /
Rev .V Apply an external CLOCK . Minimum startup command sequence . The user can then
program the system clock frequency and setup the required output format before placing the
VS in RUN mode by writing x to the Host interface manager control register x. . Enable the
microprocessor . The above three commands represent the absolute minimum required to
get video data output. . fps. see Figure Power up sequence. After these steps are complete a
delay of s is required before any IC communication can take place. Enable the digital I/O .V
or . In practice the user is likely to require to write some additional setup information prior to
receive the required data output.V Apply AVDD .Getting started VS Getting started Initial
power up Before any communication is possible with the VS the following steps must take
place .after power up the digital I/O of the VS is in a highimpedance state tristate. the internal
microprocessor must be enabled by writing the value x to the MicroEnable register xC found
in the Low level control registers Section.MHz to MHz Assert CE line HIGH These steps can
all take place simultaneously. YUV data format with ITU embedded codes requiring a
external clock frequency of MHz. The default configuration results in an output of SXGA.
The next byte of data contains the value to be written to that register index.IC control
interface Host communication . After every byte transferred the receiving device must output
an acknowledge bit which tells the transmitter if the data byte has been successfully received
or not. If multiple data bytes are read then the internal register index is automatically
incremented after each byte of data Rev / . The master can send data bytes continuously to
the slave until the slave fails to provide an acknowledge or the master terminates the write
communication with a STOP condition or sends a repeated START Sr. Read message S
DEV ADDR R/W A DATA A DATA A P Read or more Data Byte From Master to Slave From
Slave to Master For the master reading from the slave the device address is followed by the
contents of last register index that the previous read or write message accessed. Figure .
Figure . Protocol A message contains two or more bytes of data preceded by a START S
condition and followed by either a STOP P or a repeated START Sr condition followed by
another message. Higher level protocol adaptations have been made to allow for greater
addressing flexibility.VS Host communication . The first byte of the message is called the
device address byte and contains the bit address of the VW slave to be addressed plus a
read/write bit which defines the direction of the data flow between the master and the slave.
Write message S DEV ADDR R/W A DATA A Index Bytes DATA A DATA N Data Byte A/A P
Write From Master to Slave From Slave to Master For the master writing to the slave the
device address byte is followed by bytes which specify the bit internal location index for the
data write. If multiple data bytes are written then the internal register index is automatically
incremented after each byte of data transferred. STOP and START conditions can only be
generated by a VW master.IC control interface The interface used on the VS is a subset of
the IC standard. This extended interface is known as the VW interface. . The meaning of the
data bytes that follow device address changes depending whether the master is writing to or
reading from the slave.
Host communication .Write .IC control interface VS read. Detailed overview of message
format S Sr bit Device Address R/W A bit Data A A P Sr P SDA MSB SCL S or Sr LSB MSB
LSB Sr Sr or P START or repeated START condition Device Address R/W Bit . A message
can only be terminated by the bus master.Slave ACK signal from receiver STOP or repeated
Start condition The VW generic message format consists of the following sequence / Rev .
Detailed overview of the message format Figure . .Master R/W .Read ACK signal from slave
Data byte from transmitter R/W . A read message is terminated by the bus master generating
a negative acknowledge after reading a final byte of data. a repeated start condition or by a
negative acknowledge after reading a complete byte during a read operation. either by
issuing a stop condition.
.IC control interface Master generates a START condition to signal the start of new
message. The addressed slave acknowledges the device address. R/W then the master
transmitter is writing to the slave receiver. .VS . Minimum number of data bytes for a read
Shortest Message length is bytes. Data receive acknowledge a b Repeat and until all the
required data has been written or read. When a read is performed master acknowledges
data. The master outputs a negative acknowledge for the data when reading the last byte of
data. a bit device address of the slave the master is trying to communicate with followed by a
R/W bit. Data transmitted on the bus a b When a write is performed then master outputs bits
of data on SDA MS Bit first. This causes the slave to stop the output of data and allows the
master to generate a STOP condition. . When a read is performed then slave outputs bits of
data on SDA MS Bit First. Master generates a STOP condition or a repeated START. Device
addresses Sensor address R/W Sensor write address H Sensor read address H Rev / .
When a write is performed slave acknowledges data. a b . MS bit first. . R/W the master
receiver is reading from the slave transmitter. Figure . Master outputs. Host communication .
The state of SDA is changed during the low phase of SCL. If a repeated START Sr is used
instead of a stop then the bus stays busy. Figure .Host communication . SDA data valid SDA
SCL Data line stable Data valid Data change Data line stable Data valid . Start S and Stop P
conditions A START S condition defines the start of a VW message. The only exceptions to
this are the start S and stop P conditions as defined below. Data valid The data on SDA is
stable during the high period of SCL. It consists of a high to low transition on SDA while SCL
is high. A STOP P condition defines the end of a VW message.IC control interface VS . After
STOP condition the bus is considered free for use by other devices. START and STOP
conditions SDA SCL S START condition P STOP condition / Rev . It consists of a low to high
transition on SDA while SCL is high. Figure . A START S and a repeated START Sr are
considered to be functionally equivalent. See IC slave interface for full timing specification.
ROM and/or micro controller values. To acknowledge the data byte receiver pulls SDA
during the th SCL clock cycle generated by the master. Data acknowledge SDA data output
by transmitter Negative Acknowledge A SDA data output by receiver Acknowledge A SCL
clock from master S START Condition Clock Pulse for Acknowledge .IC control interface .
Most of the registers are read/write allowing the receiving equipment to change their
contents. These registers store sensor status. setup. SRAM. This space includes real
registers. Figure . Rev / . Index space Communication using the serial bus centres around a
number of registers internal to the either the sensor or the coprocessor. The internal register
locations are organized in a k by bit wide space. Others such as the chip id are read only.
Acknowledge After every byte transferred the receiver must output an acknowledge bit.VS
Host communication . If SDA is not pulled low then the transmitter stops the output of data
and releases control of the bus back to the master so that it can either generate a STOP or a
repeated START condition. exposure and system information.
Host communication . The serial interface supports variable length messages. Multiple
location. Any messages formats other than those specified in the following section should be
considered illegal. A message contains no data bytes or one data byte or many data bytes.
Only sets the index for a subsequent read message. This data can be written to or read from
common or different locations within the sensor.IC control interface Figure . The range of
instructions available are detailed below. Types of messages This section gives guidelines
on the basic operations to read data from and write data to VS. / Rev . single byte data read
or write. Internal register index space bits VS bit Index / bit Data Format k by bit wide index
space Valid Addresses . Write no data byte. multiple data read or write for fast information
transfers. Single location.
Current location. This is because if the data sent by the slave is all zeros. This was the case
in older VW implementations. single data read For the master reading from the slave the
R/W bit is set to one. Single Data Write Previous Index Value. bit Data. The first data byte
returned by a read message is the contents of the internal index value and NOT the index
value. single data read Previous Index Value. M From Master to Slave From Slave to Master
DATA S START Condition Sr repeated START P STOP Condition A Acknowledge A
Negative Acknowledge .IC control interface . Figure . single read bit index. single write bit
Index. the SDA line cannot rise. Random location.VS Host communication . Note that the
read message is terminated with a negative acknowledge A from the master it is not
guaranteed that the master will be able to issue a stop condition at any other time during a
read message. Random location. K S DEV ADDR R/W A DATA A P Read DATA DATA From
Master to Slave From Slave to Master S START Condition Sr repeated START P STOP
Condition A Acknowledge A Negative Acknowledge Rev / . which is part of the stop
condition. The write message is terminated with a stop condition from the master. bit data
current location. Current location. The register index of the data returned is that accessed by
the previous read or write message. The register index value written is preserved and is used
by a subsequent read. K S DEV ADDR R/W A DATA A DATA A DATA Index M A/A P Write
INDEX INDEX DATA Index value. single data write For the master writing to the slave the
R/W bit is set to zero. Figure . Random Location.
single data read Previous Index Value. Figure . bit data multiple location write Previous
Index Value. K S DEV ADDR R/W A DATA A DATA A Index M DATA A Index M N . As
mentioned in the previous example. bit data random index. Multiple location write For
messages with more than data byte the internal register index is automatically incremented
for each byte of data output. making it possible to write data bytes to consecutive adjacent
internal registers without having to send explicit indexes prior to sending each data byte.
specifying the index. K No Data Write Index M Data Read S DEV ADDR R/W A DATA A
DATA A Sr DEV ADDR R/W A DATA A P Write INDEX INDEX Read DATA DATA INDEX
value. M From Master to Slave From Slave to Master S START Condition Sr repeated
START P STOP Condition A Acknowledge A Negative Acknowledge . Random location.
single data read When a location is to be read. but the value of the stored index is not
known. the read message is terminated with a negative acknowledge A from the master.
DATA A/A P Write INDEX INDEX DATA DATA DATA DATA N Bytes of Data INDEX value.
Figure . M From Master to Slave From Slave to Master S START Condition Sr repeated
START P STOP Condition A Acknowledge A Negative Acknowledge / Rev . bit index.Host
communication . To avoid relinquishing the serial to bus to another master a repeated start
condition is asserted between the write and read messages. bit index. a write message with
no data byte must be written first. The read message then completes the message
sequence.IC control interface VS .
VS Host communication . A P Read DATA DATA DATA DATA N Bytes of Data DATA DATA
From Master to Slave From Slave to Master S START Condition Sr repeated START P
STOP Condition A Acknowledge A Negative Acknowledge Rev / . multiple locations can be
read with a single read message. K S DEV ADDR R/W A DATA A Index K DATA A DATA
Index K N . Multiple location read stating from the current location In the same manner to
multiple location writes.IC control interface . Figure . Multiple location read bit Index. bit data
multiple location read Previous Index Value.
K S DEV ADDR R/W A Write INDEX INDEX value. Multiple Data Read Previous Index
Value. Multiple location read starting from a random location Rev S START Condition Sr
repeated START P STOP Condition From Master to Slave From Slave to Master VS ./ Index
M Data Read Index M N . bit Index.IC control interface Multiple location read starting from a
random location Figure . No Data Write DATA A DATA A Sr DEV ADDR R/W A DATA A
DATA A P . bit Data Random Index. M DATA INDEX DATA Read DATA DATA N Bytes of
Data A Acknowledge A Negative Acknowledge Host communication .
Note For all bit parameters the MSB register must be written before the LSB register. Table .
Normalize the mantissa and calculate the exponent to give a binary scientific representation
of . Information on initial power up for the device can be found in the Section Getting started.
Data type Description Single field register bit parameter Multiple field registers .VS Register
map Register map The VS IC write address is x. The data can then be placed in the structure
above. To calculate the y value Bias the exponent by adding to decimal then converting to
binary. To read or write to registers other than those in Low level control registers section the
device must be switched on.xxxxxxxxx y. use the following procedure represent the number
as a binary floating point number. The x symbols should represent binary digits of the
mantissa. However. biased at decimal Bit bits of mantissa To convert a floating point number
to Float .function depends on value written Float Value Data Type BYTE UINT FLAGe
CODED FLOAT Float number format Float is used in ST coprocessors to represent floating
point numbers in bytes of data. Register contents represent different data types as described
in Table . The data stored in each location can be interpreted in different ways as shown
below. Rev / . bit parameter Bit of register must be set/cleared Coded register . All IC
locations contain an bit byte. Remove the leading from the mantissa as it is redundant. It
conforms to the following structure Bit Sign bit represents negative Bit bits of exponent. this
is done by writing x to xC. certain parameters require bits to represent them and are
therefore stored in more than location. round or pad with zeros to achieve digits in total.
The mantissa is rounded and the leading zero removed to give . . . . . . / Rev . we can use
the following formula. Real is sign mantissaegtgt exp Thus to convert BB back to decimal.
the following procedure is followed Note that gtgt right shift is equal to division by . We add
the exponent to the bias of that gives us or . . . . real . . . we see that some rounding errors
have been introduced. . . When compared to the original . . . To convert the encoded
representation back to a decimal floating point. Sign Exponent decimal Mantissa decimal
This gives us real / real / real . A leading zero is added to give bits . . . .Register map VS
Example Convert . . . . .. . This gives us as our Float representation or BB in hex. The sign bit
is set at as the number is negative.. . .. This gives us . We then normalize by moving the
decimal point to give . . to Float Convert the fraction into binary by successive multiplication
by and removal of integer component . . .
Ext. All other registers can be read when the MicroEnable register is set to x.start device x
Enables the digital I/O of the device CODED ltgt IO pins in a high impedance state Tristate
ltgt IO pins enabled Note The default values for the above registers are true when the device
is powered on. Rev / .VS Register map Low level control registers Table . Can be controlled
in all stable states. Index MicroEnable Default value xC Purpose Type Possible values
DIOEnable Default value xC Purpose Type Possible values . Lowlevel control registers
LowLevelControlRegisters xc Used to power up the device CODED ltxcgt initial state after
low to high transition of CE pin ltxgt Power enable for all MCU Clock. Clk input is present and
the CE pin is high.
low power mode.stop video streaming ltgt STOP .grab one frame at correct exposure for
flashgun Host interface manager control HostInterfaceManagerControl Possible values .grab
one frame at correct exposure without flashgun ltgt FLASHGUN . analogue powered down
ltgt SNAPSHOT.powerup default ltgt BOOT . UINT bFirmwareVsnMajor BYTE
bFirmwareVsnMinor BYTE BYTE BYTE Host interface manager control Table . Device
parameters read only DeviceParameters read only device id e. Can be controlled in all stable
states / Rev .the boot command will identify the sensor amp setup low level handlers ltgt
RUN .g.stream video ltgt PAUSE.Register map VS User interface map Device parameters
read only Table . Can be accessed in all stable state. Index uwDeviceId x MSByte x LSByte
Purpose Type x Type x Type bPatchVsnMajor x Type bPatchVsnMinor xa Type . Index
bUserCommand Default value Purpose Type x ltgt UNINITIALISED User level control of
operating states CODED ltgt UNINITIALISED .
The host has issued a PAUSE command.Grabbing a single frame. Can be controlled in all
stable states Run mode control RunModeControl ltgt TRUE If metering is off the Auto
Exposure AE and Auto White Balance AWB tasks are disabled Flage ltgt FALSE ltgt TRUE
Rev / . Index fMeteringOn Default Value x Purpose Type Possible values . The
HostInterfaceManager is waiting for the ModeManager to signal PAUSE processing
complete.Low power Host interface manager status Read only HostInterfaceManagerStatus
Read only x Possible values . ltgt PAUSED . ltgt FLASHGUN .VS Register map Host
interface manager status Table . CODED ltgtRAW . the input pipe is idle.Booted. ltgt
WAITINGFORBOOT . ltgtWAITINGFORRUN . Can be accessed in all stable states Run
mode control Table . ltgt RUNNING .The pipe is active. ltgt WAITINGFORPAUSE .default
powerup state. Index bState Default Value Purpose Type ltgtRAW The current state of the
mode manager.Waiting for ModeManager to complete RUN setup.Waiting for ModeManager
to signal BOOT event. ltgt STOPPED .
CODED ltgt ImageSizeSXGA ltgt ImageSizeVGA ltgt ImageSizeCIF ltgt ImageSizeQVGA
ltgt ImageSizeQCIF ltgt ImageSizeQQVGA ltgt ImageSizeQQCIF ltgt ImageSizeManual .to
use ManualSubSample and ManualCrop controls select Manual mode.Register map VS
Mode setup Table . Pipe setup bank PipeSetupBank Possible values uwManualHSize xMSB
xLSB Default value Purpose Type x if ImageSizeManual selected. Index bImageSize Default
value Purpose Type x ltgt ImageSizeSXGA required output dimension. Index Mode setup
ModeSetup bNonViewLiveActivePipeSetupBank Can be controlled in all stable states Default
Value ltgt PipeSetupbank Select the active bank for non view live mode CODED ltgt
PipeSetupbank ltgtPipeSetupbank x Purpose Type Possible values SensorMode Must be
configured in STOP mode Default value Purpose x Type Possible values
ltgtSensorModeSXGA Select the different sensor mode CODED ltgtSensorModeSXGA
ltgtSensorModeVGA ltgtSensorModeVGANormal Pipe setup bank Table . input required
manual H size UINT / Rev .
VS Table . input required manual V size UINT uwZoomStepHSize xbMSB xcLSB Default
value Purpose Type x Set the zoom H step UINT uwZoomStepVSize xfMSB xLSB Default
value Purpose Type bZoomControl Default value Purpose x Type Possible values ltgt
ZoomStop control zoom in. Index uwManualVSize xMSB xLSB Default value Purpose Type x
Register map Pipe setup bank PipeSetupBank if ImageSizeManual selected. zoom out and
zoom stop C ltgt ZoomStop ltgt ZoomStartIn ltgt ZoomStartOut x Set the zoom V step UINT
uwPanSteplHSize xMSB xLSB Default value Purpose Type uwPanStepVSize xMSB xaLSB
Default value Purpose Type x Set the PanV step UINT x Set the pan H step UINT Rev / .
pan down C ltgt PanDisable ltgt PanRight ltgt PanLeft ltgt PanDown ltgt PanUp VS Pipe
setup bank PipeSetupBank Possible values bCropControl Default value xe Purpose Type
Possible values ltgt Cropauto Select cropping manual or auto C ltgt Cropmanual ltgt
Cropauto uwManualCropHorizontalStart xaMSB xaLSB Default value Purpose Type x Set
the cropping H start address UINT uwManualCropHorizontalSize xaMSB xaLSB Default
value Purpose Type x Set the cropping H size UINT uwManualCropVerticalStart xaMSB
xaaLSB Default value Purpose Type x Set the cropping Vstart address UINT
uwManualCropVerticalSize xadMSB xaeLSB Default value Purpose Type x Set the cropping
Vsize UINT / Rev . Index bPanControl Default value Purpose xc Type ltgt PanDisable control
pandisable. pan left. pan right. pan up.Register map Table .
to use custom output select required RgbToYuvOutputSignalRange from PipeSetupBank
page. Index bImageFormat Default value Purpose Type ltgt ImageFormatYCbCrJFIF select
required output image format. CODED Register map Pipe setup bank PipeSetupBank xb
Possible values ltgt ImageFormatYCbCrJFIF ltgt ImageFormatYCbCrRec ltgt
ImageFormatYCbCrCustom . ltgt ImageFormatYCbCr ltgt ImageFormatRGB ltgt
ImageFormatRGBCustom .to use custom output select required
RgbToYuvOutputSignalRange from PipeSetupBank page.VS Table .to truncate bayer data to
bits data bBayerOutputAlignment Default value xb Purpose Type Possible values bContrast
xb Default value Purpose Type bColourSaturation xb Default value Purpose Type bGamma
Default value xb Purpose Type Possible values xf gamma settings. BYTE to x colour
saturation control for both YCbCr and RGB output. ltgt ImageFormatBayerThroughVP ltgt
ImageFormatBayerCompThroughVP. BYTE ltgt BayerOutputAlignmentRightShifted set
bayer output alignment CODED ltgt BayerOutputAlignmentRightShifted ltgt
BayerOutputAlignmentLeftShifted Rev / .to use custom output select required
RgbToYuvOutputSignalRange from PipeSetupBank page.to compress bayer data to bits
data ltgt ImageFormatBayerTranThroughVP. BYTE x contrast control for both YCbCr and
RGB output. ltgt ImageFormatRGB ltgt ImageFormatRGBCustom .
denotes registers where changes will only be consumed during the transition to a RUN
state. Index fHorizontalMirror Default Value xba Purpose Type Possible values fVerticalFlip
Default Value xbc Purpose Type Possible values bChannelD Default value xbe Purpose
Type Possible values x Logical DMA Channel Number BYTE to x Vertical image orientation
flip Flage ltgt FALSE ltgt TRUE x Horizontal image orientation flip Flage ltgt FALSE ltgt
TRUE VS Pipe setup bank PipeSetupBank . . it is not possible to move between these
groups of modes without first a transition to STOP then a BOOT. Can be controlled in all
stable state.Register map Table . / Rev . It is possible to switch between any YCrCb mode.
RGB mode and Bayer bit or move between YCrCb and a bayer mode without a requiring a
transition to STOP.
Pipe setup bank PipeSetupBank Possible values uwManualHSize xMSB xLSB Default value
Purpose Type uwManualVSize xMSB xLSB Default value Purpose Type x if
ImageSizeManual selected. input required manual H size UINT uwZoomStepHSize xbMSB
xcLSB Default value Purpose Type x Set the zoom H step UINT uwZoomStepVSize xfMSB
xLSB Default value Purpose Type x Set the zoom V step UINT Rev / .VS Register map Pipe
setup bank Table . input required manual V size UINT x if ImageSizeManual selected.
CODED ltgt ImageSizeSXGA ltgt ImageSizeVGA ltgt ImageSizeCIF ltgt ImageSizeQVGA ltgt
ImageSizeQCIF ltgt ImageSizeQQVGA ltgt ImageSizeQQCIF ltgt ImageSizeManual . Index
bImageSize Default value Purpose Type x ltgt ImageSizeSXGA required output dimension.to
use ManualSubSample and ManualCrop controls select Manual mode.
zoom stop CODED ltgt ZoomStop ltgt ZoomStartIn ltgt ZoomStartOut VS Pipe setup bank
PipeSetupBank uwPanSteplHSize xMSB xLSB Default value Purpose Type
uwPanStepVSize xMSB xaLSB Default value Purpose Type bPanControl Default value
Purpose xc Type ltgt PanDisable control pandisable.Register map Table . Index
bZoomControl Default value Purpose x Type Possible values ltgt ZoomStop control zoom in.
zoom out. pan down C ltgt PanDisable ltgt PanRight ltgt PanLeft ltgt PanDown ltgt PanUp x
Set the PanV step UINT x Set the pan H step UINT Possible values bCropControl Default
value xe Purpose Type Possible values ltgt Cropauto Select cropping manual or auto C ltgt
Cropmanual ltgt Cropauto uwManualCropHorizontalStart xMSB xLSB Default value Purpose
Type x Set the cropping H start address UINT / Rev . pan left. pan up. pan right.
to use custom output select required RgbToYuvOutputSignalRange from PipeSetupBank
page. ltgt ImageFormatYCbCr ltgt ImageFormatRGB ltgt ImageFormatRGBCustom . ltgt
ImageFormatBayerThroughVP ltgt ImageFormatBayerCompThroughVP. Index
uwManualCropHorizontalSize xMSB xLSB Default value Purpose Type x Set the cropping H
size UINT Register map Pipe setup bank PipeSetupBank uwManualCropVerticalStart xMSB
xaLSB Default value Purpose Type x Set the cropping Vstart address UINT
uwManualCropVerticalSize xdMSB xeLSB Default value Purpose Type bImageFormat
Default value Purpose Type ltgt ImageFormatYCbCrJFIF select required output image
format.to compress bayer data to bits data ltgt ImageFormatBayerTranThroughVP. CODED
ltgt ImageFormatYCbCrJFIF ltgt ImageFormatYCbCrRec ltgt ImageFormatYCbCrCustom .
ltgt ImageFormatRGB ltgt ImageFormatRGBCustom .VS Table .to use custom output select
required RgbToYuvOutputSignalRange from PipeSetupBank page.to use custom output
select required RgbToYuvOutputSignalRange from PipeSetupBank page.to truncate bayer
data to bits data x Set the cropping Vsize UINT x Possible values bBayerOutputAlignment
Default value x Purpose Type Possible values ltgt BayerOutputAlignmentRightShifted set
bayer output alignment CODED ltgt BayerOutputAlignmentRightShifted ltgt
BayerOutputAlignmentLeftShifted Rev / .
denotes registers where changes will only be consumed during the transition to a RUN
state. It is possible to switch between any YCrCb mode. BYTE x contrast control for both
YCbCr and RGB output.Register map Table . Can be controlled in all stable state. it is not
possible to move between these groups of modes without first a transition to STOP then a
BOOT. Index bContrast x Default value Purpose Type bColourSaturation x Default value
Purpose Type bGamma Default value x Purpose Type Possible values fHorizontalMirror
Default value xa Purpose Type Possible values fVerticalFlip Default value xc Purpose Type
Possible values bChannelD Default value xe Purpose Type Possible values x Logical DMA
Channel Number BYTE to x Vertical image orientation flip Flage ltgt FALSE ltgt TRUE x
Horizontal image orientation flip Flage ltgt FALSE ltgt TRUE xf gamma settings. BYTE VS
Pipe setup bank PipeSetupBank . / Rev . RGB mode and Bayer bit or move between YCrCb
and a bayer mode without a requiring a transition to STOP. . BYTE to x colour saturation
control for both YCbCr and RGB output.
Index CurrentPipeSetupBank Default value x Purpose Type Possible values ltgt
PipeSetupBank indicates the PipeSetupBank which has most recently been applied to the
pixel pipe hardware. if ViewLive is enabled the next frame will be from the other
PipeSetupBank. Index ViewLive control ViewLiveControl fEnable Can be controlled in all
stable states Default value ltgt FALSE set to enable the View Live mode. otherwise only one
PipeSetupBank will be used. CODED ltgt PipeSetupBank ltgt PipeSetupBank x Purpose
Type Possible values Viewlive status read only Table .VS Register map Viewlive control
Table . Flage ltgt FALSE ltgt TRUE x Purpose Type Possible values bInitialPipeSetupBank
must be setup in PAUSE or STOP mode Default value ltgt PipeSetupBank First frame output
will be from PipeSetupBank selected by bInitialPipeSetupBank. CODED ltgt PipeSetupBank
ltgt PipeSetupBank Viewlive status ViewLiveStatus read only Rev / .
Should be configured in the RAW state x BYTE Video timing control Table .MHz Mode
ltgtSlave Mode Video timing control VideoTimingControl Possible values . Index
bSysClkMode Default value Purpose x Type x Decides system centre clock frequency
CODED ltgtMHz Mode ltgtMHz Mode ltgt. BYTE Video timing parameter host inputs Table .
xff disables the automatic transition.. external clock frequency
uwExternalClockFrequencyMhzNumerator/bExternalClockFrequencyMh zDenominator UINT
x MSByte x LSByte Purpose Type bExternalClockFrequencyMhzDenominator x Default
value Type . Should be configured in the RAW state / Rev .. Index Video timing parameter
host inputs VideoTimingParameterHostInputs uwExternalClockFrequencyMhzNumerator
Default value xc specifies the External Clock Frequency. Index x bTimeToPowerdown
Default value Purpose Type .Register map VS Power management Table . Must be
configured in STOP mode Power management PowerManagement xf Time mSecs from
entering Pause mode until the system automatically transitions stop mode.
VS Register map Frame dimension parameter host inputs Table .used for flicker free time
period calculations this mains frequency determines the flicker free time period. Index
uwDesiredFrameRateNum xd MSByte xd LSByte Default value Purpose Type xf Numerator
for the Frame Rate UINT Static frame rate control StaticFrameRateControl
bDesiredFrameRateDen xd Default value Purpose Type . Can be controlled in all stable
states ltgt FALSE flickercompatibleframelength Flage ltgt FALSE ltgt TRUE Static frame rate
control Table . BYTE Frame dimension parameter host inputs
FrameDimensionParameterHostInputs fFlickerCompatibleFrameLength Default value xc
Purpose Type Possible values . Index bLightingFrequencyHz Default value xc Purpose Type
x AC Frequency . Can be controlled in all stable states x Denominator for the Frame Rate
BYTE Rev / .
Automatic Mode of Exposure which includes computation of Relative Step ltgt
COMPILEDMANUALMODE .Mode in which the exposure parameters are input directly and
not calculated by compiler ltgt FLASHGUNMODE .Register map VS Automatic Frame rate
control Table . Index bMode Default value Purpose Type x ltgt AUTOMATICMODE Sets the
mode for the Exposure Algorithm CODED ltgt AUTOMATICMODE . Index
bDisableFrameRateDamper Default value xe Purpose Type Possible values ltgt Manual ltgt
Auto x Defines the mode in which the framerate of the system would work Automatic Frame
Rate Control AutomaticFrameRateControl bMinimumDamperOutput xec MSByte xea LSByte
Default value Purpose Type .Compiled Manual Mode in which the desired exposure is given
and not calculated by algorithm ltgt DIRECTMANUALMODE .Flash Gun Mode in which the
exposure parameters are set to fixed values Exposure controls ExposureControls possible
values / Rev . UINT Exposure controls Table . Can be controlled in all stable states x Sets
the minimum framerate employed when in automatic framerate mode.
a user choice for setting the runtime target. A unit of exposure compensation corresponds to
/ EV.Uniform gain associated with all pixels ltgt ExposureMeteringbacklit . Coded Value of
Exposure compensation can take values from to . Default value according to the Nominal
Target of is . Num/Den gives required exposure time BYTE bManualExposureTimeDen x
Default value Type xe BYTE fpManualFloatExposureTime x MSByte xa LSByte Default value
Purpose Type xaa Exposure Time for the Manual Mode. This value is in uSecs FLOAT
iExposureCompensation Default value x Purpose x Exposure Compensation . INT Type
uwDirectModeCoarseIntegrationLines x MSByte x LSByte Default value Purpose Type x
Coarse Integration Lines to be set for Direct Mode UINT Rev / . Index bMetering Default
value Purpose x Type ltgt ExposureMeteringflat Register map Exposure controls
ExposureControls Weights to be associated with the zones for calculating the mean statistics
Exposure Weight could Centered. Backlit or Flat C ltgt ExposureMeteringflat .VS Table .more
gain associated with centre pixels possible values bManualExposureTimeNum Default value
x Purpose Type x Exposure Time for Compiled Manual Mode in seconds.more gain
associated with centre pixels and bottom pixels ltgt ExposureMeteringcentred .
Register map Table . Index VS Exposure controls ExposureControls
uwDirectModeFineIntegrationPixels x MSByte xa LSByte Default value Purpose Type x Fine
Integration Pixels to be set for Direct Mode UINT fpDirectModeAnalogGain xd MSByte xe
LSByte Default value Purpose Type x Analog Gain to be set for Direct Mode FLOAT
fpDirectModeDigitalGain xa MSByte xa LSByte Default value Purpose Type x Digital Gain to
be set for Direct Mode FLOAT uwFlashGunModeCoarseIntLines xa MSByte xa LSByte
Default value Purpose Type x Coarse Integration Lines to be set for Flash Gun Mode UINT
uwFlashGunModeFineIntPixels xa MSByte xaa LSByte Default value Purpose Type x Fine
Integration Pixels to be set for Flash Gun Mode UINT fpFlashGunModeAnalogGain xad
MSByte xae LSByte Default value Purpose Type x Analog Gain to be set for Flash Gun
Mode FLOAT fpFlashGunModeDigitalGain xb MSByte xb LSByte Default value Purpose
Type x Digital Gain to be set for Flash Gun Mode FLOAT / Rev .
VS Table . This would in turn give an idea of the degree of wobbly pencil effect acceptable to
Host. Can be controlled in all stable states Purpose Type ltgt AntiFlickerModeInhibit Anti
flicker mode CODED ltgt AntiFlickerModeInhibit ltgt AntiFlickerModeManualEnable
ltgtAntiFlickerModeAutomaticEnable Rev / . This control takes in the maximum integration
time that host would like to support. Index fFreezeAutoExposure Default value xb Purpose
Type possible values ltgt FALSE Freeze auto exposure Flage ltgt FALSE ltgt TRUE Register
map Exposure controls ExposureControls fpUserMaximumIntegrationTime Default value xb
MSByte xb LSByte xf User Maximum Integration Time in microseconds. FLOAT
fpRecommendFlashGunAnalogGainThreshold xbb MSByte xbc LSByte Default value
Purpose Type x Recommend flash gun analog gain threshold value FLOAT
bAntiFlickerMode Default value Purpose xc Type Possible values .
RedGain For FlashGun FLOAT x User setting for Blue Channel gain BYTE x User setting for
Green Channel gain BYTE x User setting for Red Channel gain BYTE / Rev .Automatic
mode. relative step is computed here ltgt MANUALRGB .User manual mode.DAYLIGHT and
all the modes below. gains are applied manually ltgt DAYLIGHTPRESET . ltgt
TUNGSTENPRESET ltgt FLUORESCENTPRESET ltgt HORIZONPRESET ltgt
MANUALCOLOURTEMP ltgt FLASHGUNPRESET White balance control parameters
WBControlParameters possible values bManualRedGain x Default value Purpose Type
bManualGreenGain x Default value Purpose Type bManualBlueGain x Default value
Purpose Type fpFlashRedGain xb MSByte xc LSByte Default value Purpose Type
fpFlashGreenGain xf MSByte x LSByte Default value Purpose Type xe . fixed value of gains
are applied here. all gains will be unity in this mode ltgt AUTOMATIC .Register map VS
White balance control Table . Green Gain For FlashGun FLOAT xe .No White balance. Index
bMode Default value Purpose Type x ltgt AUTOMATIC For setting Mode of the white balance
CODED ltgt OFF .
Index fpFlashBlueGain x MSByte x LSByte Default value Purpose Type . BlueGain For
FlashGun FLOAT Sensor setup Table . BYTE Image Stability read only Table . Can be
controlled in all stable states Sensor setup SensorSetup x Black Correction Offset which
would be added to the sensor pedestal to get the RE Offset. This is to improve the black
level. Can be controlled in all stable states Register map White balance control parameters
WBControlParameters xea .VS Table . Index bBlackCorrectionOffset Default value x
Purpose Type . Index fWhiteBalanceStable Default value x Purpose Type Possible values
fExposureStable Default value x Purpose Type Possible values x Specifies that white
balance system is stable/unstable CODED ltgt Unstable ltgtStable x Specifies that white
balance system is stable/unstable CODED ltgt Unstable ltgtStable Image stability read only
Image stability read only Rev / .
Index fStable Default value x Purpose Type Possible values x VS Image stability read only
Image stability read only Consolidated flag to indicate whether the system is stable/unstable
CODED ltgt Unstable ltgtStable Flash control Table . Index bFlashMode Default value
Purpose xa Type Possible values ltgt FLASHOFF Select the flash type and on/off CODED
ltgt FLASHOFF ltgtFLASHTORCH ltgtFLASHPULSE Flash control FlashControl
uwFlashOffLine xaMSB xaLSB Default value Purpose Type . Can be controlled in all stable
states xc At flashpulse mode. used to control off line UINT / Rev .Register map Table .
Flage ltgt FALSE ltgt TRUE Scythe filter controls Table .VS Register map Flash status read
only Table . Flage ltgt FALSE ltgt TRUE Flash status FlashStatus read only
fFlashGrabComplete Default value xb Purpose Type Possible values ltgt FALSE This flag
indicates that the FlashGun Image has been grabbed. Can be controlled in all stable state
Jack filter controls JackFilterControls ltgt FALSE Disable Jack Defect Correction Flage ltgt
FALSE ltgt TRUE Rev / . Index fDisableFilter Default value xe Purpose Type Possible values
. Can be controlled in all stable state Scythe filter controls ScytheFilterControls ltgt FALSE
Disable Scythe Defect Correction Flage ltgt FALSE ltgt TRUE Jack filter controls Table .
Index fDisableFilter Default value xd Purpose Type Possible values . It is at the discretion of
Host to use it or not for the following still grab. Index fFlashRecommend Default value xb
Purpose Type Possible values ltgt FALSE This flag is set if the Exposure Control system
reports that the image is underexposed and so the flashgun is recommended to the Host.
Can be controlled in all stable state Demosaic control DemosaicControl x Anti alias filter
suppress BYTE Colour matrix dampers Table . Index fDisable Default value xf Purpose Type
Possible values fpLowThreshold xf MSByte xf LSByte Default value Purpose Type
fpHighThreshold xf MSByte xf LSByte Default value Purpose Type fpMinimumOutput xfb
MSByte xfc LSByte Default value Purpose Type . Minimum possible damper output for the
ColourMatrix FLOAT / Rev . Can be controlled in all stable state Colour matrix dampers
ColourMatrixDamper ltgt FALSE set to disable colour matrix damper and therefore ensure
that all the Colour matrix coefficients remain constant under all conditions. Index
bAntiAliasFilterSuppress xe Default value Purpose Type . Flage ltgt FALSE ltgt TRUE xd
Low Threshold for exposure for calculating the damper slope FLOAT x High Threshold for
exposure for calculating the damper slope FLOAT xacd .Register map VS Demosaic control
Table .
range . Index bUserPeakGain x Default value Purpose Type xe controls peaking gain /
sharpness applied to the image BYTE Peaking control Peaking control fDisableGainDamping
Default value x Purpose Type Possible values ltgt FALSE set to disable damping and
therefore ensure that the peaking gain applied remains constant under all conditions Flage
ltgt FALSE ltgt TRUE fpDamperLowThresholdGain x MSByte x LSByte Default value
Purpose Type xac Low Threshold for exposure for calculating the damper slope . Minimum
possible damper output for the gain.VS Register map Peaking control Table . FLOAT
bUserPeakLoThresh x Default value Purpose Type xe Adjust degree of coring.for gain
FLOAT fpDamperHighThresholdGain x MSByte xa LSByte Default value Purpose Type xd
High Threshold for exposure for calculating the damper slope .for gain FLOAT
fpMinimumDamperOutputGain xd MSByte xe LSByte Default value Purpose Type xd . BYTE
fDisableCoringDamping Default value x Purpose Type Possible values ltgt FALSE set to
ensure that bUserPeakLoThresh is applied to gain block Flage ltgt FALSE ltgt TRUE Rev / .
Minimum possible damper output for the Coring. BYTE VS Peaking control Peaking control
fpDamperLowThresholdCoring x MSByte x LSByte Default value Purpose Type xa Low
Threshold for exposure for calculating the damper slope . FLOAT / Rev . Index
bUserPeakHiThresh x Default value Purpose Type x adjust maximum gain that can be
applied.Register map Table .for coring FLOAT fpMinimumDamperOutputCoring xf MSByte x
LSByte Default value Purpose Type . Can be controlled in all stable states xa . range .for
coring FLOAT fpDamperHighThresholdCoring xb MSByte xc LSByte Default value Purpose
Type xf High Threshold for exposure for calculating the damper slope .
Index fRgbToYuvManuCtrl Default value x Purpose Type Possible values w x MSByte
xLSByte Default value Purpose Type w x MSByte x LSByte Default value Purpose Type w xc
MSByte xd LSByte Default value Purpose Type w x MSByte xf LSByte Default value Purpose
Type w x MSByte x LSByte Default value Purpose Type w x MSByte x LSByte Default value
Purpose Type x Row Column of YUV matrix UINT x Row Column of YUV matrix UINT x Row
Column of YUV matrix UINT x Row Column of YUV matrix UINT x Row Column of YUV
matrix UINT x Row Column of YUV matrix UINT ltgt FALSE Enables manual RGB to YUV
matrix for PipeSetupBank Flage ltgt FALSE ltgt TRUE Pipe RGB to YUV matrix manual
control PipeRGB to YUV matrix Rev / .VS Register map Pipe RGB to YUV matrix manual
control Table .
Index w xb MSByte xc LSByte Default value Purpose Type w xa MSByte xf LSByte Default
value Purpose Type w xa MSByte xa LSByte Default value Purpose Type YinY xa MSByte
xa LSByte Default value Purpose Type YinCb xab MSByte xac LSByte Default value
Purpose Type YinCr xb MSByte xaf LSByte Default value Purpose Type .Register map Table
. Can be controlled in all stable states VS Pipe RGB to YUV matrix manual control PipeRGB
to YUV matrix x Row Column of YUV matrix UINT x Row Column of YUV matrix UINT x Row
Column of YUV matrix UINT x Y in Y UINT x Y in Cb UINT x Y in Cr UINT / Rev .
Index fRgbToYuvManuCtrl Default value x Purpose Type Possible values w x MSByte
xLSByte Default value Purpose Type w x MSByte x LSByte Default value Purpose Type w xc
MSByte xd LSByte Default value Purpose Type w x MSByte xf LSByte Default value Purpose
Type w x MSByte x LSByte Default value Purpose Type w x MSByte x LSByte Default value
Purpose Type x Row Column of YUV matrix UINT x Row Column of YUV matrix UINT x Row
Column of YUV matrix UINT x Row Column of YUV matrix UINT x Row Column of YUV
matrix UINT x Row Column of YUV matrix UINT ltgt FALSE Enables manual RGB to YUV
matrix for PipeSetupBank Flage ltgt FALSE ltgt TRUE Pipe RGB To YUV matrix manual
control PipeRgbToYuv Rev / .VS Register map Pipe RGB to YUV matrix manual control
Table .
Index w xb MSByte xc LSByte Default value Purpose Type w x MSByte xf LSByte Default
value Purpose Type w x MSByte x LSByte Default value Purpose Type YinY x MSByte x
LSByte Default value Purpose Type YinCb xb MSByte xc LSByte Default value Purpose
Type YinCr x MSByte xf LSByte Default value Purpose Type .Register map Table . Can be
controlled in all stable states VS Pipe RGB To YUV matrix manual control PipeRgbToYuv x
Row Column of YUV matrix UINT x Row Column of YUV matrix UINT x Row Column of YUV
matrix UINT x Y in Y UINT x Y in Cb UINT x Y in Cr UINT / Rev .
Can be controlled in all stable states Pipe gamma manual control Pipe GammaManuControl
ltgt FALSE Enables manual Gamma Setup for PipeSetupBank Flage ltgt FALSE ltgt TRUE x
Peaked Red channel gamma value BYTE x Peaked Green channel gamma value BYTE x
Peaked Blue channel gamma value BYTE x Unpeaked Red channel gamma value BYTE x
Unpeaked Green channel gamma value BYTE x Unpeaked Blue channel gamma value
BYTE Rev / .VS Register map Pipe gamma manual control Table . Index fGammaManuCtrl
Default value x Purpose Type Possible values bRPeakGamma x Default value Purpose Type
bGPeakGamma x Default value Purpose Type bBPeakGamma x Default value Purpose
Type bRUnPeakGamma x Default value Purpose Type bGUnPeakGamma xa Default value
Purpose Type bBUnPeakGamma xc Default value Purpose Type .
Index fGammaManuCtrl Default value x Purpose Type Possible values bRPeakGamma x
Default value Purpose Type bGPeakGamma x Default value Purpose Type bBPeakGamma
x Default value Purpose Type bRUnPeakGamma x Default value Purpose Type
bGUnPeakGamma xa Default value Purpose Type bBUnPeakGamma xc Default value
Purpose Type . Can be controlled in all stable states Pipe Gamma manual control
PipeGammaManuControl ltgt FALSE Enables manual Gamma Setup for PipeSetupBank
Flage ltgt FALSE ltgt TRUE x Peaked Red channel gamma value BYTE x Peaked Green
channel gamma value BYTE x Peaked Blue channel gamma value BYTE x Unpeaked Red
channel gamma value BYTE x Unpeaked Green channel gamma value BYTE x Unpeaked
Blue channel gamma value BYTE / Rev .Register map VS Pipe Gamma manual control
Table .
VS Register map Fade to black Table . Can be controlled in all stable states Rev / . Minimum
possible damper output. Index x fDisable Default value Purpose Type x MSByte xLSByte
fpBlackValue Default value Purpose Type x MSByte x LSByte x . Black value FLOAT ltgt
FALSE Flage ltgt FALSE ltgt TRUE Fade to black FadeToBlack fpDamperLowThreshold
Default value Purpose Type xd Low Threshold for exposure for calculating the damper slope
FLOAT xb MSByte xc LSByte fpDamperHighThreshold Default value Purpose Type xcdc
High Threshold for exposure for calculating the damper slope FLOAT xf MSByte x LSByte
fpDamperOutput Default value Purpose Type x . FLOAT .
SyncCodeSetupframemode . for mode SyncCodeSetupfieldbit SyncCodeSetupfieldtag
SyncCodeSetupfieldload x BYTE x BYTE Output formatter control OutputFormatterControl
bHSyncSetup Default value x Type xb CODED HSyncSetupsyncen HSyncSetupsyncpol
HSyncSetuponlyactivelines HSyncSetuptrackhenv flag bits bVSyncSetup Default value x
Type flag bits x CODED VSyncSetupsyncen VSyncSetuppol VSyncSetupsel / Rev . for
ITU.set for embedded sync codes.Register map VS Output formatter control Table . Index
bCodeCheckEn x Default value Type bBlankFormat x Default value Type bSyncCodeSetup
Default value Type x flag bits x CODED SyncCodeSetupinscodeen .
Index bPClkSetup Default value Type xa flag bits x CODED PClkSetupproglo
PClkSetupproghi PClkSetupsyncen PClkSetuphsyncenn PClkSetuphsyncenntrackinternal
PClkSetupvsyncn PClkSetupvsyncntrackinternal PClkSetupfreer Register map Output
formatter control OutputFormatterControl fPclkEn Default value xc Type Possible values
bOpfSpSetup xe Default value type bBlankDataMSB x Default value Type Possible values
bBlankDataLSB x Default value Type Possible values bRgbSetup Default value x Type x
CODED RgbSetuprgbituzp RgbSetuprbswap RgbSetupbitreverse RgbSetupsoftreset x
CODED ltgt BlankingLSBDefault x CODED ltgt BlankingMSBDefault x BYTE ltgt TRUE Flage
ltgt FALSE ltgt TRUE flag bits Rev / .VS Table .
Register map Table . Index bYuvSetup Default value x Type flag bits x CODED
YuvSetupufirst YuvSetupyfirst VS Output formatter control OutputFormatterControl
bVsyncRisingCoarseH x Default value Type x BYTE bVsyncRisingCoarseL xa Default value
Type bVsyncRisingFineH xc Default value Type bVsyncRisingFineL xe Default value Type x
BYTE x BYTE x BYTE bVsyncFallingCoarseH xa Default value Type x BYTE
bVsyncFallingCoarseL xa Default value Type xf BYTE bVsyncFallingFineH xa Default value
Type bVsyncFallingFineL xa Default value Type bHsyncRisingH xa Default value Type x
BYTE x BYTE x BYTE / Rev .
Can be controlled in all stable states x BYTE Rev / .VS Table . Index bHsyncRisingL xaa
Default value Type bHsyncFallingH xac Default value Type bHsyncFallingL xae Default value
type x BYTE x BYTE x BYTE Register map Output formatter control OutputFormatterControl
bOutputInterface Default value xb Type flag bits OutputInterfaceITU CODED
OutputInterfaceITU OutputInterfaceCCPDataStrobe OutputInterfaceCCPDataClock
bCCPExtraData xb Default value Type .
Always on NoRA controls NoRAControls bUsage x Default value Purpose Type bSplitKn x
Default value Purpose Type bSplitNl x Default value Purpose Type bTightGreen x Default
value Purpose Type BYTE x BYTE x BYTE x BYTE x fDisableNoroPromoting Default value
xa Type Possible values ltgt FALSE Flage ltgt FALSE ltgt TRUE fpDamperLowThreshold xd
MSByte xe LSByte Default value Purpose Type x Low Threshold for exposure for calculating
the damper slope FLOAT / Rev . Index fDisable Default value x Type Possible values ltgt
NoraCtrlauto Flage ltgt NoraCtrlauto .Register map VS NoRA controls Table .switches off
NoRA for scaled outputs ltgt NoraCtrlManuDisable .Always off ltgt NoraCtrlManuEnable .
FLOAT Rev / .VS Table . Can be controlled in all stable states xa . Index
fpDamperHighThreshold x MSByte x LSByte Default value Purpose Type xa Register map
NoRA controls NoRAControls High Threshold for exposure for calculating the damper slope
FLOAT MinimumDamperOutput x MSByte x LSByte Default value Purpose Type . Minimum
possible damper output.
Typ.Optical specifications VS Optical specifications Table . infinity deg. Unit inch mm . /
Max. All measurements made at C C Min. Optical specifications Parameter Optical format
Effective focal length Aperture F number Horizontal field of view Depth of field TV distortion .
cm / Rev .
optimal Camera produces optimal optical performance Digital power supplies operating
range module pin Analog power supplies operating range module pin Min. Electrical
characteristics Absolute maximum ratings Table . Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Rev / . Typ. Unit C V V Caution
Stress above those listed under Absolute Maximum Ratings can cause permanent damage
to the device. Max. . . . . . Module can contain routing resistance up to . C V V V VDD AVDD .
. Max. functional Camera is electrically functional Operating temperature. . . . . Operating
conditions Table . Symbol TSTO VDD AVDD Absolute maximum ratings Parameter Storage
temperature Digital power supplies Analog power supplies Min. nominal Camera produces
acceptable images Operating temperature. Symbol TAF TAN Supply specifications
Parameter Operating temperature. This is a stress rating only and functional operations of
the device at these or other conditions above those indicated in the operational sections of
this specification is not implied. Unit C C TAO . . . .VS Electrical characteristics .
. CLK MHz CE. .Electrical characteristics VS . CLK MHz CE. VDD Unit V V V V A A pF pF
pF Table . freq MHz TA C. . . /. VDD . .V VDD . CLK MHz streaming VGA fps . . freq MHz TA
C. . .V VDD . VDD VDD .Sensor mode VGA fps IAVDD Description supply current in power
down mode supply current in Standby mode supply current in Stop mode supply current in
Pause mode supply current in active streaming run mode Test conditions VDD . SCL Output
capacitance I/O capacitance. . CLK MHz CE.V IVDD Units IPD Istanby IStop IPause Irun CE.
. Symbol Typical current consumption . . . . Note Table . VDD Typ. . . . freq MHz . VDD /.
Test conditions Min. SDA IOL lt mA IOL lt mA IOHlt mA lt VIN lt VDD TA C. CLK MHz CE.
Max. DC electrical characteristics Description Input low voltage Input high voltage Output low
voltage Output high voltage Input leakage current Input pins I/O pins Input capacitance. . A
mA mA mA mA / Rev . Symbol VIL VIH VOL VOH IIL CIN COUT CI/O DC electrical
characteristics Over operating conditions unless otherwise specified.
Max. This clock is a CMOS digital input. . Table .. . . Rev / . Typ.Sensor mode SXGA fps
IAVDD Description supply current in power down mode supply current in Standby mode
supply current in Stop mode supply current in Pause mode supply current in active streaming
run mode Test conditions VDD .. Chip enable CE is a CMOS digital input. External clock The
VS requires an external clock. A mA mA mA mA . . . Symbol Typical current consumption . .
..V VDD .. CLK MHz CE. . . See Power up sequence for further information. . The clock input
is failsafe in power down mode. V MHz Unit DC coupled square wave Clock frequency
normal operation .V VDD . CLK MHz CE. CLK MHz CE.. External clock Range CLK Min. . . .
.. The module is powered down when a logic is applied to CE. . . CLK MHz streaming VGA
fps . . .V IVDD Units IPD Istanby IStop IPause Irun CE.VS Electrical characteristics Table . . .
CLK MHz CE... VDD .
VDD V V V ns ns . Cb capacitance of one bus line in pF Figure .Cb . V .Electrical
characteristics VS . VDD . Maximum VIH VDDmax . Voltage level specification Input voltage
levels Output voltage levels VIH . VDD VIL . VDD V V VOL VOL VOH tOF tSP N/A N/A N/A .
Min. See Host communication . Hysteresis of Schmitt Trigger Inputs VDD gt V VDD lt V LOW
level output voltage open drain at mA sink current VDD gt V VDD lt V HIGH level output
voltage Output fall time from VIHmin to VILmax with a bus capacitance from pF to pF Pulse
width of spikes which must be suppressed by the input filter Max. Table . Fast Mode Unit
VHYS N/A N/A N/A N/A . N/A N/A N/A . VDD VOL .IC control interface for detailed
description of protocol. VDD VOH . VDD . IC slave interface VS contains an ICtype interface
using two signals a bidirectional serial data line SDA and an inputonly serial clock line SCL.
Max. VDD / Rev . . Symbol Serial interface voltage levels Standard Mode Parameter Min.
DAT tr tf tSU. .VS Electrical characteristics Table .STO tBUF Cb VnL VnH Timing
specification Standard mode Parameter Min. . VDD SCL clock frequency Hold time for a
repeated start LOW period of SCL HIGH period of SCL Setup time for a repeated start Data
hold time Data Setup time Rise time of SCL.STA tLOW tHIGH tSU. VDD . VDD . . . SDA Fall
time of SCL. . .STA tHD. VDD Max.Cb . VDD . Min. Max. . .Cb .DAT tSU. . . All values are
referred to a VIHmin . SDA Setup time for a stop Bus free time between a stop and a start
Capacitive Load for each bus line Noise Margin at the LOW level for each connected device
including hysteresis Noise Margin at the HIGH level for each connected device including
hysteresis . Symbol fSCL tHD. VDD and VILmax . kHz s s s s ns ns ns ns s s pF V V Fast
mode Unit . Cb capacitance of one bus line in pF Rev / . . . .
VDD . Timing specification SDA VS tSP tSU. VDD . VDD . VDD Figure .DAT tSU. SDA/SCL
rise and fall times . VDD tr tf / Rev .DAT tSU.STA SCL tHD.STO tBUF tHD.Electrical
characteristics Figure .STA S START tLOW tHIGH tr tf P STOP S START All values are
referred to a VIHmin .STA tHD. VDD and VILmax .
Parallel data interface timing VS contains a parallel data output port D and associated
qualification signals HSYNC. This port can be enabled and disabled tristated to facilitate
multiple camera systems or bitserial output configurations. Unit MHz ns ns ns Rev / . The
port is disabled high impedance upon reset. Figure . Max. PCLK and FSO. VSYNC. VSYNC
Valid tPCLKH Table . Symbol fPCLK tPCLKL tPCLKH tDV Parallel data interface timings
Description PCLK frequency PCLK low width PCLK high width PCLK to output valid
Conditions Min. Typ. Parallel data output video timing /fPCLK tPCLKL PCLK polarity tDV D
HSYNC.VS Electrical characteristics .
Figure and Figure present the package outline FPC module VSPLP.Package mechanical
data VS Package mechanical data Figure and Figure present the package outline socket
module VSQKP. / Rev .
posns .X B . . CH . . Linear Place Decimals . Pin out info clarified DATE // // // C C F This
drawing is the property of STMicroelectronics and will not be copied or loaned without the
written permission of STMicroelectronics. Position . . RD Angle Projection Material All
dimensions in mm Finish . scallop dimensions changed Sheet . . Package outline socket
module VSQKP E . . . Sheet . . . Ref Rev . . C Figure . at A A D D REVISIONS E ZONE REV.
degrees Diameter . Place Decimals . . Place Decimals .X. . Surface Finish . . . Tolerances. .
All dimensions in mm Do Not Scale Scale F STMicroelectronics Sig. Angular . microns
Home. . unless otherwise stated Interpret drawing per BS. was . Personal amp
Communications Sector Title Camera Outline Sheet Drawn Socket version of Package
mechanical data / . . B C R . . Date Part No./. A CH. DESCRIPTION st release for comment
Sheet Added.VS A .
. . RD Angle Projection Material All dimensions in mm Finish . . Angular . All dimensions in
mm Do Not Scale Scale Package mechanical data A B . D B Pin . Pin . . unless otherwise
stated . Pin Pad Layout Partial section Interpret drawing per BS. . Surface Finish . E . ./. .
microns Home. . . . . Place Decimals . Sig. . . X .. C A Pin D . . . Pin A Top Of Scene . Place
Decimals . degrees Diameter . Position . . Linear Place Decimals . Personal amp
Communication Sector Title Sheet Drawn VS Camera Outline of . Tolerances. . . . / . D E . C
Figure . D F F STMicroelectronics Date Part No. Package outline socket module VSQKP Rev
This drawing is the property of STMicroelectronics and will not be copied or loaned without
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Projection Material All dimensions in mm Finish Sig. Angular . . . A A . . Rev Interpret drawing
per BS. . Place Decimals . B B C Figure . . DESCRIPTION st release for comment DATE //
Tolerances. Personal amp Communications Sector Title Camera Outline Sheet Drawn
Generic Flex Version of Package mechanical data / . C . . . degrees Diameter .VS . . Position
. This drawing is the property of STMicroelectronics and will not be copied or loaned without
the written permission of STMicroelectronics. microns Home. D D E REVISIONS ZONE
REV. Package outline FPC module VSPLP E .
Position . Package outline FPC module VSPLP Rev Drawn D E Molex type .pdf All
dimensions in mm Do Not Scale Scale Tolerances. Date Part No. unless otherwise stated F
F STMicroelectronics Home.Board conn http//www. . . Personal amp Communication Sector
Title Camera Outline Sheet Linear Place Decimals .com/pdmdocs/sd/sd. / . . microns
Generic Flex Version of VS . This drawing is the property of STMicroelectronics and will not
be copied or loaned without the written permission of STMicroelectronics. Place Decimals . C
A D E Interpret drawing per BS. Board . Angular . Surface Finish . A B . degrees Diameter .
Package mechanical data A B C Figure . Place Decimals .molex. RD Angle Projection
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Changes Rev / .VS Revision history Revision history Table . Date Feb Document revision
history Revision Initial release.
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