Download CMOS Devices : Limitations and Solutions for the End of the Roadmap

Introduction to CMOS Technology
C. Fenouillet-Beranger
SOI Devices Engineer, CEA/LETI &
STMicroelectronics, Crolles
1
Outline

MOSFET Basics
–
–
–
–

Ideal MOSFET physics
Main parameters : threshold, leakage and speed
What MOSFET for what application ?
Scaling theory and good design rules of CMOS Devices
The Real World
– Threshold voltage control limitations
– Gate oxide leakage and capacitance scaling

Technological Solution ?
–
–
–
–
Gate alternative : High-K and Metal Gate
Channel engineering : Strained-Si
Alternative devices and substrates
Basic logic functions
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
MOSFET Basics
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
CMOS technology applications
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Different scales inside a chip
Gate
2x2 cm²
Source
10x10 mm²
Drain
NiSi
NiSi
Silicon channel
4x4 µm²
500x500 nm²
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Making a Switch with Metal, Oxide and Silicon
Vg
Gate
C
0
Source
Vd
Metal
Drain
NiSi
Oxide
NiSi
Silicon channel
n+
Si (p)
E
Carrier reservoir
n+
=
S
D
Energy Barrier
Energy Barrier
Source
Drain
x
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
What is an ideal MOS Transistor ?
A MOS capacitor is modulating the transport
between two carrier reservoir
VG=0V
G
VS=0V
S
VG>0V
G
VD>0V
D
VS=0V
S
++++++
-------
VD>0V
D
IDS
Canal vide : courant nul
A
TMOS bloqué
OFF-STATE
Canal rempli : courant non nul
B
TMOS passant
ON-STATE
MOS capacitance : Field Effect  MOSFET
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
n-type & p-type MOSFETs
Vg>0
Vg<0
Vd>0
0
n+
Vd<0
0
Metal
Metal
Oxide
Oxide
Si (p)
n+
nMOSFET
Electron conduction
p+
Si (n)
p+
pMOSFET
Hole conduction
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
MOSFET morphology
Gate (Poly-Si)
Métal
Oxyde
Source
Drain
Semiconducteur
Si
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Basic Physics of MOSFET
Log(Idrain)
MOSFET
Ideal switch
switch
3 main parameters
ON state
Current
OFF state
Current
OFF State
Current (Thermal)
1. Threshold Voltage
2. Ion (=speed)
3. Ioff (=stand-by power)
Vgate
Threshold (Vth)
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
MOSFET Physics
nMOSFET
L
VVGG=V
=0D
VS
VD
L
----- +- +- P -+
+ + +
+
channel
source
Tox
N
gate
grille
+
« Off State»
drain
--- N
+
VB
canal
WS/C
BC
P
- d- -- N - - - - - - 
WD/C
- -- N -- N
-- -
VD
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Threshold Voltage (Vth)
L
gate
channel
source
WS/C
BC
drain
P
- N- -- - - - - -
Gate Material
Vth  V FB 
WD/C
Channel
Doping
Qdep
C ox
 2 F
Oxide Thickness
N
-- -
VD
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
On State Current (Ion)
I DS 
Qinv
t
Gate
E
VDS
L
L2
t
µeVDS
v  µe E
Qinv 

Vg-Vth
Vg-Vth-VDS
Lgate

V 
1 S

D
Qinv  Qinv
WL  C ox VG  Vth  DS WL
2
2 

Source
Drain
L
I DS
W
 µeCox
L
VDS 

VG  Vth 
VDS
2 

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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Off – State Current (Ioff)
VG1<Vth
Ithermique
VG1<VG2<Vth
Idiffusion
-- -- --
Ithermique
Idiffusion
-- -- -VD>0
V
V


I DS  I th exp  GT ln 10 1  exp   q DS
kT
 S


Log Idrain
VD>0



Modulation of barrier heigth by Capacitive coupling
+ dec
Ioff
1/S
Vth
log( I off )  log( I th ) 
S
S should be as small as possible
Vth
Vgate
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
The Static Leakage Components
i) Gate leakage
(oxide thickness
dependance)
Ioff = IS + IG + IB
ii) Channel Leakage
(Vth and S
dependant)
iii) Junction leakage
(doping dependance)
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Different Applications : Some typical numbers
Computers
100
High Performance
Low Vth
Ioff (nA/µm)
Power Dissipation
10
Hifi – TV
1
High Vth
Digital Consumer
0.1
0.01
Wireless
Mobile
Phones
0.001
0
500
1000
1500
Ion (µA/µm)
Operation Speed
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
CMOS Scaling
CMOS032
CMOS045
CMOS065
CMOS090
CMOS120
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Scaling Theory: Moore’s law
Gordon Moore, a co-founder of Intel said in 1965:
“Component count per unit area doubles every two years”
- Last 40 years : technological advances achieved mainly by reducing
transistors size
- However current trend of miniaturization causes undesired effects
degrading the electrical parameters and transistor performance
In reality:
• µ decreases
• Tox levels-off
• Off current increases as transistor size is reduced
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Ideal MOSFET Basics summary
Low Vth
Log(IDS)
High Vth
VGS
Gate Electrode
Source
Drain
Gate Electrode
Source
Drain
 Threshold Voltage :
Determines the gate voltage transition Vth between Off-state
and On-state regimes
Vth depends (at the 1st order) on the channel doping and
gate electrode material
 On-State :
MOS gate capacitance lowers channel barrier
electrons(holes) flow from Source to Drain  Ion current
Carrier transit time is Cgate*Vgate / Ion  the higher Ion the
faster the device
 Off-State :
MOS gate capacitance potential = 0
electrons(holes) flow from Source to Drain due to Thermionic
current  Ioff current
Static Power dissipation is Pstat = VDS * Ioff
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Part 2.
The Real World
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Vth Control : Short Channel Effects
Zone de charge d’espace
ZCE
L
Log Idrain
DIBL
SCE
SCE
DIBL
BC
VDS
SCE=Short Channel Effect
DIBL=Drain Induced Barrier Lowering
Vth2Vth1Vth
Vgate
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
MOSFET Typical Lenghts and Ratios
Lel  Lgate, phys  0.8 X j
Lgate,phys
Tox
gate
source
Tdep 
drain
Tdep
2 Si
 d  VSB 
qN B
Xj
Lel
Good design rules of MOSFET architecture :
Xj
1
 ;
Lel
3
T ox
Lel

1
3040
;
Tdep
Lel

1
Vth
3
Vdd

1
5
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Scaling rules (MASTAR Model)
VTH(short Mosfet)=VTH(long)-SCE-DIBL

2 
X
 Si 
 T ox T dep
j
SCE  0.8
V bi
1 

 ox 
L 2  L el L el

el 

2 
X
 Si 
 T ox T dep
j
DIBL  0.8
V ds
1 

 ox 
L 2  L el L el

el 
1
W
I dsat  m eff C ox el (Vg -Vth) V dsat
2
Lel
T. Skotnicki et al. IEEE EDL, March’88 & IEDM’1994
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Why is it so difficult to get a « Good Scaling » ?
T ox
1

Lel
Oxide Scaling
Junction Scaling Xj
1

Lel
3
3040
Lgate,phys
source
gate
Tdep
drain
Xj
Lel
Tdep
Lel

1
3 Doping increase
Vth
Subthreshold control Vdd

1
5
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Tox/Lel ratio : Gate Oxide Scaling
Poly-Silicium
Oxyde
Silicium
Tox
Lgate,phys
BC
source
Poly-Si
gate
drain
BV
Tdep
Xj
Lel
zz
zz
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
poly
Tdep

2 Si p
qN poly
 k
p
 p  

 2

kp 

 VG  V FB  2 F 

4

k 2p
2q Si N p
C ox
N+
Tdep
poly
= 0.4nm
P+
0.6nm
2
EOT of polydepletion, A
The Gate-Poly Silicon Depletion
20
18
16
14
12
10
8
6
4
2
0
NMOS ( Npoly =1e20cm-3)
Vdd scaled
with Tox
0
Tp (EOT)
@
1.8V
1.3V
1.0V
0.7V
0.5V
0.35V
0.25V
10
20
30
40
CMOS relevant Tox , A
Ref.: E. Josse et al., IEDM’99
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Quantization Effects in Inversion Layer
C-Y. Hu et al., IEEE EDL, June 1996
  2   3 qF  3   2 / 3
 
 
n
 2 m*   2  4  
 
1/ 3
En

2D
3D
V
 V
T
th
th
ox _ el

~150mV

E
0
q
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Impact on Good Design Rule
Silicium
Oxyde
Tox
Poly-Silicium
edep
einv
continuum
BC
Reality 0.18
BV
Tox, Tox_el and
Lmask, Lgate, Lel
according to ITRS 2001
Tox_el/ Lel
0.16
0.14
n=1
e
0.12
2
Tox/ L
econf
n=0
0.1
Tox_el/ Lgate
0.08
0.06
Tox_el/ Lmask
0.04
0.02
ea
ox
T
 Tox  T
poly
dep
 Tq
Tox/ Lmask
0
0
Good design Rule
50
100
CMOS node
150
Tox,eff = Tox + 8A
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
The problem of Gate Leakage
SiO2
1.E+05
Poly-Si
1nm
Gate current, A/cm2
1.E+03
Ec
1.5nm
Ef
Ev
1.E+01
2nm
Ef
Ec
1.E-01
2 .5nm
1.E-03
3nm
1.E-05
Si
1.E-07
Ev
Substrate Si
SiO2
P
3.5nm
1.E-09
0
1
2
Gate bias, V
3
Gate N+
Wpd
2A reduction in Tox  ~ 1 dec increase in gate leakage
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Impact of Gate Leakage on Circuits
0
0
Igoff
1
1
0
IgOn
0
Ioffcanal
0
0
In Static Mode, two gate leakages: IgOff & IgOn : increase of Ioff
If Tox
, Ig
, Power
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Vth/Vdd Ratio
Vth
Vdd

1
5
If Vdd drops, just decrease the Vth too keep a good
Ion. But …
Log(I DS )
S degrades at smaller L !
Ioff
Vth
Vgs
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
What Did We Learn ?
Controlling Vth (Ioff)
Increasing Doping
Junc. Leak.
Ioff (power) increase
Scaling Jonctions
Rs increase
Ion (speed) reduction
Scaling Tox
Gate leakage
Darkspace
Higher Ioff
Limited Scaling
Ion reduction
Polydepletion
Reducing Vdd (power)
Ion reduction
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Technological Boosters to recover a
Healthy Scaling
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
What can we do to retrieve a Healthy Scaling ?
Oxide Scaling
T ox
Lel
Junction Scaling

Xj
1

Lel
3
Gate
1
3040
Low RSD for lower Xj
Better Contact Resistance
Less Gate Lekage
No Poly Depletion
Source
Doping increase
Tdep
Lel

1
3
DIBL-Free Architecture
Drain
NiSi
NiSi
Silicon channel
Subthreshold control
Vs Overdrive
Vth
Vdd

1
5
Better Ion at the same
overdrive
Better Subthreshold
Slope
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Mobility Enhancement
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Ion Enhancement by materials
I DS
W
 µeCox
L
VDS 

VG  Vth 
VDS
2 

Transistor Architecture
Material
Properties
Velocity
Velocity saturation regime
Carrier velocity under
electric field E in the linear
regime: v = µ E
µ
Ecritical
Efield
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Mobility In Silicon
E
Shockwave from lattice
vibration, or impurities, or
gate oxide rugosity every t
seconds
carrier, mass m*
v
1.
2 Ec
m*
Small m* : ligth
electrons or holes
2. High t (less possible
collision)
µq
t
m
*
Effective mass of carrier
Linked to valence/conduction bands
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Who are the guys responsible for Ion ?
Silicon Band Structure
(z) 001
ml
mt
(y) 010
(x)100
6 equivalent types of electrons are involved
in conduction regime of nMOS
2 types of holes are involved in conduction
regime of pMOS : heavy and light
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
What happens in Strained-Si ?
qt
m *
mc
t
Splitting less intervalley
phonon scattering
m*c  i .mi
i
?
Splitting Sub-band
Carrier Redistribution
Band structure
deformation
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Redistribution in subbands and scattering reduction
N
Fermi-Dirac
Unstrained Si
Strained-Si
0.2
0.0
Si/Si0.5Ge0.5
Si bulk
HH
-0.1
0.1
-0.2
LH
>80 % in HH
-0.3
SO
Energy (eV)
Energy (eV)
LH
E(LH-HH)
0.0
< 1 % in HH
-0.1
HH
-0.2
-0.4
SO
-0.3
-0.5
[100]

[110]
[100]

[110]
E
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Is Stress the Only Way to Enhance Mobility ?

Carrier effective mass can depend on cristal direction !
– For Electron iso-energy are ellipsoidal  average
dependance does not depend on Si direction for standard
(100) substrate (not true in other direction)
– For Hole : extremely high anisotopy of mass !!
Heavy Mass
Holes with the same energy
Cristal Direction (3D)
Light Mass
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Choosing the right Si-orientation for Holes
Standard (100) wafer
Standard (100) wafer
45° Rotation
Heavy Mass along transport
Standard <110> channel
Light Mass along transport
Rotated <100> channel
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Optimum Cristal Orientations
 Inversion layer mobility depends on the surface orientations and current flow directions
 For holes, mobility is 2.5x higher on (110) surface compared to standard wafer with (100)
orientation
 For electrons, mobility is highest on (100) substrates
nMOS
pMOS
From M.Yang et al., IEDM 2004
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Hybrid integration
 To fully take advantage of the carrier mobility dependence on
surface orientation, fabrication of CMOS on hybrid substrates has
been demonstrated
 The hybrid substrate is obtained using a layer transfer technique in
which the bonded wafer and the handle wafer have different crystal
orientation. An additional photo step is used to etch through the SOI
and BOX and expose the surface of the handle wafer to perform SEG
 Issues : limited scalability of bulk devices and increased process
complexity
[M. Yang et al.,
IEDM 2003]
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Mobility Enhancement Techniques
Process-based Induced Stess
Substrate-based
SixGe1-x Based
Bulk
SSOI
Tensile bi-axial stress
nMOS+pMOS
Si
SiGe
BULK
Cristal
Orientation
Out of plane
In-plane
Natural mobility boost
pMOS
Mod.Orientation Si
Channel
Liners
CESL
SMT
Tensile
Tensile
nMOS
nMOS
SiGe SEG
STI
SiGe SD
SACVD
Compressive
Tensile
Bi-axial
nMOS+pMOS
Compressive
pMOS
pMOS
box
SSOI
Rotated
substrate
Cristal
Orientation
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Strain and mobility
Low field mobility
Electrons
+
Holes
+
Biaxial compressive
-
+
Uniaxial tensile (along Lg)
+
-
Uniaxial compressive (along Lg)
-
+
Biaxial tensile
Biaxial tensile
Uniaxial compressive
(along Lg)
Uniaxial tensile
(along Lg)
[F. Payet, L2MP PhD, 2006]
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Uniaxial Stress By Stressed-Liner
Strained MOSFET
(Lg=30nm) by
CESL
2D mecanical
Simulations
Impact on nMOSFETs performances
1.E-06
Vdd=0.9V
CESL Tensile
Strained
Ioff (A/µm)
Unstrained
Tension
+15.6%
1.E-07
1.E-08
250
(F.Bœuf et al., IEDM 2004 , SSDM 2004)
450
650
Ion (µA/µm)
850
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Hole Mobility enhancement using Rotated Substrates
<100>
45°
<110>
-5
<110>
-5.5
<100>
Current
Flow
Ioff Log[A/µm]
-6
-6.5
-7
+15%
-7.5
-8
-8.5
-9
0.4
0.6
0.8
1
Ion [a.u.]
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Uniaxial Stress using SiGe S/D
1.E-06
1.E-07
Ioff [A/µm]
T.Korman
n
ha
l
ne
pM
O
SiGe SD <110>
S
Wafer #1 and #2
-c
0>
0
<1
+20%
+15%
1.E-08
1.E-09
250
300
350
400
450
500
Ion [µA/µm]
550
600
650
700
Courtesy, F.Payet
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Gate Capacitance Scaling :
High-K dielectrics
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Figthing against Gate Leakage
C ox 
Leakage issue
Ec
Ef
Ev
Ef
Ec
ε ox
Tox Reducing Tunneling…
Increasing Tox !
But without reduction of Cox !
Increasing permitivity
 HIGH K materials
Ev
Substrate Si
SiO2
P
Gate N+
Wpd
Polydepletion issue
Replacing Poly-Si by Metal
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Figthing against Gate Leakage
Context

Down to 90nm gate length, N+ and P+ polysilicon gate was used for CMOS
integration compatible with oxide or oxynitride gate dielectric.

Due to aggressive scaling of the gate dielectric, the gate leakage is becoming
unacceptably high (>Ioff), requiring the use of high-k dielectric

Due to the incompatibility of polysilicon gate with high-k dielectric (Fermi pinning,
large Vt, mobility degradation) and the need to boost performance (elimination of
polydepletion, boron penetration,…), metal gate electrodes will likely be needed

For bulk technology, two metals with WFs close to the bandgap edges are
needed (high channel doping required to control SCE).

For FDSOI or double gate devices, WFs within 250meV from midgap are
preferred, requiring more complex integration

Two integration approaches are considered: gate first and gate last.
52
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
High-k dielectric
For EOTs below 20Å, gate leakage current
becomes higher than off-state leakage current.
High-k dielectric

Pre-deposition clean and post deposition
anneals affect the quality of high-k

10
Jg ON (A/Cm²)
High-k (HfO2, ZrO2, Hf-based or Zr-based,
LaO2, Al2O3,…
ALCVD or MOCVD deposition

100
Large Vt: Fermi pinning at the poly-Si/
Metal oxide interface but occurs also metal gate electrodes

2 Dec
1
0,1
FD SOI nMOS, Vg = 1.1V
Exp data.
MASTAR
Poly-Si/SiON
1 Dec
0,01
0,001
MG/SiON
2 Dec
0,0001
0,00001
17
MG/Hf SiON
MG/HfO2
19
21
23
25
27
CET (A)
C. Fenouillet et al IEDM 2007
Compatibility of polysilicon gate with high-k is unlikely !
 High-K  At an equivalent CET
of SiON dielectric, the gate
leakage current is reduced by
more than 2 decades
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
High-k Dielectric : Issues

Mobility degradation
- Many publications have reported mobility degradation using high-k
dielectrics.
- Possible cause is coupling of soft optical phonons in high-k with inversion
channel charge carrier

Vt instabilities and reliability and noise issues

Large k and large dielectric thickness result in fringing field (FIBL)
and loss of control of the channel by the gate
B. Tavel et al, PhD Thesis 2002
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Gate Capacitance Scaling :
Metal Gates
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Choosing The « Good Metal »
Vth  V FB 
Ec
nMOS Gate
poly-Si N+
Qdep
C ox
 2 F
Metal Gate « N+like »
1.12V
Mid-gap Gate
Ev
pMOS Gate
poly-Si P+
Metal Gate « P+like »
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Metal gate integration

The use of metal gate suppress:
– the polysilicon depletion : a reduced CET of 3-5Å for performance
improvement
– and suppress the boron penetration problem

Two approaches have been proposed: gate first or gate last
– Gate first approach requires to take care of FE contamination tool, metal
etching and to the high temperature anneal
– Gate last approach (replacement gate): dummy gate removal and
replacement, gate dielectric integrity has to be kept
But for some applications CMOS requires 2 different metal gates in order to
separate WFs for NMOS and PMOS devices (Dual metal gate integration)
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Why is Metal Workfunction so important ?
Regular Poly-gate n+/p+
Dual n+/p+ Metal Gate
Mid-gap Metal Gate
Log Id
Log Id
Vth,p
Vth,n
Vg
Log Id
+0.5V
+0.5V
Vth,p
Vth,n
Vth,p
Vg
Id
Id
Id
Vth,n
Ion,p
Ion,n
Vg
+25%
Polydep
reduction
Ion,n
Ion,p
Ion,p
Vdd
Vdd
Vg
Vdd
Ion,n
Vdd
Vg
Vdd
Vdd
Vg
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Metal gate interest for FDSOI
 Why midgap metal gate ?
V th (V) @ V d=|0.1V|
1
0.8
L g= 200 nm, T
= 145 nm,
BOX
T Si= 8 nm, Tox = 1.9 nm
0.6
pFET Midgap gate
0.4
 Midgap
electrode
 Why
high-k ?with
undoped channel :
symmetrical Vth for NMOS
and PMOS for high Vth
applications
nFET Midgap gate
0.2
P+ like gate
0
-0.2
1.E+16
N+ like gate
1.E+17
1.E+18
Channel doping (cm -3)
1.E+19
 With Band edge gate
electrodes (as poly-Si),
FDSOI requires very high
channel doping > 8e18
at/cm3 for HVT -> Variability
degradation
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Device Architecture
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Device Architecture
Xj
Tdep
Bulk
Scalability ?
GP
PD SOI
Scalability
as BULK

SCE  0.64 si  EI  d
 ox
EI  1
EI  1

X 2j 

x 1
 L 2
el 

T Tdep
 ox
Lel Lel
2 

X
j 
 1 
 L 2
el 

T Tdep
 ox
Lel Lel
FD SOI
Scalability may
be better or
worse (GP,BOX)
FD SON
Scalability
much improved
if GP

DIBL  0.8 si  EI Vds
 ox
DG
(Delta, FinFET,
SON, Vertical,
TriGate, Omega,
etc., etc.
Scalability very
much improved
REF.:T. Skotnicki, invited paper
ESSDERC 2000, pp. 19-33, edit.
Frontier Group
EI  1
EI  1
EI  0.5 
2 

T
si

 1 
2
 L 
el 

T T  Tbox
 ox si
Lel
Lel
2 

T
 1  si 
 L 2
el 

T T  Tbox
 ox si
Lel
Lel
 T2 /4
 1  si 

Lel 2 

T T /2
 ox si
Lel Lel
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Layout and basic functions
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Logic Applications
Basic Functions
inverter
Complex Function
(MP4 Decoder,
µProc,
Motion
Detector, TVDH …)
NAND
SRAM
Layout
Silicon
Layout
Layout
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Layout of the transistor
Gate
Metal 1
Contact
Gate
Source
Drain
Metal 1
Source
Metal 1
Drain
Contact
Contact
Vg>0
0
Vd>0
Metal
Si=Active
isolation
Oxide
n+
Si (p)
n+
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Design rules

W
Poly-contact
Activecontact
Design Rule Manual (DRM)
– Document that gives the
design rules for a technology
Poly-active node
– Gives the minium dimensions
for each level
– Give the minium distance
between two levels

Diam. contact
The design rules give the
maximum density achievable
for a technology node
Si=Active
Lpoly
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Circuit cross-section
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
FEOL & BEOL
Metal 6
Metal 5
BEOL = Back End Of Line
Metal 4
Metal 3
Metal 2
Metal 1
MOSFETs
FEOL=Front End of Line
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C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011