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Module 2 Introduction to AVR ATMega32 Architecture Chip Plastic case Pins Processor Architecture & Organization • Architecture – attributes of a system visible to a programmer – these attributes have a direct impact on the logical execution of a program • Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques – Design issue: whether a computer will have a specific instruction. • e.g. Is there a multiply instruction? 20112012-I Module 2/2 Processor Architecture & Organization • Organization – the operational units and their interconnections that realize the architectural specifications • (how features are implemented) – hardware details that are transparent to the programmers – Control signals, interfaces, memory technology – Design issue: how this instruction is to be implemented. • Is there a hardware multiply unit or is it done by repeated addition? • Split caches or unified cache 20112012-I Module 2/3 Processor Architecture & Organization • Many computer manufacturers offer a family of computer models, all with the same architecture but with differences in organization. • This gives code compatibility (at least backwards) – All Intel x86 family share the same basic architecture – The IBM System/370 family share the same basic architecture • An architecture may survive many years, but its organization changes with the changing technology. – E.g. the IBM Systems/370 architecture, with few enhancements, has survived to this day as the architecture of IBM's mainframe product line. 20112012-I Module 2/4 Introduction to Atmel AVR • Atmel Corporation is a manufacturer of semiconductors, founded in 1984. • Atmel introduced the first 8-bit flash microcontroller in 1993, based on the 8051 core. • In 1996, a design office was started in Trondheim, Norway, to work on the AVR series of products. • Its products include microcontrollers (including 8051 derivatives and AT91SAM and AT91CAP ARM-based micros), and its own Atmel AVR and AVR32 architectures. 20112012-I Module 2/5 Introduction to Atmel AVR • The AVR architecture was conceived by two students at the Norwegian Institute of Technology (NTH) Alf-Egil Bogen and Vegard Wollan. • The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time. • The AVR is a modified Harvard architecture machine where program and data is stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions. • Atmel says that the name AVR is not an acronym and does not stand for anything in particular. The creators of the AVR give no definitive answer as to what the term "AVR" stands for. However, it is commonly accepted that AVR stands for Alf (Egil Bogen) and Vegard (Wollan)'s Risc processor" 20112012-I Module 2/6 Harvard Architecture Howard Hathaway Aiken The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. In a Harvard architecture, there is no need to make the two memories share characteristics. In particular, the word width, timing, implementation technology, and memory address structure can differ. In some systems, instructions can be stored in read-only memory while data memory generally requires read-write memory. In some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses. 20112012-I Module 2/7 Von Neumann Architecture John von Neumann In contrast with the Harvard architecture, the Von Neumann architecture has a single storage structure to hold both instructions and data. The CPU can be either reading an instruction or reading/writing data from/to the memory because instructions and data use the same bus system. The phrase Von Neumann architecture derives name of the mathematician and early computer scientist John von Neumann. The meaning of the phrase has evolved to mean a stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the Von Neumann bottleneck and often limits the performance of the system. 20112012-I Module 2/8 Modified Harvard Architecture A modified Harvard architecture machine is very much like a Harvard architecture machine, but it relaxes the strict separation between instruction and data while still letting the CPU concurrently access two (or more) memory buses. The most common modification includes: • Separate instruction and data caches backed by acommon address space. While the CPU executes from cache, it acts as a pure Harvard machine. When accessing backing memory, it acts like a von Neumann machine (where code can be moved around like data, a powerful technique). This modification is widespread in modern processors such as the ARM architecture and X86 processors. • Provides a pathway between the instruction memory (such as ROM or flash) and the CPU to allow words from the instruction memory to be treated as read-only data. This technique is used in some microcontrollers, including the Atmel AVR. This allows constant data, such as text strings or function tables, to be accessed without first having to be copied into data memory, preserving scarce (and power-hungry) data memory for read/write variables. Special machine language instructions are provided to read data from the instruction memory. (This is distinct from instructions which themselves embed constant data, although for individual constants the two mechanisms can substitute for each other.) 20112012-I Module 2/9 Processor ISA: RISC versus CISC CISC RISC Emphasis on hardware Emphasis on software Include multi-clock complex instructions Include single-clock reduce instruction only Memory-to-memory: “Load” and “Store” incorporated in instructions Register-to-register: “Load” and “Store” are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers • RISC vs. CISC is a topic quite popular on the Net. Every time Intel (CISC) or Apple (RISC) introduces a new CPU, the topic pops up again. • Most PC's use CPU based on CISC architecture. For instance Intel and AMD CPU's are based on CISC architectures. • Many claim that RICS is the architecture of the future. • But even though RISC has been in the market since 1980, it hasn’t managed to kick CISC out of the picture, some argue that if it is really the architecture of the future it should have been able to do this by now. 20112012-I Module 2/10 AVR different groups • Classic AVR – e.g. AT90S2313, AT90S4433 • Mega – e.g. ATmega8, ATmega32, ATmega128 • Tiny – e.g. ATtiny13, ATtiny25 • Special Purpose AVR – e.g. AT90PWM216,AT90USB1287 Let’s get familiar with the AVR part numbers ATmega128 Atmel group ATtiny44 Atmel Tiny group Flash =4K Flash =128K AT90S4433 Atmel Classic group 20112012-I Flash =4K Module 2/12 ATMega32 Pin out & Descriptions ClearsPort all theB registers supply and Provides restart voltage to the the chip. These pins are execution of It should be used to connect program connected to +5 external crystal or RC oscillator Port A Reference voltage for ADC Supply voltage for ADC and portA. Connect it to VCC Port C Port D 20112012-I Module 2/13 ATMega32 Pin out & Descriptions 20112012-I Module 2/14 ATMega32 Pin out & Descriptions 20112012-I Module 2/15 ATMega32 Pin out & Descriptions Digital IO is the most fundamental mode of connecting a MCU to external world. The interface is done using what is called a PORT. A port is the point where internal data from MCU chip comes out or external data goes in. They are present is form of PINs of the IC. Most of the PINs are dedicated to this function and other pins are used for power supply, clock source etc . ATMega32 ports are named PORTA, PORTB, PORTC, and PORTD. 20112012-I Module 2/16 20112012-I Module 2/17 ATMega32 Pin out & Descriptions (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP) PD6 20112012-I PINB (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 DDRB PORTB Mega32/Mega16 PINA DDRA PORTA PORTC DDRC PINC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF AGND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2) Module 2/18 ATMega32 Pin out & Descriptions 20112012-I Module 2/19 ATMega32 Pin out & Descriptions Defining a pin as either Input or Output – The DDRx Registers LDI R20,0xFF OUT PORTx,R20 ;PORTA = R20 OUT DDRx,R20 DDRx = 0b01110101; 20112012-I ;R20 = 0b01110101 (binary) ;DDRA = R20 /* Configuring I/O pins of portb */ Module 2/20 ATMega32 Pin out & Descriptions Case 1 : To make a pin go high or low ( if it is an output pin)- Data Register PORTx 20112012-I Module 2/21 ATMega32 Pin out & Descriptions Pull-up resistors are used in electronic logic circuits to ensure that inputs to logic systems settle at expected logic levels if external devices are disconnected or high-impedance vcc 1 = Close PORTx.n pin n of port x Outside the AVR chip 0 = Open PINx.n Inside the AVR chip 20112012-I Module 2/22 ATMega32 Pin out & Descriptions DDRx.n 0 1 0 high impedance Out 0 1 pull-up Out 1 PORTx PORTx.n PINx.n 20112012-I DDRx Case 2 : To activate / Deactivate pull up resistors-Data Register PORTx Module 2/23 ATMega32 Pin out & Descriptions The PINx register gets the reading from the input pins of the MCU 20112012-I Module 2/24 AVR Architecture 20112012-I Module 2/25 ATMega32 Architecture • • • • Native data size is 8 bits (1 byte). Uses 16-bit data addressing allowing it to address 216 = 65536 unique addresses. Has three separate on-chip memories • 2KB SRAM • 8 bits wide used to store data • 1KB EEPROM • 8 bits wide used for persistent data storage • 32KB Flash • 16 bits wide used to store program code I/O ports A-D • Digital input/output • Analog input • Serial/Parallel • Pulse accumulator 20112012-I Module 2/26 ATMega32 Programmer Model: Memory 1. 2KB SRAM – For temporary data storage – Memory is lost when power is shut off (volatile) – Fast read and write 2. 1KB EEPROM – For persistent data storage – Memory contents are retained when power is off (non-volatile) – Fast read; slow write – Can write individual bytes 3. 32KB Flash Program Memory – Used to store program code – Memory contents retained when power is off (non-volatile) – Fast to read; slow to write – Can only write entire “blocks” of memory at a time – organized in 16-bit words (16KWords) 20112012-I Module 2/27 ATMega32 Programmer Model: Memory • AVR microcontrollers are Harvard architecture. This means, that in this architecture are separate memory types (program memory and data memory) connected with distinct buses. Such memory architecture allows processor to access program memory and data memory at the same time. This increases performance of MCU comparing to CISC architecture, where CPU uses same bus for accessing program memory and data memory. • Each memory type has its own address space: Type Flash RAM EEPROM F_END Size, kB RAMEND Size, kB E_END Size, kB Atmega8 $0FFF 8 $045F 1 $1FF 0.5 Atmega32 $3FFF 32 $085F 2 $3FF 1 Atmega64 $7FFF 64 $10FF 4 $7FF 2 Atmega128 $FFFF 128 $10FF 4 $FFF 4 20112012-I Module 2/28 ATMega32 Programmer Model: Program Memory Flash Memory Layout 20112012-I Module 2/29 ATMega32 Programmer Model: Data Memory EEPROM • ATmega32 contains 1024 bytes of data EEPROM memory. • It is organized as a separate data space, in which single bytes can be read and written. • The EEPROM has an endurance of at least 100,000 write/erase cycles. • Different chip have different size of EEPROM memory Chip Bytes Chip Bytes Chip Bytes ATmega8 512 ATmega16 512 ATmega32 1024 ATmega64 2048 ATmega128 4096 ATmega256RZ 4096 ATmega640 4096 ATmega1280 4096 ATmega2560 4096 20112012-I Module 2/30 ATMega32 Programmer Model: Data Memory The data memory is composed of three parts: • GPRs (general registers), purpose • Special Function Registers (SFRs), and • Internal data SRAM. 20112012-I Module 2/31 ATMega32 Programmer Model: Internal SRAM • Internal data SRAM is widely used for storing data and parameters by AVR programmers and C compilers. • Each location of the SRAM can be accessed directly by its address. • Each location is 8 bit wide and can be used to store any data we want. • Size of SRAM is vary from chip to chip, even among members of the same family. 20112012-I Module 2/32 ATMega32 Programmer Model: Registers 20112012-I Module 2/33 ATMega32 Programmer Model: Registers (GPRs) The fast-access Register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register file, the operation is executed, and the result is stored back in the Register file –in one clock cycle.” 20112012-I Module 2/34 ATMega32 Programmer Model: Registers (GPRs) “Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-register, Yregister and Z-register, described later.” 20112012-I Module 2/35 ATMega32 Programmer Model: Registers (GPRs) The R26..R31 registers have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are shown above. In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement 20112012-I Module 2/36 ATMega32 Programmer Model:I/O Registers (SFRs) • • • The I/O memory is dedicated to specific functions such as status register, timers, serial communication, I/O ports, ADC and etc. Function of each I/O memory location is fixed by the CPU designer at the time of design. (because it is used for control of the microcontroller and peripherals) AVR I/O memory is made of 8 bit registers. • All of the AVRs have at least 64 bytes of I/O memory location. (This 64 bytes section is called standard I/O memory) • In other microcontrollers, the I/O registers are called SFRs (Special Function Registers) Address I/O $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 Name Mem. $20 TWBR $21 TWSR $22 TWAR $23 TWDR $24 ADCL $25 ADCH $26 ADCSRA $27 ADMUX $28 ACSR $29 UBRRL $2A UCSRB $2B UCSRA $2C UDR $2D SPCR $2E SPSR $2F SPDR $30 PIND $31 DDRD $32 PORTD $33 PINC $34 DDRC $35 PORTC 20112012-I Address I/O $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F Mem. $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F $20 $40 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A Name PINB DDRB PORTB PINA DDRA PORTA EECR EEDR EEARL EEARH UBRRC UBRRH WDTCR ASSR OCR2 TCNT2 TCCR2 ICR1L ICR1H OCR1BL OCR1BH OCR1AL Address I/O $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3E Name Mem. $4B OCR1AH $4C TCNT1L $4D TCNT1H $4E TCCR1B $4F TCCR1A $50 SFIOR OCDR $51 OSCCAL $52 TCNT0 $53 TCCR0 $54 MCUCSR $55 MCUCR $56 TWCR $57 SPMCR $58 TIFR $59 TIMSK $5A GIFR $5B GICR $5C OCR0 $5D SPL $5E SPH $5E SREG Module 2/37 ATMega32 Programmer Model: Registers (SP) 20112012-I Module 2/38 ATMega32 Programmer Model: Registers (SP) 20112012-I Module 2/39 ATMega32 Programmer Model: Registers (PC) Program counter (PC, 16-bit) Holds address of next program instruction to be executed Automatically incremented when the ALU executes an instruction 20112012-I Module 2/40 ATMega32 Programmer Model: Registers (SR) 20112012-I Module 2/41 ATMega32 Programmer Model: Registers (SR) 20112012-I Module 2/42 ATMega32 Programmer Model: Registers (SR) 20112012-I Module 2/43 ATMega32 Programmer Model: Registers (SR) 20112012-I Module 2/44 ATMega32 Programmer Model: Registers (SR) 20112012-I Module 2/45 ATMega32 Programmer Model: Registers (SR) SREG: I T H Interrupt S N V Z oVerflow Temporary Half carry C Zero Carry Negative Sign N+V Data Address Space ... Example:Show Showthe thestatus statusof ofthe theC, C,H, H,and and Zflags flagsafter afterthe theaddition subtraction of Example: Show the status of the C, H, and flags after the subtraction of $0000 Example: ZZ of Example: Show the status of the C, H, and Z flags after the addition of 0x38 $0001 General 0x9C from0x64 0x9C in the following instructions: 0x23 from in the following instructions: 0x730x2F from 0x52 0x9C and the following instructions: and in0xA5 theinfollowing instructions: Purpose LDI 0x38 R20, 0x9C 0x9C Registers LDI R20, 0xA5 0x52 R20, LDI LDI R16, ;R16 = 0x38 SREG: … ADD I T H S V N Z C Solution: Solution: Solution: Solution: CPU R15 11 0101 R16 0010 1001 1100 1010 0101 0011 1000 1001 1100 R17 0011 0111 Registers $005F SPH SREG ... $0060 $52 General $9C $A5 $38 $9C purpose - $23 $73 $9C 10010100 1100 0010 0011 $2F 1111 +-- +$64 0110 RAM $DF 1101 1111 R20 = $DF PC $00 0000 0000 R20 = $00 $82 1000 0010 R20 $82 (SRAM) $67R211is0000 0110 0111 R16is==a00 0x67 $100 R20 C = 1 because bigger0000 than R20 and there borrow from D8 bit. … C===100because becausethere R21 is is not bigger than R20 R20 andbit. there is is no no borrow borrow from from D8 D8 bit. bit. C because R21 bigger than and there C isnot a R30 carry beyond the D7 H = 1 because there is a R31 borrow from D4D3 toto D3. carry from the the D4 bit. H = 0 because there is no borrow from D4 to D3. H = 0 because there is no borrow from D4 to D3. Z = 1 because the R20 (the result) has a value 0 in it after the addition. Instruction Register Z = 0 because the R16 (the result) has a value other than 0 after the addition. Z == 00 because the R20 a value otherthe than after the subtraction. C because there is has no carry beyond D7zero Instruction decoder because there the R20 R20 iscarry zero after the D3 subtraction. ZZ = == 1 01 because because the a value other than 0 bit. after the subtraction. H is ahas from the to the D4 bit. registers $FFFF IO Address $00 $01 ... LDI ... ALU R0 $001F R1 0x64 TWBR LDI 0x2F R21, 0x9C LDI R21, 0x23 0x73 $0020 LDI R21, R17, ;R17 = 0x2F TWSR R2 StandardR21 IO from SUB R17R20, R20, R21 R21;add R17;add ;subtract R20 SUB R20, R21 ;subtract ADD R21 toR21 R20from R20 R16, to R16 $3E $3F