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Paper Discussion
Reim Doumat & Thomas Watteyne
« Simulation of Soc
Architectures »
« Overview of the Ptolemy Project »
Jul. 2003
« Modeling and Simulation Issues of Programmable
Architectures »
Mar. 2001
« Rapid System-Level Performance Evaluation and
Optimization for Application Mapping onto SoC Architecures »
Oct. 2002
« Modeling and Simultaion of Embedded Processors Using
Abstract State Machine »
Mar. 2001
General Overview
Introduction to Modeling, Design and
Simulation
“Rapid System-Level Performance Evaluation
and Optimization for Application Mapping
onto SoC Architectures”
“Modeling and Simulation of Embedded
Processors Using Abstract State
Machines”
3
Part I
Introduction to Modeling, Design
and Simulation
Overview
I.
Introduction
II.
Machine and Hardware Description
Languages, the LISA example
III. Models of computation, the Ptolemy
example
5
Introduction
Push-pull
effect
The push-pull effect
Definitions
MDL, HDL
Computation Models
Designer
productivity
New
applications
System
complexity
!!
Semiconductor
technology
Time-to-market
6
Introduction
The push-pull effect
Push-pull
effect
Definitions
MDL, HDL
Computation Models
• productivity
• re-usability
In embedded system design
• flexibility
 Effective design phase
7
Introduction
Push-pull effect
Definitions
Definitions
MDL, HDL
Computation Models
• Modeling : representing an architecture
(mathematical model, constructive model)
• Design : defining an architecture
• Simulation : executable model
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Introduction
Why LISA ?
MDL, HDL
Why LISA ?
Overview
LISA
Language for Instruction Set Architecture
ASIC, DSP…
processors
Validation
Computation Models
Electronic
systems
Programmable
Architecture
Code generation and simulation tools :
• simulator
• assembler
• linker
• graphical debugger
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Introduction
MDL, HDL
Programmable Architecture overview
Why LISA ?
Overview
LISA
User Application
Validation
Computation Models
ex: POSIX
Machine Description
Language
Operating System
(ex : LISA)
Instruction Set
Hardware
(processor)
Hardware Description
Langage
(ex : VHDL, Verilog)
10
Introduction
LISA
MDL, HDL
Why LISA ?
Overview
LISA
processor
description
LISA
Validation
Generic
Processor
model
Computation Models
processor model
debugger
simulator
Simulator compiler
assembler
linker
Software developpement environment
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Introduction
Validation
MDL, HDL
Why LISA ?
Overview
• simulation speed
LISA
(x1000 instruction/cycles
per second)
Validation
Computation Models
Use of compilation
simulation
• assembler/linker speed
equivalent
LISA  VHDL ?
12
Introduction
MDL, HDL
Computation Models
Computation Models
« Overview of the Ptolemy Project »
Jul. 2003
13
Ptolemy II - Introduction
Introduction
MDL, HDL
Computation Models
Introduction
Ptolemy Project
Models
Choosing
Introduces:
- Domain polymorphism
- Modal Models
?
Ptolemy II
(1996–to date)
Facts
Ptolemy Classic
(1990–1997)
Gabriel
(1986–1991)
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Introduction
MDL, HDL
Ptolemy - Introduction
Computation Models
Introduction
Ptolemy Project
Models
Choosing
Facts
Definition: The project studies
- modeling,
- simulation,
- design of concurrent, real-time, embedded systems
Characteristics:
- Components built on top of Java compiler (Soot)
- XML as data representation
- Concept of migrating models
15
Introduction
MDL, HDL
Ptolemy Project
Computation Models
Introduction
Complete separation of the abstract synthax from the semantics.
Ptolemy
Models
Choosing
Facts
• Synthax, Actor-Oriented design :
- models, actors, ports, parameters, channels
- represented graphically, XML or by program with specific API
• Semantics, the “physical laws” :
- models constructed under model of computation
- choice of model of computation has deep impact on implementation
- interoperability of executable models
- hierarchical mix of domains
16
Introduction
MDL, HDL
Example of the actor oriented design
Computation Models
Introduction
Ptolemy
Models
Choosing
Facts
17
Introduction
MDL, HDL
Ptolemy II- Modeling and Design
Computation Models
Introduction
Ptolemy
Models
Choosing
Facts
18
Introduction
MDL, HDL
Ptolemy – Modeling & Design
Computation Models
Introduction
Ptolemy
Models
Choosing
Facts
Focus on:
- Embedded software
- Actor oriented design (Version 4.0.1)
- Architecture Design
1) Components designed to be domain
polymorphic
2) Interaction mechanisms among domains
3) Development of a meta-model describing
models of computation
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Introduction
MDL, HDL
Models of Computation
Computation Models
Introduction
Ptolemy
Models
Choosing
• At least 12 different models of computation
Facts
• Variety of models because :
time (continuous, discrete, causal)
concurency, interactions
different underlying mathematical models
20
Introduction
Models of Computation
MDL, HDL
Computation Models
Introduction
Ptolemy
Models
• Component Interaction (Demand-Driven, e.g. Web Browsers)
• Communication Sequential Processes (use of rendez-vous)
Choosing
• Continuous Time
Facts
• Discrete-Events
• Distributed Discrete Events
• Discrete Time
• Finite-State Machines
• Process Networks
• Synchronous Dataflow
• Giotto (hard real time)
• Synchronous/reactive
• Timed Multitasking
21
Introduction
MDL, HDL
Choosing a Model of Computation
Computation Models
Introduction
Ptolemy
Models
Choosing
Facts
• Most designer faced to only one or two
• Choice is very important (time, event, etc.)
Unifying not possible ... (complex)
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Introduction
MDL, HDL
Ptolemy II –What’s the Architecture?
Computation Models
Introduction
Ptolemy
Models
Choosing
Facts
• Core packages: support data model and actor model
• User Interface packages: support XML file format (MoML)
• Library packages: define actors to be domain polymorphic
• domains : subpackages of ptolemy domains package
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Introduction
MDL, HDL
Ptolemy II – some capabilities
Computation Models
Introduction
Ptolemy
Models
Choosing
Facts
•Higher level concurrent design in Java
•Better modularization through the use of packages
•Complete separation of the abstract syntax from the
semantics
•Domain-polymorphic actors
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Introduction
Ptolemy in facts
MDL, HDL
Computation Models
Introduction
• 3rd generation : Ptolemy II
Ptolemy
• Java as a programming language
Models
Choosing
• Visual synthax
Facts
• Set of packages
25
Part II
“Rapid System-Level Performance Evaluation and
Optimization for Application Mapping onto SoC
Architectures”
October 2002
Sumit Mohanty, Viktor K. Prasanna
Introduction
Introduction
GenM
HiPerE
MILAN
conclusion
GenM
Evaluation& optimization of performance
During application design
HiPerE
Estimation at the system level
MILAN
Estimation of specific component
performance
27
Introduction
GenM
HiPerE
Generic Model for Application Mapping
onto SoC Architecture
MILAN
conclusion
DVS (Dynamic Voltage
Scaling)
Components of the GenM Model
28
Introduction
GenM
Why to use GenM?
HiPerE
MILAN
conclusion
• Rapid estimation of performance.
•Development of efficient application designs
(High Level abstraction).
•Development of optimization techniques for mapping
application onto SoC architecture.
29
Introduction
GenM
HiPerE
HiPerE (High-Level Performance Estimator)
MILAN
-Interpretive simulator
conclusion
-system-level performance estimation
GenM (Target SoC architecture)Estimation of Systemlevel energy & latency
Performance parameters
Application Task Graph
HiPerE
Activity Report for Each
component in the target
architecture
30
Introduction
GenM
Component Specific Performance Estimation
MILAN(Model based Integrated simuLAtioN
HiPerE
Application
Model
Program
Implementing
The Task
Source
code
Update Energy
And Latency
Estimates
MILAN
Component
Specific
Estimates
Configure
conclusion
Resource
Model
Feedback
MILAN
Low-level
simulator
Component specific Performance Estimation using MILAN
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Introduction
GenM
Performance estimation includes?
HiPerE
MILAN
conclusion
•Cost for execution
•Data access
•Memory activation
•reconfiguration
32
Introduction
GenM
Application Optimization Using MILAN
HiPerE
MILAN
conclusion
Hierarchical Simulation for DES in MILAN
33
Introduction
GenM
Application Optimization Using MILAN
HiPerE
MILAN
conclusion
34
Introduction
GenM
Conclusion
HiPerE
MILAN
conclusion
By using (GenM,HiPerE,MILAN)
solve these problems:
•Estimation of system-level performance for SoC
architectures.
•Lack of high-level abstraction for SoC architectures.
•Lack of standard interface between different component
simulators.
35
Part III
“Modeling and Simulation of Embedded Processors
Using Abstract State Machines”
March 2001
Dirk Fischer, Jurgën Teich, Ralph Weper
Overview
I.
Architecture/compiler co-design
II.
Abstract State Machines
III. The BUILDABONG project
IV. Paper’s Interest
37
I.
Architecture/Compiler co-design
in ASIPs
co-design
The needs
Needs
Process
Related work
“ - ASIP ASAP ? ”
ASMs
BUILDABONG
Interest
Application
Specific Instruction
Set Processors
As soon as possible
• customized
processors
ASIP
• special
applications
(signal
processing…)
• time to market
ASAP
• optimal
application/processor
tradeoff
39
co-design
Process
Needs
Process
Related work
ASMs
BUILDABONG
Interest
• Simple instruction set
• complex instruction
set
• Complex application
• simple application
More computation
time, more memory
Application
Processor
More design /
manufacturing process
costs
Architecture/compile
r co-design
Exploration
Simulation
40
co-design
Needs
work on architecture/compiler co-design
Process
Related work
• LISA University of Aachen, Germany
ASMs
BUILDABONG
Compiled simulator  100K instructions per second
Interest
• CASTEL
VHDLRTL
DATA PATH MODELextended FSM
• EXPRESSION University of California, USA
Retargetable
compiler
V-SAT
EXPRESSION
Graphical Design
Environment
model
Cycle accurate
simulator
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II. Abstract State Machines
co-design
The Mathematics
ASMs
Mathematics
Modeling
Advantages
BUILDABONG
<= ?
Interest
>?
<?
>= ?
== ?
== ?
== ?
universe
• Functions
• Relations
structure 
Algebra
43
co-design
The Mathematics
ASMs
Mathematics
Modeling
Abstract State Machine
Advantages
BUILDABONG
Μ = (V, f1, f2, … , fn)
Interest
Finite
vocabulary
Finite set of n-ary
functions over V
(State of M ≡ algebra over V )
Initial state S0 + set of transition rules P = ASM
44
co-design
The Mathematics
ASMs
Mathematics
Modeling
Transition Rule
Advantages
BUILDABONG
Interest
No relations  boolean
value
If
<cond>
then
<Rule>
endif
Update rule
f(t1, t2, … , tn) := t
45
co-design
The Mathematics
ASMs
Mathematics
Modeling
Operationnal semantics
Advantages
BUILDABONG
Interest
Update
rule
R
Si
R
Si+1
state
No
cycling…
Si+2
Sn
R
Terminal
state
46
co-design
Modeling processors with ASMs
ASMs
Mathematics
Modeling
Advantages
BUILDABONG
Interest
• cycle accurate model, register transfer level
• a register tranfer is conditionned (mode registers, instruction
bits)
• “guarded register transfer paterns” (Leupers)
If
<register_transfer_condition>
then
 ASMs
<register_transfer_pattern>
endif
47
co-design
Advantages
ASMs
Mathematics
Modeling
Advantages
• short description (ARM7, 200 lines XASM)
BUILDABONG
Interest
• readability
• cycle accuracy
• simulation speed (?)
• XASM environment supports C-libraries (irregular arithmetic
operations on arbitrary large word-lengths)
• “natural” mathematical tool
48
III. The BUILDABONG project
co-design
General View
ASMs
BUILDABONG
General view
Editor
XASM
Explorer
ANSI C
Program
Graphical
input
Retargetable
Compiler
ArchitectureComposer
Simulator
Future work
Interest
Assembler
Program
ASM Generator
Instruction Set
Description
ASM
library
Simulator Generator
(Gem-Mex)
Parser
Linker
Loader
Simulator
50
co-design
ASMs
Graphical Architecture Editor
BUILDABONG
General view
Editor
XASM
Simulator
Future work
Interest
• libraries
• hierarchical
51
co-design
ASMs
XASM-code generation
BUILDABONG
General view
Editor
XASM
Simulator
Future work
Interest
52
co-design
XASM-code generation
ASMs
BUILDABONG
General view
Library include
Editor
XASM
Simulator
Future work
Interest
53
co-design
ASMs
XASM-code generation
BUILDABONG
General view
Function declaration
Editor
XASM
Simulator
Future work
Interest
54
co-design
ASMs
XASM-code generation
BUILDABONG
General view
Sequential element initialization
Editor
XASM
Simulator
Future work
Interest
55
co-design
ASMs
XASM-code generation
BUILDABONG
General view
Guarded update rules (memory and registers)
Editor
XASM
Simulator
Future work
Interest
?
56
co-design
ASMs
Automatic Simulator Generator
BUILDABONG
General view
Editor
XASM
Simulator
Future work
?
Interest
57
co-design
To-Do list…
ASMs
BUILDABONG
General view
Editor
XASM
Explorer
ANSI C
Program
Graphical
input
Retargetable
Compiler
ArchitectureComposer
Simulator
Future work
Interest
Assembler
Program
ASM Generator
Instruction Set
Description
ASM
library
Simulator Generator
(Gem-Mex)
Parser
Linker
Loader
Simulator
58
IV. The paper’s interest
co-design
Criticism
ASMs
BUILDABONG
Interest
• meets the demand
• structured project
• « natural » modeling tool
• but proprietary graphical language
• openings
Fine-tuning of the compiler (different needs)
Conversion tools with HDLs
60