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34 GUIMARÃES et al.: SINGLE-ELECTRON WINNER-TAKE-ALL MACRO BLOCK Single-electron winner-take-all macro block for large-scale integrated neural networks J. G. Guimarães, L. M. Nóbrega and J. C. da Costa Department of Electrical Engineering, Universidade de Brasília, C.P. 4386, Brasília, DF, 70904-970, Brazil, e-mail: [email protected] Abstract—This paper presents a basic block for building large scale single-electron (SET) winner-take-all (WTA) neural networks. This macro block is completely composed of SET circuits: a WTA network, transistors and a digital to analog converter. A character recognition task is implemented. Simulations are done using SIMON and MATLAB. Robustness against background charges and temperature effects are evaluated. Index Terms—single-electron; neural network. block; winner-take-all; I. INTRODUCTION Nanoscale sized devices may become an extremely attractive option for the development of giga (GSI) and even tera (TSI) scaled integrated circuits. Among these devices, Single-Electron Tunneling (SET) devices present attractive features like extremely low power consumption, reduced dimensions, excellent current control and low noise behaviour. These features should allow the realization of chips containing a number of devices orders of magnitude greater than those indicated by the roadmap [1] but still respecting the roadmap' area and power restrictions. As a result a TSI processor should be a feasible challenge in the future. Nanoscale devices, like SETs, may present operating instabilities due to local range phenomena such as background charges and cotunneling events, which may degrade their electrical performance [2]. To overcome these limitations parallel distributed processing (PDP) architectures should be considered [3]. Among PDP architectures, neural networks seem to be a very attractive system [3], presenting robustness against local fluctuation, high parallelism and redundancy [4]. More specifically, competitive nets, like winner-take-all (WTA), provide easiness of operation due to their nonsupervised training [5]. In addition, WTA has a relatively reduced number of control signals, self-organization, local memory and low connectivity when adopting a lateral inhibition configuration [5]. WTA nets are used for decision making, pattern recognition, image feature extraction, Hamming network, image processing, video compression and other tasks [6]. Single-electron devices are quite sensitive to environmental conditions (their behavior is strongly dependent on node impedances and on temperature and electromagnetic interference, as well as on offset charges and cotunneling events). Several measures can be taken to minimize or to overcome these nuisances [2] and they were taken into account in this study. To our knowledge no simulations of the overall behavior of circuits containing different single-electron blocks connected together have ever been presented. This type of study is essential to evaluate the possibility of building complex single-electron device networks. In this work a basic block for building large scale SETWTA neural networks is proposed. Each macro block can be simulated using the well-known SET simulator SIMON [7]. Offset charges were taken into account in these simulations. MATLAB is used to read the ouput of each macro block, providing the output of the whole WTA neural network. The implementation of a large-scale SETWTA network is discussed. II. SINGLE-ELECTRON TUNNELING DEVICES Single-electron tunneling devices are built using tunnel junctions which are formed by two normal metal electrodes sandwiching a thin insulator, as shown in Fig. 1. A tunnel junction can be considered as a leaky capacitor and can be modeled using a capacitance C and a tunnel resistance R that depend on the size of the junction and the barrier thickness. These devices are able to manipulate individual electrons [2]. Charge transfers along these kinds of circuits occur by tunneling events across the barriers. So, charge transfers can only occur across a barrier in multiples of e. As the energy in a capacitor with a charge q is equal to q 2 2C , tunnel events across tunnel junctions will change the electrostatic energy EC of the system as shown in Eq. 1. EC = e2 2C (1) Fig.1 Tunnel junction JOURNAL INTEGRATED CIRCUITS AND SYSTEMS, VOL 1, NO. 3, JULY 2006. 35 III. SINGLE-ELECTRON TRANSISTOR This device has two tunnel junctions in series, as illustrated in Fig. 2. If the junctions are considered as capacitors, when V = 0 and Vg < e/2C the island (region between two or more junctions) [2,8,9] is neutral and q1 =q 2 = CV g 2 , where q1 and q 2 are the charges in the first and second junction, respectively. If an electron tunnels towards the island, its charge will be shared by the capacitances of the two junctions and the gate capacitance Cg . Generally, C g << C , then q1 = (CV g − e) 2 q 2 = (CV g + e) 2 . As the energy supplied by the voltage source during a tunnel event is eV g 2 , the variation in the electrostatic energy ΔE of the circuit will be as shown in Eq. 2. ΔE = e 2 eV − 4C 2 If T << E C k B Fig.2 Single-electron transistor and (2) (i.e. no charge transfer through thermionic emission may occur), a tunnel event will have a significant probability of occurrence only if ΔE < 0 . Consequently, the sign of ΔE will determine whether there is a current or not. So, if V g < e 2C there will be no current and the device is in the Coulomb blockade [2]. On the other way, if V = −e 2C g and V g ≈ 0 , C g will be charged with e 2 , but the island will still be discharged, which means that a charge −e 2 is being divided by the junctions. If a tunnel event happens it will just change the junctions' charges in −e 4 and e 4 , making no difference for the energy. Small values of V g will make electrons pass through the barriers one after another, producing a current. According to that, the gate voltage V is able to regulate the current, making this device work as a transistor [2]. IV. SINGLE-ELECTRON WTA NEURAL NETWORK The SET-WTA circuit [10,11] was derived from a MOS implementation [6]. A 2-neuron SET-WTA circuit is shown in Fig. 3. Each neuron has a primary current input unit I i which brings the data information to the network, and secondary voltage input units ( vi−1 (t ) and vi+1 (t ) ) which come from the nearest neighbors, as illustrated in Fig. 3. These secondary connections provide the stimulation or inhibition features which are characteristic of WTA networks. Neuron 1 receives as inputs the current I1 and the output voltage v 2 (t ) from neuron 2. Its single output voltage is v1 (t ) . The bias voltage Vbias has a fixed value [11]. Resistor Rt and capacitor Ct are responsible for the time constant of the circuit, determining the output convergence time. The SET-WTA circuit identifies the largest output voltage from a set of N neurons, inhibiting the output voltages of the remaining N − 1 units [5,6]. V. SINGLE-ELECTRON WTA MACRO BLOCK The single-electron WTA macro block is presented in Fig. 4. Each macro block has a SET-WTA network with lateral inhibition [11], SET transistors and a SET digital to analog converter [12]. Considering that the goal of this work is the simulation of large-scale SET-WTA circuits, the idea of creating a macro block comes from two basic issues. The first one is the difficulty of editing large circuits on SET simulators. Using the well-know SET simulator SIMON [7], for example, takes a long time because of its "pick and place" editing system. A circuit with 400 tunnel junctions would take weeks to be totally edited with that system. A netlist description of SET circuits can be made in SIMON, but it is also time consuming, tedious and prone to mistakes. The second issue is the processing capability. For example, a SET-WTA circuit with 100 neurons, which means 400 tunnel junctions and 300 capacitors requires the observation of all individual neuron outputs, i. e., 100 nodes. In a Pentium 4, 1.5 GHz, 528 MB RAM only 45 nodes can be observed with SIMON. Taking these issues into consideration, a macro block approach would be useful to overcome those limitations. Fig.3 WTA network structure 36 GUIMARÃES et al.: SINGLE-ELECTRON WINNER-TAKE-ALL MACRO BLOCK Fig. 4 SET-WTA macro block with 4 neurons The whole network can be described by macros. Those macros are small enough to be simulated by SIMON and a transfer function will be determined for each one of them. MATLAB is used to read all macros' outputs and to determine the largest one. Considering a SET-WTA with N neurons. This network JOURNAL INTEGRATED CIRCUITS AND SYSTEMS, VOL 1, NO. 3, JULY 2006. is broken into blocks of n neurons ( n < N ), in such a way that N n macro blocks will be created. Each block is simulated separately. The SET-WTA network provides the winner output. The SET transistors, connected to the output of each neuron are used to normalize its value. From their Coulomb blockade characteristics [2,9] it is possible to have a positive value voltage in the winner output only. This value will be taken as a logic 1 . All other outputs will be taken as logic zeroes. The SET-DAC gives the analog value of the winner neuron in each block. This value is obtained converting the word defined by the output voltage array into its analog equivalent. In all blocks that do not have the winner the DAC will provide a aproximately zero ouput voltage. Only the winner block will provide a value different from zero. MATLAB identifies the winner neuron reading all DAC's outputs. For example, a SET-WTA network with N = 1000 neurons could be broken in blocks of n = 25 neurons, creating 40 circuits for simulation. In the next section, a simulation example will be presented. VI. RECOGNITION TASK In order to check if the proposed macro works as a WTA network, a character recognition task was simulated using it. The system developed in this work is shown in Fig. 5. It is composed of two neural networks: one pre-processing layer and one WTA layer, which was divided into macro blocks. For this task, sixteen exemplar characters P1 , P2 , , P16 [5], shown in Fig. 6, were chosen. Fig.5 Macro system for dot pattern recognition 37 Fig.6 Exemplar characters Moreover, four disturbed characters X 1 , X 6 , X 11 , X 16 were created from exemplar patterns P1 , P6 , P11 , P16 , respectively. These characters were generated introducing noise to 10% of the points of each exemplar and are shown in Fig. 7 [11]. The exemplar characters will be stored in the preprocessing layer weights. These characters will make the partition of the input space into classes [5], one for each exemplar. This pre-processing layer calculates the similarity from disturbed inputs X 1 , X 6 , X 11 , X 16 to each of the stored exemplar characters [10,11]. The simulation of this layer was implemented using MATLAB. The following steps are taken to process the storage. Firstly, all exemplars should be converted into a representation suitable for neural networks [11]. Considering a bipolar representation, for each point was assigned the value 1 if there was a dot in that position and the value -1 if there was not a dot. The outputs provided by the pre-processing layer are adjusted in the range from −0.6nA to 4nA [13], since the WTA inputs are currents. Fig.7 Disturbed characters 38 GUIMARÃES et al.: SINGLE-ELECTRON WINNER-TAKE-ALL MACRO BLOCK The WTA layer was designed using SET neurons shown in Figs. 3 arranged in macro blocks as can bee seen in Fig. 4. In order to check the operation of the designed architecture, the WTA layer was simulated with SIMON (Simulation of Nanostructures) [7], at circuit level, using as primary inputs the output current values resulting from the functional simulation of the pre-processing layer [10,11]. Macro simulations were executed successfully with SIMON for T = 1K and random offset charges (ROC) in the range −10%e < ROC < 10%e . Fig. 8 shows the analog output of each macro block, provided by the DAC converter for each disturbed character. MATLAB was used to read all DAC outputs and find the the block with the winner neuron according to Table 1. That table shows the corresponding DAC output voltages [12]. VII. CONCLUSIONS The macro block made possible the simulation of large-scale SET-WTA networks. In what concerns offset charges, the proposed macro block worked properly under significant ROC levels ( 10%e ). A character recognition task was successfully simulated. This study will be continued simulating more complex SET-WTA macro blocks as well as by the evaluation of the network's dynamic performance. Higher temperature operation will be considered. VIII. ACKNOWLEDGEMENTS J. G. Guimarães is grateful to CAPES-Brazil for support. L. M. Nóbrega is grateful to PIBIC-CNPq for support. The authors gratefully acknowledge PADCTBrazil for support. IX. REFERENCES Table 1 DAC output voltages b1 0 1 0 0 0 b2 0 0 1 0 0 b3 0 0 0 1 0 b4 0 0 0 0 1 DAC output 0 mV 0.6 mV 1.2 mV 2.4 mV 4.8 mV [1] [2] [3] [4] According to Fig. 8, when X 1 was presented to the system, macro block 1 provides an output of 0.6mV which indicates, as can be seen in Table 1, that neuron 1 of this block is the winner one. In this way, X 1 was [5] [6] recognized as P1 , as desired. When X 6 was presented, macro block 2 provided an output of 1.2mV indicating that neuron 2 of this macro is the winner. In Fig. 5 it can be seen that the second neuron of macro block 2 is neuron 6, showing that P6 was recognized. Also, X 11 [7] and X 16 were properly recognized, as can be noted in [9] Fig. 8. [8] [10] [11] [12] [13] Fig.8 DAC outputs “International Technology Roadmap for Semiconductors (ITRS)”, Semiconductor Industry Association, http://public.itrs.net, 2003. D. Esteve, Single Charge Tunneling - Coulomb blockade phenomena in nanostructures, H. Grabert and M. H. Devoret, Editors, NATO ASI series, Series B: Physics, USA: 1991. J. C. Costa, J. Hoekstra, M. J. Goossens, C. J. M. Verhoeven and H. M. V. Roermund, “Considerations about nanoelectronic GSI processors”, Analog Integrated Circuits and Signal Processing, vol. 24, no. 1, June, 2000, pages 59-71. J. Hoekstra, J. C. da Costa, M. J. Goossens, C. J. M. Verhoeven and A. H. M. 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