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XUQIANG ZHANG et al: A STUDY ON SUPER THRESHOLD FINFET CURRENT MODE LOGIC CIRCUITS
A Study on Super Threshold FinFET Current Mode Logic Circuits
Xuqiang ZHANG, Jianping HU*, Xia ZHANG
Faculty of Information Science and Technology, Ningbo University, Ningbo City, China
Abstract—The energy dissipation of a circuit is concerned problem for battery-operated mobile platforms. The super-threshold
computing scheme based on FinFET CML (Current Mode Logic) circuits is addressed in this paper to attain low power
dissipations. In near-threshold circuits, the power supply voltage is slightly above the threshold voltage of MOS devices, so that
their PDN transistors operate on medium inversion regions. In the super-threshold circuit, much larger supply voltage is used, so
that the larger biasing current can been used, and thus the super-threshold FinFET CML circuits can realize faster operation than
near-threshold one. The basic logic gates such as AND/NAND and XOR/XNOR, and 1-bit full-adder based on FinFET CML are
used to verify power efficiencies. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm BSIMCMG FinFET technology. The results show that the power consumption of FinFET CML circuits can be reduced by scaling the
supply voltage into super-threshold regions without performance degrading.
Keywords- Super-threshold computing, FinFET current mode logic, energy-efficient design
I.
INTRODUCTION
The MOS current mode logic (MCML) circuits have
better performance at operating speed compared with
conventional complementary CMOS logic circuits [1], since
smaller swing can be used. The power dissipation of the
MCML circuit with given voltage and biasing current is a
constant, which is independent of its operating frequency.
This means that the MCML circuits have large static power
dissipations because of constant currents [2].
With the increasing demand for battery-operating
electronic products that require low energy dissipations,
power-efficient designs have become more and more
important in IC chips [3-6]. Recently, the low power designs
of MCML have obtained attentions [7-9]. A low-power
design methodology for the MCML circuits can be carried
out by optimizing design parameters [7, 8]. Scaling supply
voltage is also a good method to obtain low power
consumption, since the power dissipation depends linearly on
supply voltage [8-12]. Anis and Elmasry presented that in
pull-down network (PDN), the multi-threshold NMOS
transistors can be used to minimize the power source voltage
to ensure PDN transistors operating at saturation region, and
thus reduce the power dissipations of the MCML circuits [9].
General, NMOS transistors in the PDN of the MCML
circuits operate on saturation regions, and thus the output
swing of the MCML circuits must be set as a smaller voltage
than the threshold voltage of NMOS transistors, resulting in
that a large power source voltage must be used in the MCML
circuits [10-14]. In this realization scheme, power dissipation
can not effectively reduced by lowering the source voltage of
the MCML circuits.
In near-threshold MCML circuits, the output swing is
usually selected as larger than the threshold voltage of
NMOS devices, and thus the NMOS transistors in the PDN
operate on linear regions, so that the lower power source
voltages can be used to reduce the power dissipations.
DOI 10.5013/IJSSST.a.17.48.29
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Moreover, near-threshold circuits use usually small biasing
current to minimum the power source voltage, resulting in a
large increasing delay.
In CMOS processes, SCE (short-channel effects) and
gate-dielectric leakage have caused the increasing leakage,
which has been a main barrier against further scaling [3].
Compared bulk CMOS devices, Fin-type Field-Effect
Transistors (FinFET) as a 3D device has lower leakage
current with better turn-on performance, which has been a
proper alternative for CMOS devices in further IC scaling
[15,16].
Compared with bulk MOS transistors, FinFET
transistors operating on super-threshold regions (medium
strong inversion regions) provide stronger turn-on current.
Therefore, it can be expected that FinFET CML circuits can
use a larger biasing current, and thus have more favorable
performance than MCML ones.
In this work, a super-threshold computing scheme for
FinFET Current Mode Logic (FinFET CML) circuits is
addressed. In near-threshold circuits, the power supply
voltage is slightly above the threshold voltage of MOS
devices, so that their PDN transistors operate on medium
inversion regions. In the super-threshold circuit, much larger
supply voltage is used, so that the larger biasing current can
been used, and thus the super-threshold FinFET CML
circuits can realize faster operation than near-threshold one.
The basic logic gates and 1-bit full-adder based on FinFET
CML are used to verify the power and delay efficiencies.
All circuits are simulated with HSPICE at a PTM
(Predictive Technology Model) 32nm BSIM-CMG FinFET
technology [17].
II.
FINFET CML CIRCUITS
The basic FinFET CML inverter/buffer and its biasing
circuit are shown in Fig. 1. The FinFET CML inverter is
composed of three main parts. The p-type FinFETs (P1 and
P2) operating at linear region act as load resistors. The full
ISSN: 1473-804x online, 1473-8031 print
XUQIANG ZHANG et al: A STUDY ON SUPER THRESHOLD FINFET CURRENT MODE LOGIC CIRCUITS
differential pull down network consisting of N-type
FinFETs (N1 and N2) is used for logic fuction. The N-type
transistor Ns provides the biasing current, which is mirrored
from the current source in the bias circuit.
In the FinFET CML, the two signals Vrfp is generated
from the bias circuit to ensure the proper operating for
output voltage swings, while and Vrfn provides the constant
bias current. This construction decide that VOH = VDD and
VOL = VDD - IBRD, where RD is the P-type transistor load
resistance. The logic swing ∆V = VOH - VOL = IB × RD .
Vrfp
VDD
OUTb
-
IN
OUT
OUTb
B
N3 N4
A
N2
VDD
Ab
N2
N1
(a) AND2/NAND2
VDD
OUT
N1
Bb N5
Ns
P2
P1
+
P2
P1
Vrfp
Vrfn
VDD
VDD
VDD
P2
P1
INb
Vrfp
OUTb
OUT
Ns
Vrfn
Bb
Bias Circuit
N3 N4
Ab
Figure 1. FinFET CML inverter/buffer and its biasing circuit.
The pull-down network in the general FinFET CML
circuits operates in saturated region. To achieve this goal,
the output swing must be controlled below threshold voltage.
With the scaling-down of technology dimension, the
threshold voltage of transistors is reduced. The typical
threshold voltage of transistors is between 0.2 and 0.3. In
order to make the pull-down network operate in saturated
region, the output swing must be smaller than this threshold
voltage, which may lead to bad performance on noise
margin. In order to solve this problem, FinFET transistors of
pull-down network in FinFET CML circuits operate in
linear region. In other words, its output swing is larger than
threshold voltage. All FinFET CML circuits mentioned in
this work are worked with an output swing of 0.3V.
FinFET CML is a type of differential logic with
differential input logic tree. Therefore, the design of the
FinFET CML PDN is similar to other differential logic
styles such as DCVSL and DSL. The complex logic
functions can be realized by replacing N1 and N2 with Ntype FinFET logic trees. When we design a FinFET CML
circuit, two parts can be divided. One part is Bias Circuit,
and the another part is logic circuit. The FinFET CML basic
gate cells such as AND2/NAND2, OR2/NOR2,
XOR2/XNOR2, and AND3/NAND3 are shown in Fig. 2.
The power consumption of FinFET CML circuits can be
expressed as
B
N1
Vrfn
N5
VDD
N2
A
Ns
(b) OR2/NOR2
VDD
Vrfp
OUTb
OUT
Bb
B
B
A
Ab
Vrfn
(b) XOR2/XNOR2
VDD
P2
P1
Vrfp
P  VDD  I
(1)
OUT
OUTb
C
Cb
VDD
B
Bb
VDD
Ab
A
where I is source current.
Vrfn
Ns
(d) AND3/NAND3
Figure 2. Basic gate cells based on FinFET CML.
DOI 10.5013/IJSSST.a.17.48.29
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XUQIANG ZHANG et al: A STUDY ON SUPER THRESHOLD FINFET CURRENT MODE LOGIC CIRCUITS
as
Easily, energy consumption per cycle can be expressed
From (5) and (6), the dynamic power consumption of a
static logic circuit increases linearly as its frequency.
VDD
E  PT  VDD  I  T 
VDD  I
f
(2)
Vrfp
Sb
where T is operation period and f is frequency.
As is shown in (2), a direct solution for reducing energy
consumption is to scale down supply voltage, since the total
energy is reduced linearly as supply voltage scales down.
Scaling supply voltage is an attractive approach. However,
scaling supply voltage to near-threshold region results in
that small biasing current must be used, so that the operating
speed of MCML circuits degrades.
Compared with bulk MOS transistors, FinFET
transistors operating on super-threshold regions (medium
strong inversion regions) provide stronger turn-on current.
Therefore, it can be expected that FinFET current mode
logic (FinFET CML) circuits can use a larger biasing
current, and thus have more favorable performance than
MCML ones. In the super-threshold circuit, much larger
supply voltage is used, so that the larger biasing current can
been used, and thus the super-threshold FinFET CML
circuits can realize faster operation than near-threshold one.
III.
S
Ci
Ci
Cib
B
Cib
Ci
Bb
Bb B
Vx
A
Ab
Vrfn
(a) sum
ONE-BIT FULL ADDER BASED ON FINFET CML
The logic functions of the 1-bit full adder can be
expressed as
Co  AB  BCi  ACi
(3)
S  ABCi  Co( A  B  Ci )
(4)
where A, B, Ci are input signal, Co is carry output, and S is
the sum of A, B, and Ci. According to (3) and (4), the 1-bit
adder can be realized by using FinFET CML, as shown in
Fig. 3, where Fig. 3(a) and Fig. 3(b) are the sum and carry
outputs, respectively.
In order to verify the performance of the FinFET CML
circuits, a criterion is needed. In this work, conventional
static logic was selected as a contrast, and its circuit is
shown in Fig. 4. The energy consumption should be
considered as a critical factor. The total power consumption
of static logic circuits can be expressed as
Ptot  Pdyn  Pdp  Pstat
VDD
A
B
A
B
Ci
B
A
Ci
B
A
S
Ci
(5)
VDD
Where Pdyn is dynamic power consumption, Pdp is the shortcircuit power consumption because of direct path from
source to Ground, and Pstat is static power consumption.
Generally, Pdyn take a large part of the total power
consumption, and it can be expressed as
2
(6)
Pdyn  C LVDD
f
where CL is load capacitance, VDD is source voltage, and f is
operational frequency.
DOI 10.5013/IJSSST.a.17.48.29
Figure 3. 1-bit full adder based on FinFET CML.
29.3
A
Ci
A
B
Co
A
B
B
Ci
B
A
Ci
Figure 4. 1-bit full adder based on static logic.
Fig. 5 shows the power consumption of the static full
adder in various frequencies with a standard source supply
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XUQIANG ZHANG et al: A STUDY ON SUPER THRESHOLD FINFET CURRENT MODE LOGIC CIRCUITS
The power dissipation comparisons of the 1-bit full adders
based on FinFET CML and static logic circuits are shown in
Fig. 7. The 1-bit FinFET CML full adder, whose pull-down
N-type transistors operate on linear region, gains an
advantage over static logic when working frequency is
larger than 800MHz. This verifies that FinFET CML
circuits have a great advantage in high-speed applications.
(1.2V). The simulation was carried out by HSPICE.
Power consumption
(uW)
150
50
0
0.1 0.3 0.5 0.7 0.9 1.2 1.6 1.8
Frequency (GHz)
2.0 3.0 4.0
Figure 5. Power consumption of the 1-bit full adder based on static logic
in various frequencies at a 1.2V standard source supply.
Power consumption (uW)
As it mentioned above, if the pull-down network of
FinFET CML operate in saturated region, it may result in
bad performance with the scaling-down of technology
dimension. Therefore, a scheme is needed to solve this
problem. We explored that whether the pull-down network
can work in linear region or not. The simulation results for
these basic FinFET CML cells and 1-bit full adder show that
all the pull-down N-type transistors of the FinFET CML
circuits can work in linear region with favorite performance.
All the FinFET CML circuits mentioned below are worked
with an output swing of 0.3V.
In order to investigate the performances of the FinFET
CML circuits, 1-bit full adder based on FinFET CML is
stimulated in various frequencies and 1.2V source voltage.
The power consumption of the 1-bit full adder is shown in
Fig. 6 in various frequencies. Moreover, the power
consumptions of the AND2, OR2, and XOR2 based on
FinFET CML circuits are all shown in Fig. 6.
Power consumption (uW)
100
Figure 7. The power dissipation comparisons of 1-bit full adder based on
FinFET CML and conventional static circuits at various frequencies and
1.3V source voltage.
IV.
SUPER-THRESHOLD COMPUTING
The power dissipation of the FinFET CML circuits can
be effectively reduced by scaling supply voltage, since the
power dissipation is reduced linearly as supply voltage
scales down. In order to get the most efficient point of the
super-threshold FinFET CML circuit, the minimum supply
voltage should be estimated.
The supply voltage of the FinFET CML circuits has a
minimum limit, at which the current source FinFET
transistor should operate at velocity saturation region, while
the N-type FinFET transistors in the pull-down network
(PDN) should be turn-on state.
Different from the conventional FinFET CML circuits,
the output swing of the proposed FinFET CML circuits
presented in this work is larger than the threshold voltage of
N-type FinFET transistors. And the N-type FinFET
transistors in the pull-down network of the FinFET CML
circuits operate on linear region, so that the source voltages
of the FinFET CML circuits can be well reduced. For a twolevel FinFET CML circuit, as shown in Fig. 8, to make sure
that the FinFET transistor N1 in the pull-down network
operates at linear state, the logic swing of the output of
FinFET CML circuits should be taken as
V  VTH
Figure 6. Power consumption of the 1-bit full adder based on FinFET
CML at various frequencies and 1.2V source voltage.
Form Fig. 6, we know that the power consumption of
FinFET CML circuits is nearly independent of frequency.
DOI 10.5013/IJSSST.a.17.48.29
29.4
(7)
where VTH is the threshold voltage of N-type FinFET
transistors. Therefore, according to Fig. 8, the minimum
operating power supply voltage of the FinFET CML circuits
can been expressed as
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XUQIANG ZHANG et al: A STUDY ON SUPER THRESHOLD FINFET CURRENT MODE LOGIC CIRCUITS
VDD , min  V1, ds  V2, ds  Vs , dsat
(8)
where V1,ds and V2,ds are gate-source voltages of the FinFET
transistors N1 and N2 when they operate in linear state,
respectively, and Vs,dsat is the drain-source voltage of the
FinFET transistor Ns when it operates at velocity saturation
point.
operation than near-threshold one. Fig. 9 shows the power
consumption of the 1-bit full adder with various supply
voltages at 500MHz.
60
50
40
P2
P1
30
N1
20
N2
10
Ns
0
0.4
0.5
0.6
0.7 0.8 0.9 1.0
Source voltage (V)
1.1
1.2
1.3
Figure 8. Minimum operating supply voltage of FinFET CML circuits,
where pull-down N-type transistors operates in linear region.
Figure 9. The power consumption of 1-bit full adder with various supply
voltages at 500MHz.
The simulations for the FinFET CML circuits have
shown that the typical value of V1,ds and V2,ds is about 20mV .
Therefore, the voltages V1,ds and V2,ds can be ignored. In
general, the drain-source saturation voltage Vs,sat in the
biasing current circuits is expressed as
From Fig. 9, scaling down the supply voltage can save
energy consumptions effectively. The power consumption
of the adder at 0.4V and 0.7V supply voltage is only 15.6%
and 50.1% of 1.3V supply voltage, respectively.
In order to give a visual contrast between standard
FinFET CML and near-threshold and super-threshold
FinFET CML, their power consumption with different
source voltages in various frequencies are also given, as
shown in Fig. 10. The power consumptions reduce
dramatically as the source voltage reduces, while the change
of frequency nearly has no influence on power dissipation.
Vds , sat 
I
2WCOX sat


4 E WLCOX sat
  1  sat
 1


I


(9)
where Esat, COX, and νsat are the saturation electric field,
oxide capacitance, and saturation velocity, respectively,
while W and L are the transistor effective width and length
of FinFET transistors, respectively.
According to (8) and (9), the minimum supply voltage
can be estimated. From (8) and (9), the minimum supply
voltage of the FinFET CML circuits can be reduced by
lowering its bias current. If the FinFET CML circuits
operate at a low-speed application, only a small biasing
current is required. Therefore, for low-speed applications, a
small bias current can be used, and thus the supply voltage
of the FinFET CML circuits can be reduced, so that more
power saving of the FinFET CML circuits can be obtained,
since the power dissipation of the FinFET CML circuits is
proportional to its supply voltage and bias current.
Compared with bulk MOS transistors, FinFET
transistors provide stronger turn-on current. Therefore, it
can be expected that FinFET current mode logic (FinFET
CML) circuits can use a larger biasing current, and thus
have more favorable performance than MCML ones. In the
super-threshold circuit, much larger supply voltage is used,
so that the larger biasing current can been used, and thus the
super-threshold FinFET CML circuits can realize faster
DOI 10.5013/IJSSST.a.17.48.29
29.5
Figure 10. The power consumption of the FinFET CML 1-bit full adder
with various operating frequency from 0.4V to 1.3V supply voltage.
V.
CONCLUSIONS
In this work, a super-threshold computing scheme for
ISSN: 1473-804x online, 1473-8031 print
XUQIANG ZHANG et al: A STUDY ON SUPER THRESHOLD FINFET CURRENT MODE LOGIC CIRCUITS
FinFET Current Mode Logic (FinFET CML) circuits has
been addressed to attain low power dissipations without
performance degrading.
General, NMOS transistors in the PDN of the MCML
circuits operate on saturation regions, and thus the output
swing of the MCML circuits must be set as a smaller
voltage than the threshold voltage of NMOS transistors,
resulting in that a large power source voltage must be used
in the MCML circuits. Compared with bulk MOS transistors,
FinFET transistors operating on super-threshold regions
(medium strong inversion regions) provide stronger turn-on
current. Therefore, FinFET CML circuits can use a larger
biasing current, and thus have more favorable performance
than MCML ones.
In near-threshold circuits, the power supply voltage is
slightly above the threshold voltage of MOS devices, so that
their PDN transistors operate on medium inversion regions.
In the super-threshold circuit, much larger supply voltage is
used, so that the larger biasing current can been used, and
thus the super-threshold FinFET CML circuits can realize
faster operation than near-threshold one. The basic logic
gates and 1-bit full-adder based on FinFET CML have been
used to verify the power efficiency in super-threshold and
near-threshold regions. The results show that the power
consumption of FinFET CML circuits can be reduced by
scaling the supply voltage into super-threshold regions
without performance degrading.
This work was supported by the Key Program of
National Natural Science of China (No. 61131001),
National Natural Science Foundation of China (No.
61671259 and No. 61271137).
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