Download Neural-Based Large-Signal Device Models Learning

Neural-Based Large-Signal Device Models Learning FirstOrder Derivative Parameters for Intermodulation
Distortion Prediction
F.Giannini, G.Leuzzi*, G.Orengo, P.Colantonio
*
Dipartimento di Ingegneria Elettronica - Università “Tor Vergata” - via Politecnico 1 - 00133
Roma - Italy – tel +390672597345 – fax 7343(53) - e_mail: [email protected]
Dipartimento di Ingegneria Elettrica – Università di L’Aquila – Monteluco di Roio – L’Aquila
- Italy – tel.++39 0862 434444 – e_mail: [email protected]
A detailed procedure to learn a nonlinear model together with its first-order derivative data is presented.
Two correlated multilayer perceptron (MLP) neural networks providing the model and its first-order
derivatives, respectively, are trained simultaneously. Applying this method to FET devices leads to
nonlinear models for current and charge fitting derivative parameters. The training data is the biasdependent equivalent circuit parameters extracted from S-parameter measurements. The resulting models
are suitable for both small-signal and large-signal analyses, in particular for intermodulation distortion
prediction. Examples for power amplifier simulations of power transfer, efficiency and intermodulation
distortion performances are presented.
INTRODUCTION
The standard approach for characterizing an
integrated microwave device and its enclosing
package requires the extraction of an equivalent
circuit which is fitted to electrical measurements.
Neural networks have been usefully applied to
model the bias dependence of S-parameters and
output current to perform small-signal and largesignal models, respectively (1). CAD software
systems generally implement separate small-signal
and large-signal models. However, this can lead to
inconsistent simulation results.
To overcome this problem, neural networks can be
used to learn a model using not only input/output
data but also derivative data. If two neural networks,
one providing the model to learn and an adjoint
network modelling its derivative parameters, have
correlated architectures, can learn both models
simultaneously (2,3). In this paper a practical
implementation providing modifications of the
backpropagation training algorithms is presented.
The proposed approach is applied to find largesignal models for drain current and charge in FET
devices without loss of generality. An experiment
based on a 0.5x1000µm medium power GaAs
MESFET is presented. The process is implemented
by the AMS foundry (Alenia-Marconi Systems).
The training data is the bias-dependent equivalent
circuit parameters extracted from S-parameter
measurements. Notice that learning the equivalent
circuit parameters means learning the derivative
information of the large-signal model. The capability
of training an active device model, using the first-
order derivative information, is very useful in
simultaneous small-signal/large-signal device
simulation, and allows intermodulation distortion
prediction.
NEURAL NETWORK APPROACH
Consider the MLP neural network shown in Figure
1, modelling the Ids current of an FET device as a
function of the bias voltages Vgs and Vds. First-order
derivative parameters Gm and Gds can be modeled by
an adjoint neural network shown in Figure 2. The
same number of layer 1 neurons in both networks
must be chosen to obtain the required accuracy. F is
the nonlinear transfer function.
The two networks have correlated weights and
topologies. In order the two networks to be trained
simultaneously, a global network has to be built. On
account of weight and bias correlations, constraints
on derivative calculation must be imposed in the
backpropagation algorithm used to train the network.
c1
b1
Vgs
c2
u11
u12
F
v1
bN
uN1
Vds
F
Ids (Vgs,Vds)
Σ
vN
d
uN2
layer 1
layer 2
Figure 1: A two layer neural network modelling the Ids
current.
cc1
b1
Vgs
u11
w11
Σ
F'
uN1
Gm(Vgs,Vds)
w1N
bN
u12
Vds
w21
F'
w2N
uN2
layer 1
cc2
Gds(Vgs,Vds)
Σ
and zero-crossing constraints to the I-V
characteristics. DC current data, on the other hand,
have a wrong RF behavior, especially for the output
conductance. The result, which is plotted in Figure
4, is that the Ids model will be completely defined for
any input voltage, whereas traditional Ids models
need conditional statements to separate different
voltages domains. This fact speed up nonlinear
simulations involving different bias regions.
layer 2
Figure 2: An adjoint neural network modelling Ids firstorder derivative parameters.
The global network can be trained alternatively with
the only input/output data of the function to learn,
with only its derivative data, or finally, with both of
them. In every case the network will provide both
the function and its derivative models as well.
FET LARGE-SIGNAL MODEL
The proposed technique has been applied to find a
large-signal model of a FET device. In particular a
0.5x1000µm medium power GaAs MESFET
implemented by the AMS foundry (Alenia-Marconi
Systems) has been considered.
(a)
The bias-dependent intrinsic parameters, from the
extracted small-signal equivalent circuit shown in
Figure 3a (4), provide nonlinar current and charge
partial derivatives, corresponding to the nonlinear
equivalent circuit shown in Figure 3b
G m = dI ds dVgs
G ds = dI ds dVds
C11 = dQ g dVgs
C12 = dQ g dVds
C 21 = dQ d dVgs
C 22 = dQ d dVds
where derivative capacitances are defined from
intrinsic capacitances as (5,6)
C11 = C gs − C gd
C12 = C 21 = −C gd
and
C 22 = C ds − C gd
The nonlinear relationship of Ids, Qg and Qd with
respect of large-signal voltages Vgs and Vds are each
evaluated by mean of a couple of neural networks as
that shown in Figure 1 and Figure 2. The nonlinear
transfer function chosen for the two sub-networks
are the hyperbolic tangent and its first-order
derivative, respectively.
The Ids model is extracted training the first-order
derivative sub-network with the extracted
parameters Gm and Gds. Input/output training data for
the Ids sub-network are taken from DC
measurements, especially to impose deep pinchoff
(b)
Figure 3: MESFET (a) linear and (b) nonlinear equivalent
circuit
On the other hand, to train charge models from Cij
parameters, only derivative data is available, that is
only the derivative sub-network is trained, whereas
the Qg and Qd sub-networks provide the desired
charge models. After training, a good agreement of
equivalent circuit parameters between the neural
models and experimental data is observed at all the
100 bias points, as it can be seen in Figg.5-6.
Neural models for gate-source current Igs and gatedrain breakdown current Igd have been also trained
on DC current measurements.
EXPERIMENTAL RESULTS
The five neural models have been easily
implemented into a user-defined nonlinear device
model of the Agilent ADS microwave circuit
simulator to predict the performance at 5 GHz of the
power amplifier shown in the circuit schematic of
Figure 7. The results for power gain and power
transfer are shown in Figure 8 and 9 respectively,
whereas a prediction of power efficiency is shown in
Figure 10. Acceptable approximation of third-order
intermodulation (IMD3) behavior with two tones at
5 GHz and 5.05 GHz has been also obtained and
results are plotted in Figure 11.
A detailed procedure to learn nonlinear models
using also derivative information has been
presented. When applied to large-signal parameter
extraction of nonlinear devices, using only firstorder derivative information, this approach has led
to models that have the same complexity of
traditional formula-based models but are more
consistent and reliable, both for small-signal and
large-signal behavior prediction. The simulation of a
power amplifier circuit with the neural FET models
approaches the accuracy of the measured data.
300
250
200
Ids [mA]
CONCLUSIONS
350
150
100
50
0
-50
0
2
4
6
8
10
Vds [V]
Figure 4: Ids neural model curves (continuous) and
DC measured curves (dashed).
200
REFERENCES
(4)
(5)
(6)
V.Rizzoli, A.Costanzo, A Fully
Conservative Nonlinear Empirical Model of the
Microwave FET, Proc. of 24th Europ. Microwave
Conf., vol. 2, pp. 1307-1312, 1994.
R.R.Daniels, A.T.Yang, and
J.P.Harrang, A Universal Large/Small Signal 3Terminal FET Model Using a Nonquasi-Static
Charge Based Approach, IEEE Trans. Electron
Devices, 40 (10), 1993, 1723-1729.
0
1
2
3
0
1
2
3
4
5
6
7
8
9
4
5
6
7
8
9
Gm [mS]
Gd [mS]
0.15
J.Xu, M.C.E.Yagoub, R.Ding, and Q-J
Zhang, “Exact Adjoint Sensitivity Analysis for
Neural Based Microwave Modeling and Design,”
IEEE MTT-S Digest, sec. WE3E-3, pp.1015-1018,
2001.
G.Leuzzi, A.Serino, F.Giannini,
S.Ciorciolini, Novel non-linear equivalent-circuit
extraction scheme for microwave field-effect
transistors, Proc. 25th European Microwave Conf.,
Bologna (Italy), 1995, 548-552.
50
-50
0.1
0.05
0
Vds [V]
Figure 5: Ids first-order derivative model fitting.
2000
Cgs [fF]
(3)
K. Hornik, M. Stinchcombe, and H.
White, “Universal Approximation of an Unknown
Mapping and Its Derivatives using Multilayered
Feedforward Networks, Neural Networks”, vol.3
no. 5, pp. 551-560, May 1990.
100
0
1500
1000
500
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
400
Cgd [fF]
(2)
F.Giannini, G.Leuzzi, G.Orengo,
M.Albertini, “Small-Signal and Large-Signal
Modeling of Active Devices Using CADoptimized Neural Networks,” International Journal
of RF and Microwave Computer-Aided
Engineering, Special Issue on Neural Networks,
Volume 12, Issue 1, Pages 71-78, January 2002.
200
0
400
Ci [fF]
(1)
150
200
0
Vds [V]
Figure 6: Charge derivative model fitting
C
C2
C=100 pF
C
C1
C=100 pF
V_DC
SRC1
Vdc=VGG
W IRE
W ire1
D=18 um
L=300 um
Rho=1
W IRE
W ire2
D=18 um
L=300 um
Rho=1
W IRE
W ire3
D=18 um
L=300 um
Rho=1
DC_Feed
DC_Feed1
3
1
I_Probe
Iin
P_1Tone
PORT1
Num=1
Z=50 O hm
P=polar(dbmtow(Pin),0)
Freq=5 GHz
DC_Block
DC_Block1
Neural
FET
↓
W IRE
W ire7
D=18 um
L=300 um
Rho=1
W IRE
W ire4
D=18 um
L=300 um
Rho=1
In_TL
X1
2
W IRE
W ire8
D=18 um
L=300 um
Rho=1
S
P11neur
X3
W IRE
W ire9
D=18 um
L=300 um
Rho=1
DC_Feed
DC_Feed2
3
D
G
2
W IRE
W ire10
D=18 um
L=300 um
Rho=1
V_DC
SRC2
Vdc=VDD
1
O ut_TL
X2
DC_Block
DC_Block2
I_Probe
Iout
Term
Term2
Num=2
Z=50 O hm
W IRE
W ire6
D=18 um
L=300 um
Rho=1
W IRE
W ire5
D=18 um
L=300 um
Rho=1
Figure 7: Agilent ADS power amplifier simulation circuit.
12
30
11
25
10
20
Pout [dBm]
Gain [dB]
9
8
7
15
10
6
5
5
0
4
3
-10
-5
0
5
10
15
20
-5
-10
25
-5
0
5
Pin [dBm]
Figure 8: Power amplifier
measurements.
gain
10
15
20
25
Pin [dBm]
simulation
and
Figure 9: Amplifier power transfer simulation and
measurements.
-5
60
-10
50
-15
-20
IMD3 [dB]
Eta
40
30
20
-25
-30
-35
-40
-45
10
-50
0
-10
-5
0
5
10
15
20
Pin [dBm]
Figure 10: Amplifier power efficiency simulation and
measurements.
25
-55
0
5
10
Pin [dBm]
Figure 11: IMD3 simulation and measurements.
15