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Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
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LECTURE 280 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP
AMPS
LECTURE ORGANIZATION
Outline
• Introduction
• Examples of differential output op amps
• Common mode output voltage stabilization
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 384-393
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-2
INTRODUCTION
Why Differential Output Op Amps?
• Cancellation of common mode signals including clock feedthrough
• Increased signal swing
v1
v1-v2
A
t
-A
A
t
-A
v2
2A
t
-2A
Fig. 7.3-1
• Cancellation of even-order harmonics
Symbol:
-
-
vin
+
+
+
-
+
vout
Fig. 7.3-1A
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-3
Common Mode Output Voltage Stabilization
If the common mode gain not small, it may cause the common mode output voltage to
be poorly defined.
Illustration:
vod
VDD
vod
VDD
vod
VDD
0
0
t
0
t
VSS
VSS
CM output voltage properly defined,
Vcm = 0
t
VSS
CM output voltage too small,
V = 0.5VSS
070506-01
CM output voltage too large,
Vcm= 0.5VDD
cm
Remember that:
vOUT = Avd(vID) ± Acm(vCM)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-4
EXAMPLES OF DIFFERENTIAL OUTPUT OP AMPS (OTA’S)
Two-Stage, Miller, Differential-In, Differential-Out Op Amp
Note that the
upper ICMR is
V DD - VSGP
VDD
+
VBP
-
M8
+ VTN
Cc
vo1
M3
Rz
vi1
M9
M1
+
-
Fig. 7.3-4
CMOS Analog Circuit Design
+
vod
-
CL
+
+
vid
- -
M2
M5
+
VBN
-
(OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat)
The maximum peak-to-peak output voltage
2·OCMR
Conversion between differential outputs and single-ended outputs:
+
+
vid
- -
+
-
+
vo2
-
M6
M4
+
vo1
-
VSS
Rz
Cc
vo
vi2
M7
Fig. 7.3-3
2CL
2CL
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-5
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output
VDD
+
VBP
-
M3
M4
M13
M7
vo1
Cc
M6
M14
Rz
vi1
M9
M1
+
VBN
-
M10
Rz Cc
vo2
vi2
M2
M5
M8
M12
VSS
Fig. 7.3-6
Comments:
• Able to actively source and sink output current
• Output quiescent current poorly defined
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-6
Folded-Cascode, Differential Output Op Amp
VDD
VPB1
I4
I5
M4
I1
+
vIN
−
M1 M2
VPB2
I3
I7
M7
− vOUT +
VNB2
CL
VNB1
M10
CL
M9
M8
M3
VNB1
I6
M6
I2
M5
M11
060717-01
• No longer has the low-frequency asymmetry in signal path gains.
• Class A
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-7
Enhanced-Gain, Folded-Cascode, Differential Output Op Amp
VDD
VPB1
M10
VPB1
+
vIN
−
M3
M11
What about the A amplifier?
Below is the upper A amplifier:
VDD
+A −
− +
M8
M1 M2
M9
− vOUT +
M6
M7
− +
+ A−
VPB2M9 vin+
voutVNB1
M11
M8
M10
VPB2
vin-
M3
M2
M1
vout+
M4
VBias
M5
M12
M6
060718-02
M4
VNB1
VPB1
M7
M5
060718-01
Note that VBias controls the dc voltage at the
input of the A amplifier through the negative
feedback loop.
• Balanced inputs
• Class A
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-8
Push-Pull Cascode Op Amp with Differential-Outputs
VDD
M7
M3 M4
M5
M8
M6
M20
M21
M9
M10
R2
vo1
vi1
M1 M2
M22
M15
M23
vi2
M19
M16
M17
VBias
vo2
R1
M18
M12
M13
M11
M14
VSS
Fig. 7.3-8
• Output quiescent currents are well defined
• Self-biased circuits can be replaced with VNB2 and VPB2
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-9
Folded-Cascode, Push-Pull, Differential Output Op Amp
VDD
VPB1
VPB1
I14
I15
0.5gm2vin
M14 M15
I16
VPB2
M16
I1 I2
I17
M17
+
vIN M1 M2
−
I3
M5
VNB1
I6
I7
M6
I4 0.5g v I8
m4 in
M8
M3 M4
CL
I5
M7
VPB2
0.5gm2vin
− vOUT +
CL
0.5gm3vin
0.5gm1vin
VNB2
0.5gm3vin
I9
M9
0.5gm4vin
VNB2
0.5gm1vin
M10
M11
M12
M13
M18
M19
M20
M21
060717-02
I6 = I7 = I14 = I15 > 0.5I5
I5 = I1 + I2 + I3 + I4
Av = gmRout(diff)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-10
Enhanced-Gain, Folded-Cascode with Push-Pull Outputs
VDD
VPB1
VPB1
M10 M11
VPB2
M12
M6
M13
+
vIN M1 M2
−
M7
+A −
− +
M3 M4
M9
M8
M5
− vOUT +
CL
VNB1
VNB2
M15
M14
M16
M17
− +
+A −
CL
M18
M19
M20
VNB2
M21
060718-06
• Gain approaches gm3rds3
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-11
Cross-Coupled Differential Amplifier Stage
The cross-coupled input stage allows the push-pull output quiescent current to be well
defined.
i2
i1
VGS1
vi1
VSG3
+ M1 M2 +
vGS2
vGS1
+
+
vSG3
vSG4
M3 M4
i2
i1
VGS2
vi2
VSG4
Fig. 7.3-9
Operation:
Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2
Using the notation for ac, dc, and total variables gives,
vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2)
If gm1 = gm2 = gm3 = gm4, then half of the differential input is applied across each
transistor with the correct polarity.
gm1vid gm4vid
gm2vid
gm3vid
i1 = 2 = 2
and
i2 = - 2 = - 2
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-12
Class AB, Differential Output Op Amp using a Cross-Coupled Differential Input
Stage
VDD
M10
M7 M8
M9
M25
M26
M13
vi1
M22
M19
M15
R1
M14
vo2
M20
M3 M4
R2
M16
M27
M11
M1 M2
M21
vo1
M24
vi2
M17
M18
M28 +
VBias
-
M5
M6
VSS
M23
M12
Fig. 7.3-10
Quiescent output currents are defined by the current in the input cross-coupled
differential amplifier.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-13
COMMON MODE OUTPUT VOLTAGE STABILIZATION
Common Mode Feedback Circuits
Because the common mode gain is undefined, any common mode signal at the input
can cause the output common mode voltage to be improperly defined. The common
mode output voltage is stabilized by sensing the common mode output voltage and using
negative feedback to adjust the common mode voltage to the desired value.
Model for the Output of Differential Output Op Amps:
VDD
io1(source)
VDD
Ro1
Ro2
io2(source)
vo2
Ro3
Ro4
Io2(sink)
vo1
Io1(sink)
io1(source)
vo1
Ro1
Ro2
io2(source)
vo2
io1(sink)
Ro3
Ro4
io2(sink)
Push-Pull Output
Class A Output
060718-08
Roi represents the self-resistance of the output sink/sources.
1.) If the common mode output voltage increases the sourcing current is too large.
2.) If the common mode output voltage decreases the sinking current is too large.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-14
Conceptual View of Common-Mode Feedback
VDD
vo2
vo1
Output
Stage
Model
Common Mode
Sensing Circuit
+
−
VCMREF
060718-09
Function of the common-mode feedback circuit:
1.) If the common-mode output voltage increases, decrease the upper currents sources or
increase the lower current sink until the common-mode voltage is equal to VCMREF.
2.) If the common-mode output voltage decreases, increase the upper currents sources or
decrease the lower current sink until the common-mode voltage is equal to VCMREF.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-15
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-Mode
Feedback
VDD
+
VBP
M10
-
M7
Cc
vo1
Rz
vi1
M9
M11
M6
M3
M4
M1
Rz
vo2
vi2
M2
M5
+
VBN
-
Cc
M8
VSS
Fig. 7.3-12
Comments:
• Simple
• Unreferenced – value of common mode output voltage determined by the circuit
characteristics
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-16
Common Mode Feedback Circuits
Implementation of common mode feedback circuit:
VDD
M3
M4
IBias MC3
vo1 I3
I4 vo2
MC4
Common- I
C3
IC4
Ro1 Ro2
mode feedback circuit
MC1 MC2A
vi2
vi1
VCM
M1
M2
MC2B
MC5
MB
M5
060718-10
This scheme can be applied to any differential output amplifier.
CM Loop Gain = -gmC1Ro1 which can be large if the output of the differential output
amplifier is cascaded or a gain-enhanced cascode.
The common-mode loop gain may need to be compensated for proper dynamic
performance.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-17
Common Mode Feedback Circuits – Continued
The previous circuit suffers when the input common mode voltage is low because the
transistors MC2A and MC2B have a poor negative input common mode voltage.
The following circuit alleviates this disadvantage:
VDD
M3
M4
IBias MC3
Commonmode feedback circuit
MC1
vi1
VCM
vo2
RCM2
RCM1
MC2
I4
I3
vo1
MC4
IC4
IC3
M1
M2
vi2
M5
MC5
MB
060718-11
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-18
An Improved Common-Mode Feedback Circuit
The resistance loading of the previous circuit can be avoided in the following CM
feedback implementation:
VDD
M5
M6
CM Correction Circuitry
vo1 M1
M2
RCM
M4 vo2
M3
VCMREF
RCM
060718-12
This circuit is capable of sustaining a large differential voltage without loading the output
of the differential output op amp.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-19
Frequency Response of the CM Feedback Circuit
Consider the following CM feedback circuit implementation:
VDD
VPB1
M12
M4
M5
VPB2
M6
−
M1 M2
+
vIN
−
M7
vOUT
+
M13 M14
VNB2
M3
Cc
M8
VNB1
VCMREF
C
M9 c
M11
M16
M15
M10
070506-02
The CM feedback path has two poles – one at the gates of M10 and M11 and the
dominant output pole of the differential output op amp.
Can compensate with Miller capacitors as shown.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-20
Improved CM Feedback Frequency Response
The circuit on the previous page can be modified to eliminate the pole at the gates of
M10 and M11 as follows:
VDD
VPB1
M12
M4
M5
VPB2
M7
M6
+
vin
−
M1 M2
vo1
M8
M3
VNB1
M13 M14
vo2
VCMREF
VNB2
M9
VNB1
M10
M19
VNB2
M18
M15
M11
M17
M16
060718-14
• The need for compensation of the common mode loop no longer exists since there is
only one dominant pole
• The dominant pole of the differential amplifier becomes the dominant pole of the
common mode feedback
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-21
A Common Mode Feedback Correction Scheme for Discrete Time Applications
Correction Scheme:
φ1
φ1
φ2
+
+
vid
- -
vo1
+
-
CMbias
vo2
Ccm
φ1
Ccm
φ1
φ2
φ1
Vocm
Fig. 7.3-14
Operation:
1.) During the 1 phase, both Ccm are charged to the desired value of Vocm and CMbias
= Vocm.
2.) During the 2 phase, the Ccm capacitors are connected between the differential
outputs and the CMbias node. The average value applied to the CMbias node will be
V ocm.
CMOS Analog Circuit Design
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
© P.E. Allen - 2010
Page 280-22
Example of a Common-Mode Output Voltage Stabilization Scheme for DiscreteTime Applications
Common mode
VDD
adjustment phase:
VPB1
M15
Switches S1, S2 and S3
Discrete time common
are closed. C1 and C2
M4
M5
mode correction circuit
VPB2
are charged to the value
S4
S1
M6
M7
necessary for I12 and I13
S2
C1
to keep the common
− vOUT +
M1
M2
mode output voltage at
+
C2
vIN
V CM.
−
S5
S3
VNB2
M3
Amplification phase:
M9
M8
VNB1
VCM
I12
Switches S4 and S5 are
I13
closed. If the common
M12 M13
VNB1
M14
mode output voltage is
M11
M10
not at VCM, the currents
070506-03
I12 and I13 will change
to force the value of the common mode output voltage back to VCM.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
Page 280-23
Correction of Channel Charge and Clock Feedthrough
In the discrete-time common mode correction schemes, the switches can introduce
error due to channel charge and clock feedthrough.
Through simulation, these errors can be predicted and corrected by applying a
correction signal superimposed upon the error signal to achieve the desired (target)
common mode voltage.
General principle:
Differential
Outputs
Unwanted Charge
Injection Error
Correction
CMFB
Signal
Amplifier
Error
Signal
CMFB
Sense
VBias
ΔV
Vcm
(Target voltage)
CMOS Analog Circuit Design
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10)
•
•
•
•
•
© P.E. Allen - 2010
Page 280-24
SUMMARY
Advantages of differential output op amps:
- 6 dB increase in signal amplitude
- Cancellation of even harmonics
- Cancellation of common mode signals including clock feedthrough
Disadvantages of differential output op amps:
- Need for common mode output voltage stabilization
- Compensation of common mode feedback loop
- Difficult to interface with single-ended circuits
Most differential output op amps are truly balanced
For push-pull outputs, the quiescent current should be well defined
Common mode feedback schemes include,
- Continuous time
- Discrete time
CMOS Analog Circuit Design
© P.E. Allen - 2010