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EC6601- VLSI DESIGN UNIT I-MOS TRANSISTOR PRINCIPLE OUTLINE • NMOS and PMOS transistors • Process parameters for MOS and CMOS • Electrical properties of CMOS circuits and device modeling • Scaling principles and fundamental limits CMOS inverter scaling • Propagation delays • Stick diagram, Layout diagrams. Introduction • Integrated circuits: many transistors on one chip. • Very Large Scale Integration (VLSI): very many • Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors • Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication A Brief History • 1958: First integrated circuit – Flip-flop using two transistors – Built by Jack Kilby at Texas Instruments • 2003 – Intel Pentium 4 mprocessor (55 million transistors) – 512 Mbit DRAM (> 0.5 billion transistors) • 53% compound annual growth rate over 45 years – No other technology has grown so fast so long • Driven by miniaturization of transistors – Smaller is cheaper, faster, lower in power! – Revolutionary effects on society A Brief History • 1958: First integrated circuit – Flip-flop using two transistors – Built by Jack Kilby at Texas Instruments • 2003 – Intel Pentium 4 mprocessor (55 million transistors) – 512 Mbit DRAM (> 0.5 billion transistors) • 53% compound annual growth rate over 45 years – No other technology has grown so fast so long • Driven by miniaturization of transistors – Smaller is cheaper, faster, lower in power! – Revolutionary effects on society Invention of the Transistor • Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable • 1947: first point contact transistor – John Bardeen and Walter Brattain at Bell Labs – Read Crystal Fire by Riordan, Hoddeson Transistor Types • Bipolar transistors – npn or pnp silicon structure – Small current into very thin base layer controls large currents between emitter and collector – Base currents limit integration density • Metal Oxide Semiconductor Field Effect Transistors – nMOS and pMOS MOSFETS – Voltage applied to insulated gate controls current between source and drain – Low power allows very high integration MOS Integrated Circuits • 1970’s processes usually had only nMOS transistors – Inexpensive, but consume power while idle 1101 256-bit SRAM Intel 4004 4-bit mProc • Intel 1980s-present: CMOS processes for low idle power Moore’s Law • 1965: Gordon Moore plotted transistor on each chip – Fit straight line on semilog scale – Transistor counts have doubled every 26 months 1,000,000,000 Integration Levels 100,000,000 10,000,000 Transistors Intel486 1,000,000 Pentium 4 Pentium III Pentium II Pentium Pro Pentium SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates Intel386 80286 100,000 8086 10,000 8080 8008 4004 1,000 1970 1975 1980 1985 Year 1990 1995 2000 Corollaries • Many other factors grow exponentially – Ex: clock frequency, processor performance 10,000 4004 1,000 8008 Clock Speed (MHz) 8080 8086 100 80286 Intel386 Intel486 10 Pentium Pentium Pro/II/III Pentium 4 1 1970 1975 1980 1985 1990 Year 1995 2000 2005 MOS Transistor Basics Four Terminal Structure p-Substrate The MOS n-channel transistor structure: G(ate) S(ource) n+ L p B(ody, Bulk or Substrate) D(rain) n+ MOS Transistor Basics Four Terminal Structure (Continued) Symbols: n-channel - p-substrate; p-channel – n-substrate D D B G S G D G S D G S S G S D N-channel (for P-channel, reverse arrow or add bubbles) P-channel Enhancement mode: no conducting channel exists at VGS = 0 Depletion mode: a conducting channel exists at VGS = 0 MOS Transistor Basics Four Terminal Structure (Continued) • Source and drain identification D VDS B G VSB VGS S nMOS Cutoff • No channel • Ids = 0 Vgs = 0 + - g + - s d n+ n+ p-type body b Vgd MOSFET Modes of Operation Cutoff • Assume n-channel MOSFET and VSB=0 Cutoff Mode: 0≤VGS<VT0 – The channel region is depleted and no current can flow gate source drain IDS=0 VGS < VT0 nMOS Linear • Channel forms • Current flows from d to s Vgs > Vt – e- from s to d • Ids increases with Vds • Similar to linear resistor + - g + - s d n+ n+ Vgd = Vgs Vds = 0 p-type body b Vgs > Vt + - g s + d n+ n+ p-type body b Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt MOSFET Modes of Operation Linear Linear (Active, Triode) Mode: VGS≥VT0, 0≤VDS≤VD(SAT) – Inversion has occurred; a channel has formed – For VDS>0, a current proportional to VDS flows from source to drain – Behaves like a voltage-controlled resistance gate source current drain IDS VDS < VGS – VT0 nMOS Saturation • • • • Channel pinches off Ids independent of Vds We say current saturates Similar to current source Vgs > Vt + - g + - Vgd < Vt d Ids s n+ n+ p-type body b Vds > Vgs-Vt MOSFET Modes of Operation Pinch-Off Pinch-Off Point (Edge of Saturation) : VGS≥VT0, VDS=VD(SAT) – Channel just reaches the drain – Channel is reduced to zero inversion charge at the drain – Drifting of electrons through the depletion region between the channel and drain has begun gate source current drain IDS VDS = VGS – VT0 MOSFET Modes of Operation Saturation Saturation Mode: VGS≥VT0, VDS≥VD(SAT) – Channel ends before reaching the drain – Electrons drift, usually reaching the drift velocity limit, across the depletion region to the drain – Drift due to high E-field produced by the potential VDS-Vgate D(SAT) between the drain and the end of the channel source drain VDS > VGS – VT0 IDS PMOS ENHANCEMENT MOSFET I-V Characteristics • In Linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving? Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel gate Vg polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Qchannel = CV Cox = ox / tox • C = Cg = oxWL/tox = CoxWL • V = Vgc – Vt = (Vgs – Vds/2) – Vt gate Vg polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body Carrier velocity • Charge is carried by e• Carrier velocity v proportional to lateral E-field between source and drain • v= Carrier velocity • Charge is carried by e• Carrier velocity v proportional to lateral E-field between source and drain • v = mE m called mobility • E= Carrier velocity • Charge is carried by e• Carrier velocity v proportional to lateral E-field between source and drain • v = mE m called mobility • E = Vds/L • Time for carrier to cross channel: –t= Carrier velocity • Charge is carried by e• Carrier velocity v proportional to lateral E-field between source and drain • v = mE m called mobility • E = Vds/L • Time for carrier to cross channel: –t=L/v nMOS Linear I-V • Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Qchannel I ds t W mCox L Cox= oxide capacitance W = mCox L V V Vds V gs t 2 ds V Vgs Vt ds Vds = β (Vgs-Vt )Vds -Vds2/2 2 = β (Vgs-Vt )Vds It is a region called linear region. Here Ids varies linearly, with Vgs and Vds when the quadratic term Vds2/2 is very small. Vds << Vgs-Vt nMOS Saturation I-V • If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt • Now drain voltage no longer increases current Qchannel I ds t W mCox L V V Vds V gs t 2 ds V Vgs Vt ds Vds = β (Vgs-Vt )Vds -Vds2/2 2 Where 0 < Vgs – Vt <Vds, considering (Vgs-Vt )=Vds we have Ids = β (Vgs-Vt ) 2/2 nMOS I-V Summary • nMOS Characteristics Variations in I-V Characteristics •The velocity of the carriers is proportional to the electric field up to a point. •When electric field reaches a critical value, Esat, the velocity saturates. •When the channel length decreases, only a small VDS is needed for saturation •Causes a linear dependence of the saturation current wrt the gate voltage (in contrast to squared dependence of long- channel device) •Current drive cannot be increased by decreasing L Velocity Saturation Effects 10 For short channel devices and large enough VGS – VT VDSAT < VGS – VT so the device enters saturation before VDS reaches VGS – VT and operates more often in saturation 0 IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage Velocity Saturation 1.5 0.5 VGS = 3 0.5 VGS = 2 VGS = 1 0.0 1.0 2.0 VDS 3.0 (V) 4.0 (a) I D as a function of VDS 5.0 ID (mA) VGS = 4 I D (mA) 1.0 Linea r Dependence VGS = 5 0 0.0 1.0 2.0 VGS (V) (b) ID as a function of VGS (for VDS = 5 V). Linear Dependence on VGS 3.0 Short Channel I-V Plot (NMOS) NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V 2.5 X 10-4 Early Velocity Saturation 2 VGS = 2.5V VGS = 2.0V 1.5 Linear 1 Saturation 0.5 VGS = 1.5V VGS = 1.0V 0 0 0.5 1 1.5 VDS (V) 2 2.5 Channel Length Modulation • Reverse-biased p-n junctions form a depletion region – Region between n and p with no carriers – Width of depletion Ld region grows with reverse bias V V GND Source Gate Drain – Leff = L – Ld Depletion Region Width: L • Shorter Leff gives more current – Ids increases with Vds L n+ n+ L – Even in saturation p bulk Si DD DD d eff GND Chan Length Mod I-V I ds Ids (mA) V 2 gs Vt 1 lVds 2 400 Vgs = 1.8 300 Vgs = 1.5 200 Vgs = 1.2 100 0 0 Vgs = 0.9 Vgs = 0.6 0.3 0.6 0.9 1.2 • l = channel length modulation coefficient – not feature size – Empirically fit to I-V characteristics 1.5 1.8 Vds Body Effect • Vt: gate voltage necessary to invert channel • Increases if source voltage increases because source is connected to the channel • Increase in Vt with Vs is called the body effect Vt Vt 0 Body Effect Model g f V f s sb s • fs = surface potential at threshold fs 2vT ln NA ni – Depends on doping level NA – And intrinsic carrier concentration ni • g = body effect coefficient g tox ox 2q si N A 2q si N A Cox OFF Transistor Behavior • What about current in cutoff? I • Simulated results 1 mA Sub100 mA threshold 10 mA • What differs? Region ds – Current doesn’t go to 0 in cutoff Saturation Region Vds = 1.8 1 mA 100 nA 10 nA Subthreshold Slope 1 nA 100 pA 10 pA Vt 0 0.3 0.6 0.9 Vgs 1.2 1.5 1.8 Leakage Sources • Subthreshold conduction – Transistors can’t abruptly turn ON or OFF • Junction leakage – Reverse-biased PN junction diode current • Gate leakage – Tunneling through ultrathin gate dielectric • Subthreshold leakage is the biggest source of DC power dissipation in modern transistors D D S S Gate Leakage • Carriers tunnel thorough very thin gate oxides • Exponentially sensitive to tox and VDD D IG S – A and B are tech constants – Greater for electrons • So nMOS gates leak more • Negligible for older processes (tox > 20 Å) • Critically important at 65 nm and below (tox ≈ 10 Å=1nm) From [Song01] Sub-Threshold Conduction -2 The Slope Factor 10 Linear -4 I D ~ I 0e 10 -6 10 Quadratic Slope S 10 -10 Exponential -12 VT 10 10 , n 1 0 0.5 1 1.5 VGS (V) CD Cox S is DVGS for ID2/ID1 =10 ID (A) -8 qVGS nkT 2 2.5 Typical values for S: 60 .. 100 mV/decade Sub-Threshold ID vs VGS D ID VG + - VS I D I 0e qVGS nkT qV DS 1 e kT VDS from 0 to 0.5V VGS Sub-Threshold ID vs VDS VD VG ID I D I 0e qVGS nkT VS VGS from 0 to 0.3V qV DS 1 e kT 1 l VDS ID versus VGS -4 6 x 10 -4 x 10 2.5 5 2 4 linear quadratic ID (A) ID (A) 1.5 3 1 2 0.5 1 quadratic 0 0 0.5 1 1.5 VGS(V) Long Channel 2 2.5 0 0 0.5 1 1.5 VGS(V) Short Channel 2 2.5 ID versus VDS -4 6 -4 x 10 VGS= 2.5 V x 10 2.5 VGS= 2.5 V 5 2 ID (A) VGS= 2.0 V 3 VDS = VGS - VT 2 VGS= 2.0 V 1.5 1 VGS= 1.5 V 0.5 VGS= 1.0 V VGS= 1.5 V 1 0 0 Saturation ID (A) Resistive 4 VGS= 1.0 V 0.5 1 1.5 VDS(V) Long Channel 2 2.5 0 0 0.5 1 1.5 VDS(V) Short Channel 2 2.5 A PMOS Transistor PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V -4 0 x 10 -0.2 ID (A) -0.4 VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! -0.6 VGS = -2.5V -0.8 -1 -2.5 -2 -1.5 -1 VDS (V) -0.5 0 Parasitic Resistances Polysilicon gate LD increase W G Drain contact D S RS RS , D W VGS,eff RD LS , D W RSQ RC RSQ is the resistance per square RC is the contact resistance Drain Silicide the bulk region The Transistor as a Switch ID V GS = VD D Rmid VGS VT Ron S D R0 V DS VDD/2 VDD The Transistor as a Switch VGS VT 7 x105 6 S Resistance inversely proportional to W/L (doubling W halves Ron) Ron D 5 4 3 For VDD>>VT+VDSAT/2, Ron independent of VDD 2 1 Once VDD approaches VT, Ron increases dramatically VDD (V) 0 0.5 1 1.5 2 (for VGS = VDD, VDS = VDD VDD/2) 2.5 VDD(V) 1 1.5 2 2.5 NMOS(k) 35 19 15 13 PMOS (k) 115 55 38 31 Ron (for W/L = 1) For larger devices divide Req by W/L Summary of MOSFET Operating Regions • Strong Inversion VGS > VT – Linear (Resistive) VDS < VDSAT – Saturated (Constant Current) VDS VDSAT • Weak Inversion (Sub-Threshold) VGS VT – Exponential in VGS with linear VDS dependence Capacitance • Any two conductors separated by an insulator have capacitance • Gate to channel capacitor is very important – Creates channel charge necessary for operation • Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion Gate Capacitance • Approximate channel as connected to source • Cgs = oxWL/tox = CoxWL = CpermicronW • Cpermicron is typically about 2 fF/mm polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.90) Diffusion Capacitance • Csb, Cdb • Undesirable, called parasitic capacitance • Capacitance depends on area and perimeter – Use small diffusion nodes – Varies with process Capacitance of MOS Why it is important ? limits switching speed of the circuits How to estimate ? calculate from device dimension and dielectric constant for DSM the values are specified in femto Farad per micron of width (fF/µm) There are two types linear cap: voltage independent non-linear cap: voltage-dependent Design Rules • Non-linear :thin-oxide cap (Cg or Cgd, Cgd,and Cgb) pnjunction cap (Csb,Cdb) and depletion layer cap under channel (Cjc) • Linear: overlap cap (Col) Thin-Oxide or Gate Capacitor Polysilicon gate Source Drain xd n+ xd Ld W n+ Gate-bulk overlap Top view Gate oxide tox n+ L Parallel-plated cap (F): C Area thickness ε ox CG WL t ox n+ Cross section Lateral diffusion reduces channel length Thin-Oxide or Gate Capacitor Parallel-plated cap formed by gate and channel with oxide as the dielectric Cap values changes depending on operation mode of MOS Total amount (the maximum cap) is : CG = WLCox=WL(εox/tox)=WCg (fF) where Cg = CoxL = (εox/tox)L Cox : cap per unit area (fF/µm2) Cg : cap per unit width (fF/µm) Since tox an L are both scaled at the same rate Cg has remained constant ! Typical value for DSM is 1.6 fF/µm Gate Capacitance Decomposed into three capacitance: Cgb, Cgs, Cgd Depend on operation mode G G G S D S D S D Cgb Cgs Cut off Cgs Cgd Sat Linear Mode Cut off Sat Linear Cgb Cg 0 0 Cgs 0 (2/3)Cg Cg/2 Cgd 0 0 Cg/2 Gate Capacitance C In cut off region during the depletion mode Cgb is less than Cg because it is series with Cjc When VGS = 0, Cgb is about 1/2 Cg The most important regions are at cut off and saturation since that is where the device spends most of its time. Diffusion or pn-junction Cap C jo A Cj Vj m (1 ) fB Cjo: zero-bias junction capacitance A: area of junction m: junction graded coef. f BBuild in potential Vj: Junction bias voltage Diffusion or pn-junction Cap Y 3 4 5 1 Xj 2 W Cj = CjbAbottom + CjswAsidewall = Cjb(area of 5) + Cjsw(area of 1+2+3+4) Cap on 1,2,3 facing STI can be neglected Typical value of Cj ~ 0.2 fF/µm2 for 0.13 µm process Overlaps Capacitance Due to lateral diffusion and fringing field Linear or voltage independent Col = Cov + Cf Typical value of Col ~ 0.2 fF/µm for 0.13 µm process Capacitance: Summary Col 2 3 Complementary MOSFETS (CMOS) • N-Channel and P-Channel transistors can be fabricated on the same substrate as shown below nMOS and pMOS operation VDD Vin VDD Idsp Idsn Vout Vin Idsp Vout Idsn Vgsn = Vin Vgsp = Vin - VDD Vdsn = Vout Vdsp = Vout - VDD Graphical derivation of the inverter DC response: I-V Characteristics Make pMOS wider than nMOS such that n = p For simplicity let’s assume Vtn=Vtp Graphical derivation of the inverter DC response: current vs. Vout, Vin Load Line Analysis: For a given Vin: Plot Idsn, Idsp vs. Vout Vout must be where |currents| are equal Graphical derivation of the inverter DC response: Load Line Analysis Vin = 0 Vin0 Idsn, |Idsp| Vin0 Vout VDD Graphical derivation of the inverter DC response: Load Line Analysis Vin = 0.2 VDD Idsn, |Idsp| Vin1 Vin1 Vout VDD Graphical derivation of the inverter DC response: Load Line Analysis Vin = 0.4 VDD Idsn, |Idsp| Vin2 Vin2 Vout VDD Graphical derivation of the inverter DC response: Load Line Analysis Vin = 0.6 VDD Idsn, |Idsp| Vin3 Vin3 Vout VDD Graphical derivation of the inverter DC response: Load Line Analysis Vin = 0.8 VDD Vin4 Idsn, |Idsp| Vin4 Vout VDD Graphical derivation of the inverter DC response: Load Line Analysis Vin = VDD Vin0 Idsn, |Idsp| Vin5 Vin1 Vin2 Vin3 Vin4 Vout VDD DC Transfer Curve Transcribe points onto Vin vs. Vout plot DC transfer curve: operating regions DC Characteristics of a CMOS Inverter • • A complementary CMOS inverter consists of a p-type and an n-type device connected in series. The DC transfer characteristics of the inverter are a function of the output voltage (Vout) with respect to the input voltage (Vin). • • The MOS device first order Shockley equations describing the transistors in cut-off, linear and saturation modes can be used to generate the transfer characteristics of a CMOS inverter. Plotting these equations for both the n- and p-type devices produces the traces below. IV Curves for nMOS PMOS IV Curves DC Characteristics of a CMOS Inveter • • • • The DC transfer characteristic curve is determined by plotting the common points of Vgs intersection after taking the absolute value of the p-device IV curves, reflecting them about the xaxis and superimposing them on the n-device IV curves. We basically solve for Vin(n-type) = Vin(p-type) and Ids(n-type)=Ids(p-type) The desired switching point must be designed to be 50 % of magnitude of the supply voltage i.e. VDD/2. Analysis of the superimposed n-type and p-type IV curves results in five regions in which the inverter operates. • Region A occurs when 0 leqVin leq Vt(n-type). – – – – • The n-device is in cut-off (Idsn =0). p-device is in linear region, Idsn = 0 therefore -Idsp = 0 Vdsp = Vout – VDD, but Vdsp =0 leading to an output of Vout = VDD. Region B occurs when the condition Vtn leq Vin le VDD/2 is met. – Here p-device is in its non-saturated region Vds neq 0. – n-device is in saturation • Saturation current Idsn is obtained by setting Vgs = Vin resulting in the equation: I dsn n 2 Vun Vtn 2 CMOS Inverter DC Characteristics CMOS Inverter Transfer Characteristics • In region B Idsp is governed by voltages Vgs and Vds described by: V gs Vin VDD and Vds Vout VDD V VDD I dsp p Vin VDD Vtp Vout VDD out 2 2 Recall that : I dsn I dsp • n 2 Vin Vtn 2 p Vin VDD Vtp Vout VDD Vout VDD 2 2 • Region D is defined by the inequality VDD Vin VDD Vtp 2 • p-device is in saturation while ndevice is in its non-saturation region. p Vin VDD Vtp 2 ; Vin Vtp VDD I dsp 2 AND Region C has that both n- and p2 devices are in saturation. Vout I dsn n Vin Vtn Vout ; Vin Vtn • Saturation currents for the two 2 devices are: • Equating the drain currents allows us p to solve for Vout. (See supplemental Vin VDD Vtp 2 ; Vin Vtp VDD I dsp 2 notes for algebraic manipulations). AND 2 I dsn n Vin Vtn ; Vin Vtn 2 CMOS Inverter Static Charateristics Vin VDD Vtp • • • • • In Region E the input condition satisfies: The p-type device is in cut-off: Idsp=0 The n-type device is in linear mode Vgsp = Vin –VDD and this is a more positive value compared to Vtp. Vout = 0 nMOS & pMOS Operating points A VD Vout =Vin-Vtp B D Output Voltage • Vout =Vin-Vtn Both in sat nMOS in sat pMOS in sat C D 0 Vtp Vtn E VDD/2 VDD+Vt VD p D Beta Ratio If p / n 1, switching point will move from VDD/2 Called skewed gate Noise Margins How much noise can a gate input see before it does not recognize the input ? Noise Margins To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic DC parameters Input switching threshold: VTH Minimum high output voltage: VOH Maximum low output voltage: VOL Minimum HIGH input voltage: VIH Maximum LOW input voltage: VIL Latchup VD D VDD p + n + + n + p + + p n-well Rnwell p-source n Rnwell Rpsubs n-source p-substrate (a) Origin of latchup Rpsubs (b) Equivalent circuit SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular Berkeley Short-Channel IGFET Model MAIN MOS SPICE PARAMETERS SPICE Parameters for Parasitics Simple Model versus SPICE 2.5 x 10 -4 VDS=VDSAT 2 Velocity Saturated ID (A) 1.5 Linear 1 VDSAT=VGT 0.5 VDS=VGT 0 0 0.5 Saturated 1 1.5 VDS (V) 2 2.5 A unified model for manual analysis G S D B VT0(V) g(V0.5) VDSAT(V) k’(A/V2) l(V-1) NMOS 0.43 0.4 0.63 115 x 10-6 0.06 PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1 Technology Evolution • Semiconductor Industry Association forecast – Intl. Technology Roadmap for Semiconductors Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters , such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. Introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices. Impact of Device Variations 2.10 2.10 Delay (nsec) Delay (nsec) 1.90 1.90 1.70 1.70 1.50 1.10 1.20 1.30 1.40 1.50 1.60 Leff (in mm) 1.50 –0.90 –0.80 –0.70 –0.60 –0.50 VTp (V) Delay of Adder circuit as a function of variations in L and VT Parameter Variation • Transistors have uncertainty in parameters – Process: Leff, Vt, tox of nMOS and pMOS FF pMOS SF TT FS SS slow • Fast (F) – Leff: ____ – Vt: ____ – tox: ____ • Slow (S): opposite • Not all parameters are independent for nMOS and pMOS fast – Vary around typical (T) values slow nMOS fast Parameter Variation • Transistors have uncertainty in parameters – Process: Leff, Vt, tox of nMOS and pMOS FF pMOS SF TT FS SS slow • Fast (F) – Leff: short – Vt: low – tox: thin • Slow (S): opposite • Not all parameters are independent for nMOS and pMOS fast – Vary around typical (T) values slow nMOS fast Environmental Variation • VDD and T also vary in time and space • Fast: – VDD: ____ – T: ____ Corner Voltage Temperature 1.8 70 C F T S Environmental Variation • VDD and T also vary in time and space • Fast: – VDD: high – T: low Corner Voltage Temperature F 1.98 0C T 1.8 70 C S 1.62 125 C Scaling Scaling Transistors :Constant field scaling and lateral scaling Interconnect • The only constant in VLSI is constant change • Feature size shrinks by 30% every 2-3 years – Transistors become cheaper – Transistors become faster and lower power – Wires do not improve (and may get worse) • Scale factor S 2 Scaling Constant field Scaling Proposed by Dennard in 1974 . Electric fields remain the same as features scale. Scaling assumptions All dimensions (x, y, z => W, L, tox) Voltage (VDD) Doping levels Lateral scaling:Only the gate of the transistor is scaled.Also called as gate shrink scaling. Scaling Effects •Gate capacitance per micron is nearly independent of process •But ON resistance * micron improves with process •Gates get faster with scaling (good) •Dynamic power goes down with scaling (good) •Current density goes up with scaling (bad) Constant field Scaling Constant & Lateral scaling Interconnect scaling Wire cross-section w, s, t all scale Wire length Local / scaled interconnect Global interconnect Interconnect scaling Interconnect scaling Interconnect scaling Interconnect scaling