Download Nanocrystlline Oxide Semiconductor Materials for Future Semiconductor and Display Technology

Nano-crystalline Oxide
Semiconductor Materials for
Semiconductor and Display
Technology
Sanghun Jeon Ph.D. Associate Professor
Department of Applied Physics
Korea University
Personnel Profile (Affiliation and Employment)
Affiliation
Associate Professor in the Department of Applied Physics at Korea University
Education
03 Ph.D. Electronic Materials (Semiconductor Device, MOS dev. & Tr. Tech
(w/ Best Paper Award & Young Researcher Award)
Young Researcher Award at Int. Conf. on SSDM Nagoya Japan 2002)
Employment
~ 10 Yr experience at Samsung Adv. Inst. Tech., and Samsung Electronics in Semiconductor Area
for Last a Decade with 6 research awards.
12~
Samsung Adv. Inst. Tech., SEC. Principal Research Staff Member
Project leader of Haptic materials and devices (Tactile sensor)
09~11 Samsung Adv. Inst. Tech., SEC. Principal Research Staff Member
Ox-based Device, Lead Device Physicist and Process Integrator
Photo/Image Sensor, Interactive Display, Integrated Circuits, High Power Device Transparent device, 3D
device, Electrical/Reliability/Modeling works.
05~09 Memory Business Division of SEC, Senior Research Staff Member
Charge Trap Flash (8, 16, 32Gb). Process Integrator and Device Engineer.
03~05 Samsung Adv. Inst. Tech., [SAIT] Senior Research Staff Member
Initiative Study on Charge Trap Flash Memory Device.
Technology Transfer @ Samsung
Two-time tech. transfer from SAIT to business divisions of SEC, memory
division (2005-2009) and display division (2011)
16Gb
Flash
Tech.
8Gb
Flash
Device
32Gb
Flash
Tech.
Memory
Division of
SEC (20052009)
SAIT (2003-2005) Tech. Transfer
Meeting
Basic Research
Specification of
on CTF
NAND for 40nm gen.
1T DRAM
Display Division
of SEC (2011)
SAIT (2009-2012)
Various
Understanding on Demonstration
of Ox. Sensor Sensors for
science of oxide
E-Body
Array
Contents
For nc-ox. device, I present various applications.
Image Sensor
Power
Display
-9
10
-11
10
-13
10
-20 -15 -10 -5 0 5
VGS [V]
H
VIN (V)
VOUT (V)
H
100Å
OUT
IN
20
10
Bi-layer
HIZO-IZO Bi-Layer
Sample
TFT Response Speed
50nsec
nQ
S
Monitoring
signal
Q
R
40mv =>800uA
Sample signal
L
2.0m
4.0m
Time (sec)
6.0m
0.000
50
600Å 40
30
High Data Latch Output
Low Data Latch Output
L
0.0
IZO Thickness
200Å 400Å
0.20
0.15
HIZO-IZO
Bi-layer
0.10
IZO: 100Å
-11 200Å -HIZO/IZO
10
IZO: 200Å
0.05
IZO: 400Å
VDS:10V
Single
IZO: 600Å
-13
0.00
10
0
100 200 300 400 500
10 15 20
HIZO
VDS [V]
-9
10
H
L
Single
HIZO:400Å
0.001
0.002
0.003
Time (sec)
0.004
VLSI 2012
0
2
-7
10
VOUT (V)
IDS [A]
10
-7
10
sat [cm /Vs]
-5
Power, BV× Ion [W]
HIZO(200Å )-IZO Bi-layer
IZO: 100Å
IZO: 200Å
IZO: 400Å
IZO: 600Å
HIZO:400Å
Single Layer
-3
IDS @ VGS-VTH=-1V [A]
Bilayer oxide transistor exhibits remarkable performance such as, high mobility
(23~47cm2/Vs) and high breakdown voltage (BV) of 60~340V despite low process
temperatures (<300°C), which can be integrated on metal pad.
10
Memory
The Evolution of Devices
•
CMOS Logic Device (Si → III-V/ Graphene on Si)
Si based Integration
III-V Integration
Graphene
High-k
metal gate
•
Memory (Planar →Vertical/Hybrid Integration)
Planar Structure, IEDM 2006
VNAND, VLSI 2009
AOS TFT
RRAM, Adv.
Fuct. Mat. 2008
Transition
Ox. Based
RRAM
Key Trend: Alternative Materials and 3D Stack
Benefit of nc-InGaZnO, nc-HfInZnO, and
nc-InZnO
• Optical transparency due to large band-gap of ~3.4eV
• Stackable process nature due to low temp. process capability
• Nano-crystalline structure in amorphous matrix (negligible DVth) but High  (>10)
→ The integration of nc-oxide semiconductor onto Si circuits is possible.
CCD Spectrum profile
Drift corrected spectrum profile Scanning
SiO2
CCD Spectrum profile
Spectrum profile Scanning
Mo
GIZO
IZO
Mo
GIZO
HIZO
IZO
CCD Spectrum profile
CCD Spectrum profile
GIZO
GIZO
SiO2
HIZO
CCD Spectrum profile
CCD Spectrum profile
1
IZO
CCD Spectrum profile
GIZO
CCD Spectrum profile
IZO
CCD Spectrum profile
IZO
CCD Spectrum profile
GIZO
CMOS Image Sensor
Applications
Current Status of CIS Devices
• Like others, CIS devices are facing physical limitation
• Shrinking the pixel size is a major driver for imaging business
• Pixel performance is inversely proportional to the size of CIS
• At a pace which counteract both, new technique is needed
6 Conventional Architecture New architecture
6
BSIS
FSIS
4
BSIS+ α 3D Stack
(3D Stack)
5
60 80
3
4
40 60
2
3
1
20 40
2
0
12000-2H
0
2004-2H
2007-2H
2010-2H
2012-2H
2015-2H
20
Time
0 Front side image sensor BSIS: Back side image sensor
FSIS:
2000-2H
2004-2H
2007-2H
2010-2H
2012-2H
0
2015-2H
Time
FSIS: Front side image sensor BSIS: Back side image sensor
Resolution (Mega Pixel)
80 100
5
Size (um)
Pixel (nm)
Pixel Size
Light source
Light path
Blocked/deflected light
100
Resolution (Mega Pixel)
Conventional Architecture New architecture
Color filter
Metal 2
Metal 1
Photo diode
Front side image
sensor
Color filter
Photo diode
Metal 1
Metal 2
Back side image
sensor
Pixel Circuit of CMOS Image Sensor
• A pixel consists of 1 Photodiode (PD) and 4 Transistors.
• Pixel Tr.s (Reset, SF, RS) are shared with neighboring pixels
• Interestingly, all pixel transistors are NMOSFET
• Pixel Tr.s (Reset, SF, RS) with less stringent requirement can be replaced with
oxide TFT
VDD
TX11 TX12 RS
TX21 TX22
PD
FD
Column Bus
TX: Transfer Gate Transistor
Reset: Reset Transistor
SF: Source Follower Transistor
RS: Row Select Transistor
PD: Photodiode
FD: Floating Diode
SF
Reset
Our Approach
• The integration of electronically active oxide device onto silicon circuit.
• Here we propose a novel hybrid CIS architecture utilizing nanometer scale
nano-crystalline oxide TFT with a photodiode.
S. Jeon et al., ACS Applied Mat. Int. 2011
S. Jeon et al., IEEE IEDM 2010
Micro-lens
Metal line
Transparent
conducting line
nc-oxide TFT
Structural Comparison (1st layer)
• This demonstrates how Si PD in active can be enlarged.
Conventional
Novel Hybrid
Other Pixel
Transistors
Transfer Gate Si
Transistor
Transfer Gate
Transistor
Si PD
Si PD
Structural Comparison (2nd layer)
• The 2nd layer of a novel hybrid four-pixel CIS structure consists of inter-connect
metal lines and other pixel transistors.
• Some interconnect metal lines for delivering constant voltage, VDD, are replaced
by a TCO
Novel Hybrid
Conventional
Micro-lens
Micro-lens
Transparent
Conducting
Line
Metal
line
TFT
nc-IGZO TFT
Simulation Results
• Electromagnetic power density contour plots were calculated by Sentaurus
electromagnetic solver.
• The simulation results reveals a quantum efficiency increase of 143% 116%, and
120% at blue, green, and red wavelengths, respectively.
Novel Hybrid
Conventional
Pixel
Wavelength (nm)
Conventional
Hybrid + TCO
Interconnect Line
540
Conventional
Hybrid + TCO
Interconnect Line
Ratio (%)
34.3
-
49.2
143
61.9
-
71.5
116
41.3
-
49.4
120
450
Conventional
Hybrid + TCO
Interconnect Line
Quantum Efficiency (%)
650
Structural Analysis & Electrical Analysis
• Self aligned top gate structure
• Dual gate stack (SiO2/Al2O3)
• Trapezoidal active channel
• nc-oxide semiconductor
Z
S. Jeon et al., Applied Physics Letters 2011
Y
b
180nm
X-X ’
X
-4
10
a-IGZO
-5
10
-6
10
Mo
Mo
Al2O3
SiO2
IGZO
5 nm
Y-Y ’
IDS(A)
IGZO
-7
10
Vd=0.1V
Vd=1.0V
Vd=2.0V
Vd=3.0V
Vd=4.0V
Vd=5.0V
-8
10
-9
10
-10
10
-11
10
-12
10
-4
-2
0
VGS(V)
2
4
Memory Applications
Essential Device Architecture for V-NAND
Even with revolutionary transition, the core stack remains the same.
Vertical NAND for 1 terabit and beyond
Planar NAND
Revolutionary Transition
Core CTF Stack for Vertical NAND
S. Jeon et al., US 7,391,075
High FM metal
High k
SiN
SiO2
Si
Three dimensional approach to high density memory
The schematics of 3D approach
Depletion load inverter by hybrid channel
Oxide TFT for 3D logic
b
a
Vertical NAND Flash
Memory Layer
3D Logic
Stackable RRAM
Bottom Logic
Bottom Si
Layer:CMOS
Integrated circuits: Ring oscillator & NOR decoder
Conventional
Architecture
3D Logic
Architecture
Oxide-based integrated circuits
can be applied to integrated
sensors.
IEDM 2009, IEEE TED 2011, ACS
Appl. Mat. Int. 2011
Power Applications
Conventional Power and This System
Different device specifications of PMIC & gate driver hinders on-chip integration even with
the merits, such as low cost, reduced form factor, and low noise.
S. Jeon et al., VLSI 2012
Conventional Power System
Currently Proposed System
Conventional Power system
Power system with gate driver
PMIC
PMICOxide
PMIC
Gate DRV
using ox. Tr.
Gate DRV
Gate DRV
Power TR.
Power TR.
Power TR.
High Power Oxide Transistor Technology
-7
10
-9
10
-11
10
-13
10
-20 -15 -10 -5 0 5
VGS [V]
H
VIN (V)
H
VOUT (V)
L
H
0.20
OUT
IN
30
20
10
Bi-layer
HIZO-IZO Bi-Layer
Sample
High Data Latch Output
50nsec
nQ
S
Monitoring
signal
Q
R
40mv =>800uA
Sample signal
L
2.0m
4.0m
Time (sec)
6.0m
0.000
600Å 40
TFT Response Speed
Low Data Latch Output
L
0.0
100Å
0.15
HIZO-IZO
Bi-layer
0.10
IZO: 100Å
-11 200Å -HIZO/IZO
10
IZO: 200Å
0.05
IZO: 400Å
VDS:10V
Single
IZO: 600Å
-13
0.00
10
0
100 200 300 400 500
10 15 20
HIZO
VDS [V]
-9
10
VOUT (V)
IDS [A]
10
Single
HIZO:400Å
50
0.001
0.002
0.003
Time (sec)
0.004
VLSI 2012
0
2
-5
-7
10
IZO Thickness
200Å 400Å
sat [cm /Vs]
10
Power, BV× Ion [W]
HIZO(200Å )-IZO Bi-layer
IZO: 100Å
IZO: 200Å
IZO: 400Å
IZO: 600Å
HIZO:400Å
Single Layer
-3
IDS @ VGS-VTH=-1V [A]
Bilayer oxide transistor exhibits remarkable performance such as, high mobility
(23~47cm2/Vs) and high breakdown voltage (BV) of 60~340V despite low process
temperatures (<300°C), which can be integrated on metal pad.
Display Applications
In-cell touch technologies
 Displays with touch functionality are in great demand.
“ In-cell touch display” is an industrial goal (integration of
sensor into LCD cell)
 Even with various approaches, there is no clear solution to
realize large area interactive display.
 Previous photo-sensor technologies based on a-Si are not
applicable for large area touch screen due to low speed.
Information
Display 2010
Motivation of oxide photo-sensor
 Large Area Interactive Display
Large size
Motion picture
(>120Hz)
High resolution
(FHDUD)
• Display size is limited
by driving speed.   5
cm2/eV/s for UD-level
High  oxide TFT for
display
• Process compatibility:
oxide sensor
Sensor Region
Display Region
R
G
B
Gated Three Terminal Sensor Architecture
 High photo-current for oxide sensor leads to simple pixel structure
 2 TFT architecture: One sensor TFT & one switch TFT (Shield Metal)
 Transparent photo-sensor array due to simple structure S. Jeon et al., Nature Materials 2012
a-Si Photo TFT array
Oxide Photo TFT array
S. Jeon et al., Adv. Mat. 2012
S. Jeon et al., IEEE IEDM 2010
S. Jeon et al., IEEE IEDM 2011
Sensor
Switch
Source/Drain
Shield Metal
Gate
Isolation Ox.
-7
10
IDS [A]
Ox. TFT
Light
Fully Transparent Ox. Sensor Array
Passivation
-9
10
a-Si TFT
-11
10
Dark
-13
10
-1
10
1
10
3
10
5
10
Pulse Cycle [#]
7
10
9
10
GIZO
IZO
Switch SensorGIZO
Gate Ox.
Demonstration of photo-sensor array and Interactive
Display
Photo-sensor in 2010
Interactive Display in 2011
Array : 192 x 256 lines
(49,152 pixels)
S. Jeon, Nature Materials
S. Jeon IEDM 2010, Adv. Mat. 2012, SID 2012
Summary
• NC-oxide semiconductor devices present various device applications.
• We proposes a novel hybrid CMOS image sensor utilizing oxide TFT and
demonstrating excellent device performance of 180nm Lg TFT for future
high density CIS devices.
• We present the three-dimensionally alternating integration of stackable
logic devices with memory cells
• We present high performance bilayer oxide semiconductor such as
HfInZnO/InZnO transistor for high power application
• We have integrated photo-TFTs in a transparent active-matrix
photosensor array that can be operated at high frame rates and that has
potential applications in contact-free interactive displays