Download Sequential Circuit Design

Clock Distribution
Shmuel Wimer
Bar Ilan Univ. Eng. Faculty
Technion, EE Faculty
July 2010
1
Clock System Architecture
clk3
External
Clock
ext_clk
Clock
Generator
Clock
Distribution
gclk
Buffers
clk1
Clocked
Elements
Gaters
clk2
Chip
Chip receives external clock through I/O pad.
Clock generator adjusts the global clock to the external clock.
Global clock is distributed across the chip.
Local drivers and gaters drive the physical clocks to clocked elements.
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2
Global Clock Generation
• Receives external clock signal and produce the global
clock distributed across the die.
• A large skew occurs between external clock and the
physical clocks at clocked elements due to delay of
distribution network (wires, buffers, gaters).
• Therefore, data at clocked elements is no more in sync
with data at I/O pins.
• Phased Locked Loop (PLL) compensates this delay.
• PLL can perform frequency multiplication to obtain the
required on-chip frequencies.
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Synchronous Chip Interface with PLL
Chip A communicates synchronously with chip B
Chip B uses the clock sent by chip A. Data in and out must be
synchronized to the common clock.
A PLL produces the global clock of chip B such that it is in sync
with the external clock.
Chip A
Chip B
CLKin
ext_clk
CLKout
clk
Dout
Din
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Din
ref_clk
PLL
clk_out
gclk
fdbk_clk
Dout
Clock Distribution
4
How PLL Works?
Charge
Pump
Loop
Filter
C
Up
I R
ref_clk
M
fdbk_clk
Phase
Detect
Vctrl
N
Voltage
Controlled
Oscillator
clk_out
I
Down
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Phase – Frequency Detector (PFD)
1
D
Q
Q_A: B should go
faster
A
CLR
CLR
B
1
D
Q
Q_B: B should go
slower
The two flip-flops receive the signals at their clock input (one is usually a
reference and the other is the sampled).
The output of the leading flip-flop is 1 for the lead duration.
Once the lagging signal arrives, a reset turns both Q_A and Q_B to zero.
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What happens when the reference and the sampled signals are a shift of
each other?
A: reference
B: sampled
Q_A: sampled
should go faster
Q_B: sampled
should go slower
The spikes at Q_B are a result of the delay of the AND gate driving the
CLR input of flip-flip and the internal delay from CLR to Q.
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What happens when the reference and the sampled signals have different
frequencies?
A: reference
B: sampled
Q_A: sampled
should go faster
Q_B: sampled
should go slower
Sampled is more often 1-value than the reference is, since rising edge of
B occurs more often than rising edge of A.
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Charge Pump
faster
1
D
Q
Icp
CLK_ref
CLR
Sup
Vctrl
Sdn
CLR
CLK_fdbk
1
D
Icp
Q
slower
Converts PFD error (digital) to charge (analog), which then controls PLL VCO.
Charge is proportional to PFD widths: Qcp  I up  tfaster  Idn  tslower .
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Current Mirror
Iin
Vcc
V
Iout
N2
N1
P1
Iin
Vss
V
P2
Iout
Charge pump consists of current mirrors which are sources of constant
current. Device N1 is in saturation since its gate is connected to high voltage.
Ids (=Iin) depends only on Vgs. Vgs is similar in N2, hence Iout=Iin.
This is an ideal current source with infinite output impedance since Iout is
independent of N2 load; a change in output voltage doesn’t affect Iout.
Current mirror works similarly for P transistors.
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How Charge Pump Works?
R load – determines
the current through
current mirror
Vcc
I
I
Vcc
I
C
P-type current mirror
faster
R
Switch – open when
faster = 1
Switch – open when
slower = 1
Vout
slower
I
I
I
N-type current mirror
Vss
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Faster Mode Vout → Vcc
Vcc
Vcc
C
faster=1
R
Vout
slower=0
Vss
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Slower Mode Vout → Vss
Vcc
Vcc
C
faster=0
R
Vout
slower=1
Vss
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Loop Filter
Vcc
C
R
Vctrl
+
Vctrl
-
Differential amplifier connected as a unity-gain follower is used.
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14
Voltage Controlled Oscillator (VCO)
A Ring Oscillator cascades an odd number of inverters and feeds back the
last output to first inverter (even number of inverters will be stable). It starts
to oscillate spontaneously.
Vout
If tinv is the delay of an inverter and n is the number of inverters,
oscillation frequency is f  1  2ntinv 
Frequency can be controlled by number of inverters and supply voltage
of inverter (higher voltage obtains faster inverter).
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Components of VCO
Buffering for
driving clk_out
clk_out
Vctrl
Vcc
- cc
V
V-cc
+
-
+-
Vss
Ring of 5 inverters
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Level Converter from
Vctrl-Vss to Vcc-Vss
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Delay Locked Loop (DLL)
• It is a variant of PLL that uses voltage-controlled delay
line rather than oscillator.
• It adjusts phase only. Frequency multiplication is
impossible.
• It is simpler than PLL, less sensitive to Vctrl noise and
requires simpler loop filter.
• It is very difficult to correctly design PLL and DLL. It
requires expertise in control systems and analog circuit
design.
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How DLL Works?
Charge
Pump
Loop
Filter
C
Up
I R
ref_clk
Phase
Detect
Vctrl
fdbk_clk
Voltage
Controlled
Delay Line
clk_out
I
Down
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Clock Distribution Networks
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Tree Clock Network (Unconstrained)
clk1
clk2
clk3
clkn
No constraints imposed on buffers and wires.
Used mostly by automatic tools in automatic synthesis flows.
Can be used for small blocks within large design.
Tools aim at minimizing the variance of clock delays.
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If TCLK is the clock delay at a leaf, the variance exapression
i

n 
T
i 1  CLKi

2
1 n

  i 1TCLK  should be minimized.
i
n
Serpentine routing or extra buffers may be introduced
to obtain small variance.
Constraints on power can be imposed by limiting
number and size of clock buffers and width of wires.
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Clock Distribution with Grids
Grid feeds flops
directly, no local
buffers
Clock driver tree spans height of chip
Internal levels shorted together
Low skew but high power
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Clock drivers are on perimeter
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Clock drivers are on grid points
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Delay and Skew in Grid Distribution
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DEC’s Alpha Microprocessor Clocking
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DEC Alpha 21264 Microprocessor Clock distribution
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Clock Distribution with Spines
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Intel’s Pentium4 Clock Distribution
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Clock Distribution with Trees
RC-Tree
Each branch is individually
routed to balance RC delay
H-Tree
Recursive pattern to
distribute signals uniformly
with equal delay over area
More skew but less power
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Clock H-Tree
chip / functional block / IP
sequential elements
clock / PLL
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IBM / Motorola PowerPC Clock Distribution
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Delay Calculation
We use Elmore delay model. Sub trees are modeled
as capacitive loads
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Clock Skew and Jitter
• Clock should theoretically arrive simultaneously to all
sequential circuits.
• Practically it arrives in different times. The differences
are called clock skews.
• Skews result from paths mismatches, process variations
and ambient conditions, resulting physical clocks.
• Most systems distribute a global clock and then use
local clock gaters located near clocked elements.
Clock skew consists of the following components:
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• Systematic is the portion existing under nominal
conditions. It can be minimized by appropriate design.
• Random is caused by process variations like devices’
channel length, oxide thickness, threshold voltage, wire
thickness, width and space. It can be measured on
silicon and adjusted by delay components.
• Drift is caused by time-dependent environmental
variations, occurring relatively slowly. Compensation of
those must takes place periodically.
• Jitter is rapid clock changes, occurring by power noise
and clock generator jitter. It cannot be compensated.
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Factors affecting clock skew, Intel 1998, 0.25u.
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Skew, Clock Cycle and Design Margins
Clock Jitter is the same order as skew, but far more
difficult to compensate.
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Skew Modeling
Point of
divergence
Q
1
2

Clock
Generator
1
2
Tclk1
m
CL
Tclk2
n
D
TCLK1  
m
T
i 1 i
 m
TCLK2  
n
T
i 1 i
 n
Cl - capacitive load, Id - drive current, VCC - voltage swing
  Cl VCC I d
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Consider a small change in the delay, taking the linear term.
VCC
ClVCC
Cl



 
VCC 
Cl 
I d  VCC 
Cl 
I d
2
VCC
Cl
I d
Id
Id
Id
 VCC Cl I d 
 


  
Cl
Id 
 VCC
Standard deviation of stage delay is    = .  is around 5%.
If clock buffers delays are normally distributed and independent
of each other, then  TCLK1   m , and  TCLK2   n .
Skew is:  Tskew    | TCLK2  TCLK1 | 
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

m  n  skew .
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Clock Distribution Switching Power
Consider m - level clock tree.
Let Cl_m be the total load of its far-end driven sequential
elements.
Assuming a fixed fanout k of each clock tree buffer, the
dynamic power is:
2
PCLK_m  Cl_mVCC
f,
PCLK_  m j  
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Cl_m
kj
2
VCC
f , 0  j  m  1.
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Summing over whole clock tree:
PCLK  
2
VCC
f
m 1
2
C
V
j 0 l_  m  j  CC
m 1 Cl_m
j
j 0
k
f 
1  1 k m 
2

 VCC
fCl_m 
 1  1 k  
How much of the power is consumed by the far
end drivers of clock tree?
PCLK _ m
PCLK
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
1  1 k 
1  1 k 
m
.
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Given the number of sequential elements in a block, at
least 50% of the switching power is consumed by the
far end drivers (clock tree is binary, k=2). This number
approaches 1 rapidly with k growth.
Example: Assume a block with 214 sequential elements
and H-tree clock distribution. Then k=4 and m=7. The
far end drivers consume nearly 75% of the clock tree
switching power, while adding the next upper level
drivers brings it to more than 90%.
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Active Clock De-Skewing
• Compensates process variability, temperature gradients,
imperfect design.
• Can be implemented for global fixes (small HW
overhead) or local fixes (high HW overhead).
• Can be used at testing for one time fix (variability
occurring
during
manufacturing),
or
dynamically
concurrently with chip operation.
• Its implementation is a difficult design challenge.
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Intel’s Pentium2 De-Skewing System
1998, 450MHz Clock
0.25u process
60pSec skew w/o fix
15pSec skew with fix
Two clock spines for
two clock regions.
A phase detector
detects relative shifts.
Clock of a region is
shifted by a delay line.
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Delay line consists of two cascaded inverters.
Each has a programmable load consists of eight parallel P-N gate
capacitors.
The shift register stores a thermometer code for load programming
in steps of 12pSec.
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Another Programmable Delay Line
The signal from input to output is delayed
In
1
or not according to the control bit.
Out
0
In
2 n1
1
2n2
1
0
0
Dn 1
Dn  2
1
1
Out
0
D0
Connecting a series of n delay elements, each of delay 2i , n  1  i  0,
it is possible to control the dely of the line to any value from 0 to 2 n  1
dealy units by an n-bit control word  Dn1, Dn2 ,
July 2010
, D0  .
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Intel’s IA64 Itanium1 De-Skewing System
2000, 800MHz clock
0.18u process
28pSec skew with fix
X4 increase w/o fix
30 independent de-skew
regions.
PLL
Each cluster is driven
from a global H-tree.
Delay circuit in de-skew
region are similar to
Pentium3 with 20-bit
registers.
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July 2010
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Proposal for H-Tree Clock De-Skew –
Hierarchical Approach
If a phase detector (PD) has a skew guard band g, then guard bands
may accumulate along tree paths.
For example, if a logic stage is shared between region B and C, it may
add 7g time units to path delay.
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Proposal for H-Tree Clock De-Skew –
Mesh Approach
Clock is distributed by Htree, but de-skew takes
place by neighbor leaves
phase detection.
A delay buffer accepts
phase inputs from its 4
neighbors and then
decides of whether to
increase, decrease or
not change its delay.
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Clock Characteristics of Commercial Processors
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Power Consumption in Chips
• Clock power may reach 50% of total (dynamic +
static).
• Clock gating is very useful and standard design
practice
• Four gating methods:
– Synthesis based, automated by EDA tools, RTL
compilers, inserted into clock-tree
– Clock enable signals manually defined by designer,
inserted into clock-tree, FFs’ clock input
– Data-Driven clock gating, inserted at FF-level
– Auto-gated FF, inserted at latch-level
52
FF Data Toggling (DSP core)
23k FFs, Test bench of 250k CLK cycles
10% of application run-time CLK is enabled.
Of which, only 1.6% CLK pulses are useful!
53
FF Data Toggling
0.3
1.2
63 control blocks of ϻP, 200k FFs
1
b
0.2
0.8
0.15
0.6
0.1
0.4
a
0.05
0.2
0.03
0
0
1
6
11
16
21
26
31
36
block count
41
46
51
56
61
cumulative normalized clock
capacitive load
data activity / clock activity
0.25
Data-Driven CLK Gating
55
tight
constraint
56
How Many FFs To Group ?
k: # flip-flops, q: FF probability of D=Q
q=1-p
Worst case : All FF are toggling independently of each other.
Latch overhead
amortized over k FFs
Net saving per FF
csaving  q
k
 cFF  cw   clatch
k  1  q   cw  cOR  
FF
Gater’s disabling probability
Derivate by k:
Probability of enabling FF
qk ln q  cFF  cW   clatch k 2  0
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58
Optimal Flip-flop k-size Grouping
Given n flip-flops and m  1 clock cycles
a   a1, , am  is the activity (toggling) of flip-flop
FF1: 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0
FF2: 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1
ai  a j is the number of redundant clock pulses
ocurring by jointly clocking FFi and FFj
59
FF Pairwise Activity Model
G V , E, w: FF pairwise activity graph.
vi V corresponds to FFi .


eij  vi , v j  E is FF pairing.
ai | a j is joint toggling.
 
w eij  ai  a j is redundant clock pulses, hence a waste.
E   E: vertex matching
60
Total power:
P  2e
ij E
 v V
i
v V
i
ai | a j 
ai   e
 ai   ai | a j   a j   ai | a j   

E 
e E  

ai   e
Essential + Waste
ai  a j   v V ai   e E w  eij 
ij
ij E 
ij
i
ij
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Flip-Flop Grouping Algorithm
FFj
Minimize:
 FFi  FFj
FFi  FF j
FFi
Optimal FFs pairing
can be solved by
minimal cost perfect
graph matching.
Can be repeated for groups of size 4, 8, 16 …
62
Is repeated perfect matching optimal ?
a 7 | a8
a1 | a2
a1
a3
a3 | a 4
a6 | a5
a2
a7
a4
a6
a5
a8
63
No! Here is the optimal 4-size grouping
64
Multi-Bit Flip-Flop
Saving the power of internal CLK drivers
1-bit flip-flop
2-bit flip-flop
CLK
CLK
D
Master
Latch
CLK
Slave
Latch
+
Q
=
CLK
CLK
D
Master
Latch
Master
Latch
CLK
Slave
Latch
Q1
CLK
CLK
D2
CLK
Slave
Latch
D1
Master
Latch
Slave
Latch
Q2
Q
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MBFF should be combined with data-driven CG to
maximize energy savings.
Toggling vectors (VCD) are unfortunately not
always available.
Data-to-clock toggling ratio (probability) is more
often available.
How to utilize it for MBFF optimal grouping?
67
What is the energy waste in 2-bit MBFF?


p j 1  pi   pi 1  p j  pi  p j  2 pi p j
For n FFs grouped
in n/2 MBFFs it is
n
n2
j 1
i 1
 p j  2 psi pti
What is the optimal MBFF grouping?
Group the FFs such that
p1  p2 
 pn
68
Auto-Gated FF
69
Look-Ahead CLK Gating
70
Relaxed
constraint
71
Power Saving Per FF
save
cdyn

1  p   cFF+CLK  cFF  cO  
k
 cFF+CLK

p  cX  kcO   
 cAint  cFF  cO 
3


72
Which FF to Gate?
73
Results
74
75