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Differential Amplifiers/Demo
Motivation and Introduction
The differential amplifier is among the most important circuit inventions, dating back to the
vacuum tube era. Offering many useful properties, differential operation has become the
dominant choice in today's high-performance analog and mixed-signal circuits.
This chapter deals with the analysis and design of CMOS differential amplifiers. Following a
review of single-ended and differential operations, we describe the basic differential pair, and
analyze both the large-signal and the small-signal behavior. Next, we introduce the concept of
common-mode rejection and formulate it for differential amplifiers. Finally we study differential
pairs with diode-connected and current-source loads as well as differential cascode stages.
Prerequisites
Concept of amplification, MOS physics, small signal and large signal models.
Learning Outcome

Knowledge of Various types of differential amplifier.

Characteristics of Differential Amplifiers

Applications of Differential amplifiers

Ability to decide Which Differential Amplifier.

Designing out of specifications

Ability to draw and understand the characteristics
Suggested Time
10 hours
Single Ended and Differential Operation
Differential Operation
Definitions
A single-ended signal is defined as one that is measured with respect to
a fixed potential, usually the ground. A differential signal is defined as
one that is measured between two nodes that have equal and opposite
signal excursions around a fixed potential. In the strict sense, the two
nodes must also exhibit equal impedance to that potential. Figure 1
illustrates the two types of signals conceptually. The "center" potential
in differential signalling is called the "common-mode"(CM) level.
Figure 1. Single-Ended Signal (left) Differential Signal (Right)
Advantages of Differential Operation over Single-ended
An important advantage of differential operation over single-ended
signaling is higher immunity to "environmental" noise. Consider the
example depicted in Figure 2, where two adjacent lines in a circuit carry
a small, sensitive signal and a large clock waveform. Due to capacitive
coupling between the lines, transitions on lineL2 corrupt the signal on
line L1. Now suppose as shown in figure 2(b), the sensitive signal is
distributed as two equal and opposite phases. if the clock line is placed
mid-way between the two, the transitions disturb the differential
phases by equal amounts, leaving the difference intact. Since the
common-mode level of the two phases is disturbed but the differential
output is not corrupted, we say this arrangement "rejects" commonmode noise.
Figure 2(a) Corruption of a signal due to coupling (b) Reduction of
coupling by differential operations
Thus far, we have seen the importance of employing differential paths
for sensitive signals. It is also beneficial to employ differential
distribution for noisy lines. Another useful property of differential
signaling is the increase in maximum achievable voltage swings. Other
advantages of differential circuits over single-ended counterparts
include simpler biasing and higher linearity.
Animation
Corrsigdiff.swf (For your convenience you can get them inside Self
Learning Quadrant)
Drawbacks of Differential Operation
The differential circuits occupy twice as much as area as single-ended
alternative. But in practice this is a minor drawback, Also, the
suppression of non-ideal effects by differential operation often results
in a smaller area than that of a brute-force single-ended design.
Furthermore, the numerous advantages of differential operation by far
outweigh the possible increase in area.
Basic Differential Pair
Introduction
How do we amplify a differential signal? As suggested by the
observations in the previous section, we may incorporate two identical
single-ended signal paths to process the two phases(Figure 1). Such a
circuit indeed offers some of the advantages of differential signaling:
high rejection of supply noise, higher output swings etc. But what
happens if Vin1 and Vin2 experience a large common-mode disturbance
or simply do not have a well defined common-mode dc level? As the
input CM level, Vin,CM changes, so do the bias currents of M1 and M2,
thus varying both the transconductance of the devices and the output
CM level. The variation of the transconductance in turn leads to a
change in the small-signal gain while the departure of the output CM
level from its ideal value lowers the maximum allowable output swings.
For example, as shown in Figure 1, if the input CM level is excessively
low, the minimum values of Vin1 and Vin2 may in fact turn off M1and M2,
leading to severe clipping at the output. Thus, it is important that the
bias currents of the devices have minimal dependence on the input CM
level.
Figure 1(a) Simple Differential Circuit (b) illustration of sensitivity to the
input common-mode level.
A simple modification can resolve the above issue. SHown in Figure 2,
the
"differential
pair"
employs
a
current
source ISS to
make ID1+ID2 independent of Vin,CM. Thus, if
, the bias current
of each transistor equals
and the output common-mode level
is
. It is instructive to study the large-signal behavior of
the circuit for both differential and common-mode input variations.
Figure 2. Basic Differential Pair
Qualitative Analysis
Let us assume that in Figure 2,
varies from - to + .
If Vin1 is much more negative than Vin2, M1 is off, M2 is on, and
. Thus,
and
. As Vin1 is brought closer
to Vin2, M1 gradually turns on, drawing a fraction of ISS from RD1 and
hence lowering Vout1. Since
, the drain current
of M2 decreases and Vout2 rises. As shown in Figure 3(a), for Vin1 = Vin2,
we have
. As Vin1 becomes more positive
than Vin2, M1 carries a greater current than does M2 and Vout1 drops
belowVout2. For sufficiently large Vin1 - Vin2, M1 "hogs" all of ISS,
turning M2 off. As a result,
and
.
Figure 3 also plots
versus
.
Figure 3.Input-output characteristics of a differential Pair
The foregoing analysis reveals two important attributes of the
differential pair. First, the maximum and minimum levels at the output
are well-defined and independent of the input CM level. Second, the
small-signal gain is maximum for Vin1 = Vin2, gradually falling to zero as
|Vin1 - Vin2| increases. In other words, the circuit becomes more nonlinear as the input voltage swing increases. For Vin1 = Vin2, we say that
the circuit is in equilibrium.
Now it us consider the common-mode behavior of the circuit. As
mentioned earlier, the role of the tail current source is to suppress the
effect of input CM level variations on the operation of M1 and M2 and
the output level. Does this mean that Vin,CM can assume arbitrarily low
or high values? To answer this question, we set Vin1=Vin2=Vin,CM and
vary Vin,CM from 0 to VDD. Figure 4(a) shows the circuit
with ISS implemented by an NFET. Note that the symmetry of the pair
requires that Vout1=Mout2
Figure 4.(a)Differential pair sensing an input common-mode change
(b)equivalent circuit if M3 operates in deep triode region (c)commonmode input-output characteristics
What happens if Vin,CM=0? Since the gate potential of M1 and M2 is not
more positive than their source potential, both devices are off,
yielding ID3 = 0. This indicates that M3 is in deep triode region
because Vb is high enough to create an inversion layer in the transistor.
With ID1=ID2 = 0, the circuit is incapable of signal amplification,
and Vout1=Vout2=VDD. Now suppose Vin,CM becomes more positive.
Modelling M3 by a resistor as in Figure 4(b), we note
that M1 and M2 turn
on
ifVin,CM VTH.
Beyond
this
point, ID1 and ID2 continue to increase and VP also rises. In a
sense, M1 and M2 constitute a source follower, forcing VP to trackVin,CM.
For
a
sufficiently
high Vin,CM,
the
drain-source
voltage
of M3 exceeds VGS3-VTH3, allowing the device to operate in saturation.
The total current through M1and M2 then remains constant. We
conclude that for proper operation Vin,CM VGS1+ (VGS3-VTH3).
What happens if Vin,CM rises further? Since Vout1 and Vout2 are relatively
constant,
expect
that M1 and M2 enter
the
triode
region
if Vin,CM > Vout1 + VTH = VDD-RDISS/2 + VTH. This sets an upper limit on the
input CM level. In summary, the allowable value of Vin,CM is bounded as
follows:
.
With our understanding of differential and common-mode behavior of
the differential pair, we can now answer another important question:
How large can the output voltage swings of a differential pair be? As
illustrated in Figure 5, for M1 and M2 to be saturated, each output can
go as high as VDD but as low as approximatelyVin,CM-VTH. In other words,
the higher the input CM level, the smaller the allowable output swings.
For this reason, it is desirable to choose a relatively low Vin,CM, but the
preceding stage may not provide such a level easily. An interesting
trade-off exists in the circuit of Figure 5 between the maximum value
of Vin,CM and the differential gain. Similar to a simple common-source
stage the gain of a differential pair is a function of the dc drop across
the load resistors. Thus, if RDISS/2 is large, Vin,CM must remain close to
ground potential.
Figure 5.Maximum allowable output swings in a differential pair
Quantitative Analysis
We now quantify the behavior of MOS differential pair as a function of
the input differential voltage. We begin with the large-signal analysis to
arrive at an expression for the plots shown in Figure 3.
Figure 6.Differential pair
For the differential pair in figure 6, we have Vout1 = VDD RD1ID1 and Vout2 = VDD - RD2ID2, i.e., Vout1 - Vout2 = RD2ID2 - RD1ID1 = RD(ID2 ID1) ifRD1=RD2=RD.Thus, we simply calculate ID2 and ID2 in terms
of Vin1 and Vin2, assuming the circuit is symmetric, M1 and M2 are
saturated, and
. Since the voltage at node P is equal to Vin1 VGS1 and Vin2-VGS2.
..............(1).
For a square-law device, we have:
...............(2)
and, therefore,
..............(3)
It follows from (1) and (2) that
................(4)
Our objective is to calculate the differential output current, ID1 - ID2.
Squaring the two sides of (4) and recognizing that ID1 + D2 = ISS, we
obtain
..............(5)
That is,
.............(6)
Squaring the two sides again and noting that 4ID1ID2 = (ID1 + ID2)2 - (ID1 2
2
2
D2) = ISS - (ID1 - ID2) , we arrive at
...............(7)
Thus,
.............(8)
As expected, ID1-ID2 is an odd function of Vin1 - Vin2, falling to zero
for Vin1 = Vin2. As |Vin1 - Vin2| increases from zero , |ID1 - ID2| also
increases because the factor preceding the square root rises more
rapidly than the argument in the square root drops.
Before examining (8) further, it is instructive to calculate the slope of
the characteristic i.e. the equivalent Gm of M1 and M2. Denoting ID1 ID2 and Vin1 - Vin2 by
and
, respectively, the reader can show
that.
...............(9)
For
. Moreover,
since
, we can write the small-signal
differential voltage gain of the circuit in the equilibrium condition as
................(10)
Equation (9) also suggests that Gm falls to zero
for
..........(11)
As we will see below, this value of
plays an important role in
operation of the circuit. Let us now examine Equation (8) more closely.
It appears that the argument in the square root drops to zero
for
, implying that
crosses zero at two
different values of
. This was not predicted in our qualitative
analysis in Figure 3. This conclusion, however, is incorrect. To
understand why, recall that (8) was derived with the assumption that
both M1 and M2 are on. In reality, as
exceeds a limit, one
transistor carries the entire ISS, turning off the other. Denoting this
value by
, we have
and
because M2 is nearly off. It follows that
............(12)
For
is off and (8) does not hold. As mentioned
above, Gm falls to zero for
. Figure 7 plots the behavior.
Figure 7. Variation of drain currents and overall transconductance of a
differential pair versus input voltage
The value of
given by (12) in essence represents the maximum
differential input that the circuit can "handle". It is possible to
relate
to the overdrive voltage of M1 and M2 in equilibrium. For a
zero differential input,
, and hence
.............(13)
Thus, the equilibrium overdrive is equal to
. The point is that
increasing
to make the circuit more linear inevitably increases the
overdrive voltage of M1 and M2. For a given ISS, this is accomplished
only by reducing W/L and hence the transconductance of the
transistors.
SMALL SIGNAL ANALYSIS
In the above figure, assuming M1 and M2 are saturated, Applying small
signals Vin1 and Vin2 to the two inputs,
To arrive at some result, we proceed by small signal analysis.
Assume RD1 = RD2 = RD
As the circuit is driven by two independent signals, The output will be a
reult of superposition of these two signal.
Set Vin2 = 0 an find the effect of Vin1 at X and Y. M1 forms a commonsource stage with a degeneration resistance equal to the impedance
seen looking into the source M2. Neglecting channel-length and body
effect,
Therefore,
To calculate VY , replace M1 by a thevnin equivalent circuit, where
thevnn voltage VT = Vin1 and thevnin resistance RT = 1/gm1 as shown in
figure below.
With M2 operating as a common gate stage, we get gain equal to
For gm1 = gm2 = gm , we get
Similarly
On superposition, we have Differential gain equal to
If the output is single ended i.e the output is sensed between X or Y and
ground, so the differential gain is halved.
Common Mode Response
Introduction
An important attribute of differential amplifiers is their ability to
suppress the effect of common mode perturbations. In reality, neither
is the circuit fully symmetric nor does the current source exhibits an
infinite output impedance. As a result, a fraction of the input CM
variation appears at the output.
Symmetric Circuit
Assuming that circuit is symmetric but the current source has finite
output impedance,RSS[Figure 1(a)]. As Vin,CM changes, so does VP,
thereby increasing the drain currents of M1 and M2 and lowering
both VX and VY. Owing to the symmetry, VX remains equal to VY and, as
depicted in Figure 1(b), the two nodes can be shorted together.
Since M1 and M2 are now "in parallel", i.e. they share all of their
respective terminals, the circuit can be reduced to that in Figure 1(c).
Note that the compound device, M1 + M2, has twice the width and the
bias current of each of M1 and M2 and, therefore twice their
transconductance. The CM gain of the circuit is thus equal to
.............(1)
.............(2)
where gm denotes the transconductance of each
of M1 and M2 and
.
In a symmetric circuit, input Cm variations disturb the bias points,
altering the small-signal gain and possibly limiting the output voltage
swings.
Figure 1. (a) Differential pair sensing CM input, (b) simplified version of
(a),(c) equivalent circuit of (b)
The foregoing discussion indicates thatthe finite output impedance of
the tail current source results in some common-mode gain in a
symmetric differential pair. Nonetheless, this is usually a minor
concern. More troublesome is the variation of the differential output as
a result of a change in Vin,CM an effect that occurs because in reality the
circuit is not fully symmetric, i.e., the two sides suffer from slight mis-
matches during manufacturing. For example in Figure 1(a) RD1 may not
be exactly equal to RD2.
Asymmetric Circuit
If circuit is asymmetric and the tail current source suffers from a finite
output impedance the effect of input common mode variation is
different from symmetric case. Suppose as shown in Figure
2. RD1 = RD and
, where
denotes a small
mismatch and the circuit is otherwise symmetric. What happens
to VX and VY as Vin,CM increases? Since M1 and M2 are
identical, ID1 and ID2 increase by
,
but VX and VYchange by different amounts:
............(3)
............(4)
Figure 2. Common mode response in the presence of resistor mismatch
Thus, a common-mode change at the input introduces a differential
component at the output. We say the circuit exhibits common-mode to
differential conversion. This is a critical problem because if the input of
a differential pair includes both a differential signal and common mode
noise the circuit corrupts the amplified differential signal by the input
CM change. The effect is illustrated in Figure 3.
Figure 3. Effect of CM noise in the presence of resistor mismatch
Nut shell
The common-mode response of the differential pairs depends on the
output impedance of the tail current source and asymmetries in the
circuit, manifesting itself through two effects: variation of the output
CM level ( in symmetric case) and conversion of the input commonmode variations to differential components at the output. In analog
circuits, the latter effect is much more severe than the former. For this
reason, the common-mode response should usually be studied with
mismatches taken into account
Significance
We make two observations. First, as the frequency of the CM
disturbance increases, the total capacitance shunting the tail current
source introduces larger tail current variations. Thus, even if the output
resistance of the current source is high, common-mode to differential
conversion becomes significant at high frequencies. Shown in Figure 4,
this capacitance arises from the parasitics of the current source itself as
well as the source-bulk junctions of M1 and M2. Second, the asymmetry
in the circuit stems from both the load resistors and the input
transistors, the latter contributing a typically much greater mismatch.
Figure 4. CM response with the finite tail capacitance
Figure 5(a) Differential pair sensing CM input (b) equivalent citcuit of (a)
Let us now study the asymmetry resulting from mismatches
between M1 and M2 in Figure 5(a). Owing to dimension and threshold
voltage mismatches, the two transistors carry slightly different currents
and exhibit unequal transconductances. To calculate the gain
from Vin,CM to X and Y, we use the equivalent circuit in Figure 5(b),
writing ID1 = gm1(Vin,CM-VP) and ID2=gm2(Vin,CM-VP). That is,
........(5)
and
..............(6)
We now obtain the output voltages as
..............(7)
and
..............(8)
The differential component at the output is therefore given by
..............(9)
In other words, the circuit converts input CM variations to a differential
error by a factor equal to
..............(10)
where
denotes common-mode to differential-mode
conversion and
. For meaningful comparison of
differential circuits, the undesirable differential component produced
by CM variations must be normalized to the wanted differential output
resulting from amplification. We define "common-mode rejection
ratio"(CMRR) as
..............(11)
Differential Pair with MOS loads
The load of a differential pair need not be implemented by linear
resistors. Differential pairs can employ diode-connected or currentsource loads (Figure 1). The small-signal differential gain can be derived
using the half circuit concept. For Figure 1(a),
....................(1)
where subscripts N and P denote NMOS and PMOS, respectively.
Expressing gmN and gmP in terms of device dimensions, we have
.....................(2)
For Figure 1(b) we have
....................(3)
In the circuit of Figure 1(a), the diode-connected loads consume voltage
headroom, thus creating a trade-off between the output voltage
swings, the voltage gain, and the input CM range. To achieve a higher
gain
must decrease, thereby increasing
and
lowering the CM level at nodes X andY.
Figure 1. Differential pair with (a) diode-connected and (b) currentsource loads
In order to alleviate the above difficulty, part of bias currents of the
input transistors can be provided by PMOS current sources. Illustrated
in Figure 2, the idea is to lower the gm of the load devices by reducing
their current rather than their aspect ratio. For example, if M5 and M6
carry 80% of the drain current of M1 and M2, thr current through M3
and M4 is reduced by a factor of five. For a given
, this
translates to a factor of five reduction in transconductance M3 and M4
because the aspect ratio of the devices can be lowered by same factor.
Thus, the differential gain is now approximately five times that of the
case with no PMOS current sources.
Figure 2.Addition of current sources to increase the voltage gain
The small-signal gain of the differential pair with current-source loads is
relatively low -- in the range of 10 to 20 in submicron technologies.
How do we increase the voltage gain? We increase the output
impedance of both PMOS and NMOS devices by cascoding, in essence
creating a differential version of the cascode stafe. The result is
depicted in Figure 3(a). To calculate the gain, we construct a half circuit
of Figure 3(b).
Figure 3(a) Cascode differential pair (b) half circuit of (a)
Thus,
............(4)
Cascoding therefore increases the differential gain substantially but at
the cost of consuming more voltage headroom.
As a final note, we should mention that high gain fully differential
amplifiers require a means of defining the output common-mode level.
For example, in Figure 1(b), the output common-mode level is not well-
defined whereas in Figure 1(a), diode-connected transistors define the
output CM level as
.