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Proceedings
of the 37th Annual EDS/CAS
Activities in
Western New York Conference
November 13, 2013
Louise Slaughter Hall
Center for Integrated Manufacturing Studies
Rochester Institute of Technology
Rochester, NY
37th Annual EDS/CAS
Activities in Western New York Conference
November 13, 2013
IEEE Electron Devices Society
Rochester, NY
http://www.rit.edu/kgcoe/eme/EDSWNY
The IEEE Electron Devices Society (EDS) is involved in the advancement of electronics and
electrical engineering through research, development, design, manufacture, materials, technology
and applications of electron devices. The field of interest for EDS is all aspects of the physics,
theory and phenomena of electron devices such as elemental and compound semiconductor
devices, quantum effect devices, optical devices, displays and imaging devices, photovoltaics,
solid-state sensors and actuators, solid-state power devices, high frequency devices,
micromechanics, tubes and other vacuum devices. EDS is concerned with technical, educational,
scientific publication and meeting activities, which provide benefits to members while
contributing towards the progress of this field.
The Rochester EDS chapter has been highly effective in introducing a variety of successful
technical programs and activities. Our EDS chapter supports several activities each year,
including the annual IEEE Electron Devices Activities in Western New York Conference. We
also interact with other professional organizations such as the Materials Research Society and the
Society for Information Display. If you are interested in joining EDS, please contact one of the
Rochester IEEE EDS officers.
Thank you for coming to our annual conference - enjoy the presentations!
Karl D. Hirschman, Ph.D.
Rochester IEEE EDS Society, Conference Chair
Micron Professor of Microelectronic Engineering
Rochester Institute of Technology
37th EDS/CAS
Activities in Western New York Conference
Wednesday Nov 13th, 2013
Louise Slaughter Hall, Rooms 2210-2220
Rochester Institute of Technology
Agenda
12:30PM
Conference Registration
1:00PM
Conference kick-off – EDS Announcements
1:05PM
(Invited) “Thin-film Electronics by Spatial ALD” Shelby F. Nelson,
Carolyn Ellinger and Lee Tutt, Eastman Kodak Company, Rochester,
NY
1:50
“Raman Spectroscopy Studies of III-V Stacks: A Non-destructive
Approach for Examining Charge Carrier Density and Crystal Quality
in III-V Semiconductors” Kenneth R. Kort and Sarbajit Banerjee,
Department of Chemistry, University at Buffalo, Buffalo, NY
2:15
“Analysis of Thermal Paths in 3-D Structures” Boris Vaisband and
Eby G. Friedman, Department of Electrical and
Engineering, University of Rochester, Rochester, NY
Computer
2:45-3:15
Coffee Break / Poster Setup
3:20
(Invited) “Functional Printing of Devices and Materials” Denis
Cormier, Department of Industrial and Systems Engineering, RIT
4:05
“High aspect ratio micropillar arrays for studying nanoscale cellular
traction forces”
Eyup Cinar, Ferat Sahin and Jiandi Wan,
Microsystems Engineering Department, RIT
4:30
Poster “NanoFlash” Session
4:50 – 6:15PM
Poster Session / Reception
Thin-film Electronics by Spatial ALD
Shelby F. Nelson, Carolyn Ellinger, and Lee Tutt
Eastman Kodak Company
1999 Lake Ave
Rochester, NY 14650-2102
Abstract:
In this talk we describe our approach to thin-film electronics using spatial atomic layer
deposition (SALD). ALD has long been known for producing dense conformal films of
conductors, insulators, and semiconducting layers from a limited set of precursors. However, in
the more common vacuum- and chamber-based ALD processes, the deposition speed has
generally been limited. In contrast, the SALD deposition process can be relatively fast. The
coating takes place at atmospheric pressure in a localized region of a coating head, with no
enclosure except that produced by gas isolation curtains, and thus without any pumping cycles.
Focusing on the field of metal oxide semiconductor thin-film transistors (TFTs), we have
demonstrated that SALD produces high quality planar thin film transistors. TFTs with aluminum
oxide for the insulator and zinc oxide (ZnO) for the semiconductor have high on/off ratios, and
good uniformity of the deposited layers for deposition temperatures at and below 200°C. We
show that the regime of fast ALD cycles accessible by SALD produces particularly good
performance.
Patterning and alignment of transistors on flexible substrates can present a challenge, especially
for short channel lengths. We have investigated novel vertical device architectures enabled by
the conformal nature of SALD deposition that unite high performance with generous alignment
and resolution requirements. With self-aligned sub-micron channel lengths, these devices
demonstrate remarkable current-carrying capability at low voltage.
Finally, we will present a “patterned-by-printing" technique for SALD-grown transistors. By
printing an inhibitor ink on the surface, the growth of aluminum-doped ZnO (conductor),
aluminum oxide (insulator), and ZnO (semiconductor) can be limited to selected areas of the
substrate. The process produces TFTs with the same excellent performance as lithographically
patterned TFTs, with high yield, and rapid throughput.
In summary, we will present a range of opportunities in the area of thin-film and “printed”
electronics that are enabled by spatial ALD.
Bio:
Shelby F. Nelson is a Senior Research Scientist in the Aligned Technology Center at Eastman
Kodak Company. She joined the company in 2001, where she has worked primarily on thin-film
electronics. She received the Ph.D. degree from Cornell University in Applied Physics. Since
then she has worked on silicon/germanium heterostructures at IBM’s Thomas J. Watson
Research Center, been the Clare Booth Luce Assistant/Associate Professor of Physics at Colby
College, and worked at Xerox Corporation as a semiconductor device physicist modeling power
transistors in a mixed-signal CMOS process for ink-jet ejector heads.
Raman Spectroscopy Studies of III-V Stacks: A Non-destructive Approach for Examining Charge
Carrier Density and Crystal Quality in III-V Semiconductors
Kenneth R. Kort and Sarbajit Banerjee
Department of Chemistry, University at Buffalo
The State University of New York, Buffalo, NY
Abstract:
The incorporation of dopants within III-V semiconductors with precise control of areal and depth profiles
represents a significant challenge for the fabrication of aggressively density- and gate-length-scaled
device architectures. Sulfur monolayer doping has emerged as a particularly facile approach for areaselective doping of III—V semiconductors, and has the added advantage of being agnostic to channel
geometries, thereby allowing for selective doping of multi-gate 3D field-effect transistors and the
stabilization of ultra-shallow junctions. Techniques such as secondary ion mass spectrometry allow for
determination of dopant depth profiles but do not permit evaluation of dopant activation. Fortuitously, the
free carrier density within doped III-V semiconductors couples strongly to optical phonons rendering
Raman spectroscopy an excellent contactless and non-destructive probe of dopant activation and the free
electron density. Here, we present a Raman spectroscopy study of electron—phonon coupling in
In0.53Ga0.47As epilayers doped via the sulfur monolayer doping method. The evolution of the Raman
spectra of S-doped In0.53Ga0.47As epilayers has been studied as a function of annealing temperature. Sulfur
monolayer doping is observed to create a plasmon (analogous to doping of In 0.53Ga0.47As by Si using
conventional ion implantation) that couples to the longitudinal optic modes of In0.53Ga0.47As. A highfrequency coupled mode (HFCM) is detected above 400 cm-1 and is strongly divergent with charge carrier
density. The peak positions of this mode allow for extraction of the activated dopant concentration in
these samples. Two other modes, the intermediate-frequency coupled mode (IFCM) and low-frequency
coupled mode (LFCM) are observed to atypically shift to lower frequencies with increasing dopant
activation.
InAslike LO
GaAslike LO
3.0
Intensity (a.u.)
2.5
Undoped
ADM
2.0
Sulfur doped
1.5
IFCM
LFCM
1.0
0.0
HFCM
Silicon doped
0.5
ADM
//
200 250 200
300 250
350 900
400 1000
300
350 1100
400 1200 1300
-1
-1
Raman Shift (cm )
-1
Bio:
Kenneth R. Kort is currently a PhD student in the Department of Chemistry at the University at Buffalo,
The State University of New York. Kenneth received his B.S. in Chemistry from the University at
Buffalo in 2008 and continued on at the University at Buffalo for his graduate work. His research interests
are focused on the synthesis, characterization, and spectroscopic studies of two-dimensional rare-earth
oxychloride and InGaAs thin films. In 2011 Kenneth was selected as a National Science Foundation East
Asia Pacific Summer Institute (EAPSI) fellow, which allowed him to spend the summer at Pusan
National University in Busan, South Korea. Most recently Kenneth has just been named as one of the
Spring 2014 recipients of the National Academies Christine Mirzayan Science and Technology Policy
Graduate Fellowship.
Analysis of Thermal Paths in 3-D Structures
Boris Vaisband and Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester
Rochester, New York 14627
{bvaisban, friedman}@ece.rochester.edu
Two important issues in modern ICs are heterogeneity and global signaling. Coupling between
different circuits has increased with greater on-chip integration. A natural solution is to use a 3-D
structure, where each layer is fabricated separately, and all of the layers are stacked to form a
heterogeneous system. However, as the vertical dimension becomes blocked by additional stacked
layers, the heat is not as easily transferred towards the heat sink as in 2-D circuits. With higher
temperature, the mobility of the charge carriers decreases, which consequently slows the circuit. An
important issue is therefore identifying thermal paths within a 3-D integrated system.
The thermal resistance per unit length is a useful metric to characterize the thermal behavior of
the horizontal and vertical paths. Results from a 3-D structure, modeled using the HotSpot simulator, as
well as experimental results from a fabricated test vehicle, are shown in Figure 1. The thermal resistance
per unit length of the vertical path is two orders of magnitude larger than the thermal resistance of the
horizontal path, since SiO2 exhibits two to three orders of magnitude lower thermal conductivity than
silicon. The dependence of the thermal conductivity on temperature is also analyzed in this work. A
comparison among the constant thermal conductivity, temperature dependent thermal conductivity,
and experimental results is shown in Figure 1 for two paths. The results based on a constant thermal
conductivity deviate from experimental measurements by up to 25% and 36% for, respectively, the
vertical and horizontal paths, while the results based on a temperature dependent thermal conductivity
only deviate by 13% and 12% for the same paths.
Heat propagation in the vertical dimension is shown to be poor; the heat primarily passes along
the horizontal dimension. Vertical heat removal paths are therefore needed to reduce degradations in
performance caused by thermal gradients. This analysis confirms the importance of accurately modeling
the thermal conductivity, and integrating accurate thermal conductivity models into the thermal analysis
process.
(a)
(b)
Figure 1: Thermal resistance per unit length of (a) a vertical path, and (b) a horizontal path within the 3-D structure.
Functional Printing of Devices and Materials
Denis Cormier
Earl W. Brinkman Professor
Rochester Institute of Technology
Industrial and Systems Engineering
Rochester, NY 14623-5603
Ph: 585-475-2713
Web: www.heterofoam.com
Abstract:
Color printing processes that deposit multiple inks or toners have been in existence for decades.
Inkjet printers, for example, employ color inks consisting of solid pigments that are suspended in
a liquid vehicle. In recent years, researchers have begun to replace color pigments with nano and
micron-scale particles. The aim is to print functional materials and 3D micro/meso-scale devices
rather than documents. RFID tags, GPS antennas, and photovoltaic current collectors are now
routinely produced by printing conducting inks onto planar substrates. More recent process
developments have allowed researchers to spatially vary the printed material composition and to
print materials on non-planar substrates. This talk will start with an overview of direct-write
technologies currently available to print materials and devices. The talk will then discuss how
multi-material printing systems are being used to produce heterogeneous materials with spatially
tailored mechanical, thermal, and electrical properties. Recent developments in low temperature
pulsed photonic sintering will also be discussed.
Bio:
Dr. Denis Cormier is the Earl W. Brinkman Professor of Industrial and Systems Engineering at
the Rochester Institute of Technology. His teaching and research interests focus on additive
manufacturing (commonly known as 3D printing) for synthesis of novel materials and geometric
structures. His research has led to several key commercially implemented process enhancements
in the electron beam melting (EBM) metal additive process. Prior to joining RIT in 2009, he was
a professor at North Carolina State University for 15 years. He is a founding member of ASTM’s
F-42 additive manufacturing standards group, and he also serves on the Society of
Manufacturing Engineer’s Rapid Technologies and Additive Manufacturing steering committee.
He received SME’s Outstanding Young Manufacturing Engineering award in 2003.
High aspect ratio micropillar arrays for studying
nanoscale cellular traction forces
Eyup Cinar, Ferat Sahin, Jiandi Wan
Microsystems Engineering Department
Rochester Institute of Technology, Rochester, NY
Abstract:
High aspect ratio (HAR) micropillar arrays have received considerable attention because of their
wide potential applications. The unique properties that come with these structures such as large
surface area, small mechanical stiffness and a well separated topography from its substrate have led
to many interesting applications. These include dry adhesive surfaces, superhydrophobic selfcleaning surfaces, micromechanical sensors and actuators.
In this study, we fundamentally focus on mechanical characterization of HAR micropillar arrays
microfabricated out of an elastomer material called polydimethlsiloxane (PDMS). The polymeric
HAR micropillar arrays are aimed to be used as a mechanosensor in order to measure nanonewton
scale cellular traction forces for studying cancer metastasis (spread of cancer). When these structures
are used as a mechanical sensor, their mechanical properties (e.g. effective Young’s modulus) should
be thoroughly characterized and specific force and displacement curves should be accurately
obtained. In this regard, we utilize a multi-probe nanoindentation tool which enables us to measure
effective Young’s modulus in a unique way as compared to previous studies in the literature. The
results will be used to verify the accuracy of currently available mechanical models in representing
the small scale deflection of micropillar structures. The verified mathematical models will help with
analyzing the cellular traction forces of cancer cells during metastasis.
a)
b)
Fig 1. Microfabricated HAR pillar structures 5 µm diameter and 20µm height a)
COMSOL® FEM simulation results after 20 nN lateral force is applied on the top of the
micropillar b) Incubated HCT116 Colorectal cancer cells and deflection of micropillar arrays
before and after 12 hours. Scale bars are 25 µm
A Low Voltage Input Self-startup DC/DC Converter for On Chip
Thermoelectric Energy Harvesting
Mo Yang
University of Rochester, Department of Electrical and Engineering
Thermoelectric generators (TEG) are used to convert thermal energy to electrical energy
in order to power circuits on chip. However, due to the unpredictability of the heat
absorbed, the voltage generated by TEGs is very unstable and small. An efficient step-up
DC/DC converter is needed to convert the unstable and small input voltage (tens of
millivolts) into stable DC voltage that is high enough to power circuits on chip. In this
poster, a novel boost converter with low input voltage is presented to achieve self-startup.
In addition, maximum power point tracking (MPPT) technique is applied to extract the
maximum power from TEGs.
CMOS Compatible 3-Axis Hall Effect Magnetic Field Sensor
Joshua Locke and Dr. Lynn Fuller
Electrical & Microelectronic Engineering Department
Rochester Institute of Technology
Abstract:
The purpose of this study is to design, fabricate and test a CMOS compatible 3-axis Hall Effect
sensor capable of detecting the earthʼs magnetic field, with strengthʼs of ~50 μT. Preliminary
testing of N-well Van Der Pauw structures using strong neodymium magnets showed proof of
concept for hall voltage sensing. A 1-axis Hall Effect sensor was designed, fabricated and tested
with a sensitivity of 1.12x10-3 mV/Gauss. An offset voltage of 0.1238 volts prevented sensing of
the earthʼs magnetic field. A new design has been created that includes a second axis of sensing
and expected smaller offset. Fabrication of the new design is in progress.
Improving the Energy Efficiency of traditional DVFS Design
ZHE WEN
ECE Dept., University of Rochester, Rochester, NY 14627
[email protected]
Abstract:
To deal with the increasing on-chip density and reliability concerns, the technique of dynamic
voltage and frequency scaling (DVFS) is adopted in energy-constrained design. However,
conventional design usually traps the embedded devices in a low-power mode during the most
part of the lifetime, and causes a significant overhead when not in performance mode. When
the performance constrains are relaxed, the supply voltage is reduced to achieve a better
energy efficiency, thanks to the dependence of both static and dynamic power on supply
voltage(CV2f). In this work, we studied different aspects of traditional design techniques and
propose new ones to improve the performance and achieve better energy efficiency.
Porphyrin Self-Assembled Monolayers as Copper Diffusion Barrier
Anthony Aiello1, Scott Williams2 and Santosh Kurinec1
1
Electrical and Microelectronic Engineering
School of Chemistry and Materials Science
Rochester Institute of Technology
2
Abstract:
Copper diffusion into the silicon bulk is a detrimental obstacle to advanced-CMOS and
nanotechnology processes that seek to incorporate copper into the metallization steps because of
its deep-level trap nature to carriers. Recent studies have hinted that a metallated porphyrin selfassembled monolayer (SAM) could be a method of prevention to copper diffusion. The selfassembly of non-metallated tetrakis (hydroxyphenyl) porphyrins over silicon and silicon nitride
substrates (planar and textured) has been examined using atomic-force microscopy (AFM) and
spectrophotometry. Preliminary AFM results suggest a formation of a self-assembled layer.
However, further analysis is required to investigate its orientation and uniformity.
Spectrophotometry revealed that the SAM had a negligible impact on the reflectance when
compared with reflectance data from the original substrate, which can be beneficial in
developing copper metallization for solar cells.
Turn–key Silicon Solar Cell Process Expedites Investigation of
Copper Metallization for Photovoltaics
Mihir Bohra, Karine Florent, Michael Jackson and Santosh Kurinec
Electrical & Microelectronics Engineering
Rochester Institute of Technology
Abstract
Single-Crystal Silicon Solar Cell panels have not only reached the $1/Watt cost goal cited for
years as the benchmark of economic viability for photovoltaics (PV) to compete with
conventional electric energy sources, they have surpassed it. With current market prices in the
$0.60 – 0.70/W range, almost all other forms of PV technology are challenged to remain cost
competitive. In addition, this low cost factor now opens the possibility of incorporating
moderately more expensive IC processing practices into PV manufacturing in the hopes of
raising cell and module efficiencies from the current 16-20% range into the 20-22% range, while
maintaining power costs below $1/W. To facilitate the rapid investigation and development of
novel PV manufacturing processes, RIT has developed a simplified, turn-key silicon solar cell
process to act as the venue for such studies.
In this paper, the turn-key process will be reviewed, results for a prior study involving a back
surface field will be presented to illustrate the utility of this approach, and a proposed study on
Cu metallization will be introduced. Cu metallization for PV applications holds promise in terms
of sustainability and cost effectiveness. However, a diffusion barrier to copper is required to
preserve lifetime of the silicon. Nickel serves as a diffusion barrier; however, studies have shown
that Cu can diffuse through the commonly used antireflection coating (SiO2/Si3N4/Si) stack.
Efforts are underway to investigate amorphous ternary nitrides like WNx, HfNx and TaN as Cu
diffusion barriers. With the in-house developed turn-key process, qualification of PVD Cu as
front metal grid on the solar cell will be performed and compared with the industrial solar cells.
After PVD Cu, collaboration with IntrinsiQ Materials, located in Rochester, NY, will focus on
printing of copper inks as front-side metal interconnects, further reducing metallization
costs. This work is supported by NSF I/UCRC Silicon Solar Consortium (SiSoC).
Field-Enhanced STT-MRAM Switching
for Reduced Write Latency and Energy
Ravi Patel, Engin Ipek, and Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester
Spin torque transfer magnetoresistive RAM (STT-MRAM) is a modern CMOS compatible memory
technology with the promise of becoming the mainstream on-chip memory. Key features of STT-MRAM
are non-volatility, no static power consumption, and unlimited write endurance. A key issue constraining
the use of STT-MRAM, however, is the switching latency of the magnetic tunnel junction (MTJ) within
each memory cell. The long latency causes the switching energy of an MTJ to be much greater than
traditional CMOS SRAM.
To address these issues, the classic first generation MRAM cell topology is utilized with an STT-MTJ
where an additional field current destabilizes the MTJ prior to switching, thereby reducing the switching
latency. As illustrated in Fig. 1a, classical MRAM cells utilize two large orthogonal currents to generate
magnetic fields within the MTJ located at the intersection of the metal lines. These fields are sufficiently
strong to induce a torque on the magnetization, which induces a reversal in the device state. In modern
spin torque transfer MTJs, the internal ferromagnetic layers generate a torque on the magnetization by
passing a current through the device. STT-MTJs can be switched using a smaller current applied directly
to each cell, allowing many MTJs to be written in parallel, as shown in Fig 1b. By leveraging both the
STT effect and a current induced magnetic field, in the manner shown in Fig 1c, the write latency for a
single MTJ can be reduced. Moreover, the additional field current is amortized over many cells within a
row, leading to a significant reduction in energy per bit.
An MRAM array model is presented to determine the switching energy and maximum achievable
reduction in energy using the field driven approach and constraints on the memory system size. MTJ
switching is evaluated via the Landau–Lifshitz–Gilbert (LLG) expression in conjunction with a
macrospin approximated free layer to determine the effect of the applied field on the write latency. The
switching latency per bit is reduced by more than a factor of ten. The resultant switching energy per bit is
reduced by 82% as compared to standard STT-MRAM.
Fig. 1 Current biasing scheme for a) classical MRAM, b) standard STT-MRAM, and c) the proposed STT-MRAM
Benchmarking Heterojunction vs. Homojunction Esaki Tunnel Diodes
RIT : Paul Thomas, David Pawlik, Brian Romanczyk, Matthew Filmer, Abhinav Gaur, Sean Rommel
SEMATECH : Man-Hoi Wong, Wei-Yip Loh, Kausik Majumdar, Chris Hobbs, Paul Kirsch
Texas State University : Ravi Droopad
Tunneling Field Effect Transistors are increasingly a subject of study due to potentially
superior performance relative to standard CMOS transistors with respect to switching efficiency
[1, 2]. However, the ideal material system for this replacement technology is not presently well
defined as the maximum current densities, JP for tunneling systems are unknown. It has also
been estimated that a 10 MA/cm2 JP will be necessary to provide appropriate drive current for
scaled devices. This authors aim to address this void through the design, fabrication, and
testing of multiple Esaki tunneling devices with varied tunneling barriers and potential TFET
candidate materials as shown in Figure 1 a and b. By varying effective tunnel barrier heights
and degenerate doping levels for the tunnel junctions the authors aim to light a path for
focused research into materials appropriate for exceeding Si CMOS performance at future
technology nodes.
Figure 1. a. Alignment of band gaps for heterojunction systems utilized in this work. b. Range of
effective tunnel barrier heights due to the semiconductors chosen for this work.
[1]
[2]
G. Dewey, B. Chu-Kung, J. Boardman, J. M. Fastenau, J. Kavalieros, R. Kotlyar, et al., "Fabrication,
characterization, and physics of III-V heterojunction tunneling field effect transistors (H-TFET) for
steep sub-threshold swing," in 2011 IEEE International Electron Devices Meeting, IEDM 2011,
December 5, 2011 - December 7, 2011, Washington, DC, United states, 2011, pp. 33.6.1-33.6.4.
G. Dewey, B. Chu-Kung, R. Kotlyar, M. Metz, N. Mukherjee, and M. Radosavljevic, "III-V field
effect transistors for future ultra-low power applications," in 2012 IEEE Symposium on VLSI
Technology, 12-14 June 2012, Piscataway, NJ, USA, 2012, pp. 45-6.
Power Efficiency of 14 nm MCML
Near Threshold Circuits
Alexander Shapiro and Eby G. Friedman
Department of Electrical Engineering
University of Rochester
Rochester, New York 14627
Abstract—Near threshold circuits (NTC) are an attractive and
promising technology that provides significant power savings
with some delay penalty. The feasibility of NTC technology
with MOS Current Mode Logic (MCML) based on a 14 nm
FinFET process is examined in this work. A 32 bit Kogge Stone
adder is chosen as a demonstration vehicle for simulation and
feasibility analysis. MCML is shown to yield enhanced power
efficiency when operated with a 100% activity factor above 1
GHz as compared to CMOS. Standard CMOS does not achieve
frequencies above 9 GHz without a dramatic increase in power
consumption. MCML is most efficient beyond 9 GHz over a wide
range of activity factors. MCML also exhibits significantly lower
noise levels as compared to standard CMOS. The results of the
analysis demonstrate that pairing NTC and MCML is efficient
when operating at high frequencies and activity factors.
Fig. 1. Power vs maximum frequency of MCML and standard CMOS for
activity factors of 100%, 20%, and 10%
I. I NTRODUCTION
Near threshold circuits (NTC) consume an order of magnitude less power than circuits operating under nominal voltages
while not suffering from the significant delay penalty found in
subthreshold circuits. NTC has therefore become an attractive
methodology for sub-30 nm CMOS circuits [1]. In this work,
NTC [2] is paired with MOS Current Mode Logic (MCML)
to compensate for the vulnerable aspects of each technology.
MCML is a differential circuit topology driven by a constant
tail current. The lack of switching transients contributes to a
low noise environment as compared to standard CMOS. The
low noise environment is particularly beneficial for NTC due
to the low voltage operation.
TABLE I
C OMPARISON OF NOISE IN CMOS AND MCML CIRCUITS
II. S IMULATION RESULTS
The simulations are based on 14 nm low power FinFET
predictive technology models [3]. A standard threshold voltage
of Vth = 350 mV is assumed. The supply voltage is set to
400 mV to operate near the threshold voltage with an MCML
input/output voltage swing of 100 mV. A 32 bit Kogge Stone
adder is evaluated in both standard CMOS and MCML.
III. C ONCLUSIONS
The combination of NTC and MCML exploits the advantages of each technology [4]. Unlike standard CMOS, MCML
circuits operating near the threshold voltage perform better at
higher frequencies and higher activity factors. Unlike standard
CMOS, 14 nm MCML circuits operating near the threshold
voltage can achieve high operating frequencies and power
efficiencies at frequencies above 9 GHz.
R EFERENCES
[1] S. Jain et al., “A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor
in 32nm CMOS,” Proceedings of the IEEE Solid-State Circuits Conference, pp. 66–68, February 2012.
[2] H. Kaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, and
S. Borkar, “Near-Threshold Voltage (NTV) Design: Opportunities and
Challenges,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 1149–1154, June 2012.
[3] Y. K. Cao, “Predictive Technology Models,” June 2012. http://ptm.asu.
edu/.
[4] A. Shapiro and E. G. Friedman, “Performance Characteristics of 14
nm Near Threshold MCML Circuits,” Proceedings of the IEEE S3S
Conference, pp. 79–80, October 2013.
Annealing Conditions for Improved Stability of High Performance IGZO TFTs
N. Walsh, T. Mudgal, and K.D. Hirschman
Electrical & Microelectronic Engineering Department
Rochester Institute of Technology, Rochester, New York, 14623, USA
R.G. Manley
Corning Incorporated, Science and Technology
Corning, New York 14870, USA
Abstract:
Traditionally flat panel displays were developed using amorphous silicon thin-film transistor (TFT)
backplanes. As flat panel and display technology has progressed, a new and improved material is sought.
Oxide semiconductors are a strong candidate because they can be deposited on large glass panels, as well
as flexible materials due to a low deposition temperature. Indium-Gallium-Zinc-Oxide (IGZO) proved to
be an attractive oxide semiconductor because it exhibits high electron mobility and is optically transparent
over a broad range of wavelengths. However, the stability of IGZO TFTs is an issue which is hindering
their acceptance into the display market.
This work involves the development of IGZO devices fabricated and tested at RIT. The devices made are
sputter-deposited IGZO for bottom-gate and double-gate TFTs. The potential advantages of a double-gate
TFT are higher current drive and improved off-state, and the initial bottom-gate design makes it
straightforward to implement this option. TFTs were fabricated using IGZO material sputtered at both
RIT and Corning, with different process parameters due to very different machine configurations. It was
soon realized that the Corning process yielded superior device performance, which then became the sole
source for further study. The annealing ambient was investigated, which included both oxidizing ambient
(O2 & air) and presumably inert ambient (H2/N2 forming gas, N2 & vacuum) conditions. Initial
characterization has found that nitrogen annealing results in bottom-gate IGZO TFTs with superior
electrical stability, compared to other annealing ambient conditions, when left unpassivated. These TFTs
have demonstrated a subthreshold swing (SS) of ~ 160mV/dec and electron mobility of ~10 cm2/V∙sec, as
shown below. An investigation on passivation materials is currently in progress.
ID (A)
ID2
Sqrt(Id-sat)
0.009
1.E-04
0.008
1.E-05
0.007
1.E-06
0.006
1.E-07
0.005
1.E-08
0.004
1.E-09
0.003
1.E-10
0.002
1.E-11
0.001
Sqrt(IDsat) (A.5)
ID
1.E-03
0
1.E-12
-5
0
5
10
VG (V)
Transfer characteristics of an IGZO TFT with L=24 µm & W=100 µm. Y1 axis for subthreshold with
drain at 0.1 V and 10 V, showing SS ~ 160 mV/dec. Y2 axis for sqrt(I Dsat) showing a VT ~ 0.5 V.
Electroforming Backside Contacts for Solar Cells
Wilkie Olin-Ammentorp and Santosh Kurinec
Electrical and Microelectronic Engineering
Rochester Institute of Technology
Abstract:
Localized ohmic contacts to heavily doped regions on the back side in silicon solar cells
are preferred to minimize the contact resistance while keeping the back surface
recombination velocity low. However, this method is not used in the mainstream
production of solar cells as it requires a separate lithography step adding to the processing
cost. In this work, an electroforming method is proposed that can be used to create selfaligned point contacts without the use of lithography. This method is based on the hard
dielectric breakdown on heavily doped regions resulting in formation of ohmic contacts
without affecting the low doped regions where dielectric/silicon interface passivation is
preserved. A test chip has been designed to demonstrate the process for aluminum
contacts to P-type silicon with different dielectric layers. Heavily doped P+ regions are
created by ion implantation to emulate the laser doping process used in conventional solar
cell production. Electrical results for electroformed contacts through passivating materials
such as PECVD oxide, thermal oxide, and silicon nitride have been obtained.
Crystalization of Amorphous Silicon and Dopant Activation using
Xenon Flash-Lamp Annealing
C. Reepmeyer, T. Mudgal, D. Cormier and K. D. Hirschman
Electrical & Microelectronic Enigneering Department
Industrial & Systems Engineering Department
Rochester Institute of Technology, Rochester, New York, 14623, USA
R. G. Manley
Corning Incorporated, Science and Technology
Corning, New York 14870, USA
November 12, 2013
Abstract
Low temperature polysilicon (LTPS) is commonly used in thin film transistors (TFTs) where
the substrate cannot withstand high temperature processing. Excimer laser annealing (ELA)
is typically used for crystalizing polysilicon and for dopant activation, but it cannot be extended to larger substrates like gen8 or larger display glass. Flash lamp annealing (FLA) can
achieve similar results to ELA and can provide additional process integration and enable larger
substrates.
A Novacentrix Pulseforge 3300 flash lamp system was used for these FLA experiments. This
tool uses a broad-spectrum xenon flash lamp to achieve very high intensities (up to 20 kW/cm2 )
for very short exposure times (as short as 30 µs). These conditions enable annealing the silicon
thin film without damaging temperature-sensitive substrates like glass or plastic.
Using the Pulseforge system, an experiment was performed to determine the optimal conditions for crystalizing amorphous silicon into polycrystaline silicon. The ideal conditions, within
the limitations of the machine, were 490 V for 270 µs, giving an intensity of 19 kW/cm2 and an
exposure energy of 5.01 J/cm2 . Raman spectroscopy was used to quantify the crystalization of
the silicon film.
This FLA treatment was used to crystalize the silicon layer in a bottom gate/double gate
transistor experiment. It was found that the extreme conditions of the FLA caused the metal
bottom gate to break, resulting in open gates.
To avoid the issue with the bottom gate, an FLA experiment was carried out with top gate
transistors. Transistors that received FLA treatment did not perform as well as the standard
furnace-anneal solid-phase crystallization process.
Another application of flash lamp is to activate dopants after implant. Boron and phosphorous were implated into silicon then the samples were exposed to FLA. The degree of dopant
activation was characterized using the resistivity of the sample after annealing.
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