Download Design Procedure for Compact Asymmetric SPDT Switches

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INTERNATIONAL JOURNAL OF MICROWAVE AND OPTICAL TECHNOLOGY,
VOL.9, NO.1, JANUARY 2014
Design Procedure for Compact Asymmetric SPDT Switches
and Full X-Band Demonstrator
Mirko Palomba*, Riccardo Cleriti, Sergio Colangeli and Ernesto Limiti
Università degli Studi di Roma “Tor Vergata”, Via del Politecnico, 1, 00133, Rome (IT)
Tel: +39-0672597343; E-mail: [email protected]
Abstract – A design procedure for asymmetric
SPDT switches is proposed and validated by a
MMIC demonstrator covering the full X-Band,
well suited to integration in T/R modules. The
demonstrator exhibits 0.7 dB and 1.6 dB insertion
loss along its TX and RX paths, respectively, and
21.5 dB isolation in TX mode. Chip size is as
compact as 1  1 mm2.
Index Terms – asymmetric SPDT, compact MMIC,
SPDT switch design, X-band.
I. INTRODUCTION
In the past, the best way to separate transceivers’
TX and RX chains consisted in using ferrite
circulators, thanks to their low insertion loss and
high isolation. Unfortunately these bulky and
heavy devices could not be integrated. Therefore,
an increasing interest in replacing ferrite
circulators with FET-based circulators or
switches resulted, thus leading to small,
lightweight systems. However, although active
circulators represent a valid improvement, they
are typically larger than simple switches;
furthermore, in particular cases (e.g., T/R
modules) signal circulation along TX or RX path
is mutually exclusive, and therefore an SPDT
switch solution is sufficient.
Several satellite systems for Earth Observation
operate around 9.6 GHz, and it is therefore
interesting to investigate switches operating in
the X-Band. Contributions in open literature use
particular techniques to null parasitic effects.
Resonating two shunt FETs [1] results in 0.6 dB
insertion loss and 17 dB isolation at 10 GHz. The
resulting circuit is 0.675  1.15 mm2 but the
performance results to be narrowband since
isolation rapidly degrades with frequency.
Another available technique is presented in [2, 3]
by resonating FET in series connection instead of
shunt devices. This approach leads again to
narrowband
behavior,
but
multi-octave
performance on a single series resonated FET are
achievable by introducing a resistor on the
resonating arm [4]. A study about single gate
FET SPDTs can be found in [5], highlighting the
possibilities underlying FET resonant techniques.
In this case, 0.7 dB insertion loss and 28 dB
isolation was reached by a 0.76  1.78 mm2 chip.
Also in this case, the circuit exhibits a
narrowband behavior. In fact, at 0.9 GHz from
central frequency, isolation drops down to 20 dB.
A deep study about the relationship between
FET’s physical parameters and its quality factor
is presented in [6]: according to this study, the
best isolation for a single-throw-single-pole
(SPST) switch, with 1 dB insertion loss, is
50.7 dB. A power switch with 10 W capability is
reported in [7]: this circuit exhibits 1 dB insertion
loss and 26 dB isolation for a 4.5  3.7 mm2 chip.
The bandwidth is 2 GHz around 9.5 GHz. A very
small circuit is described in [8], with only
0.3  0.5 mm2 chip size, by developing the
dielectric overhang gate process to reduce the
distance between source and drain electrodes of
the multiple-gate HEMTs used for the switch.
Good performance is registered at 900 MHz but
they rapidly degrade to 1 dB insertion loss and
16 dB isolation at 2.7 GHz. A high-power SPDT
switch with selectively anodized aluminum
substrate is reported in [9], exhibiting 1.3 dB
insertion loss and 20.3 dB isolation in a 1 GHz
bandwidth around 9.5 GHz; chip size is in a
4.4  3.1 mm2. A quarter-wave PIN switch
architecture used for T/R modules is presented in
[10], providing better bandwidth performance
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INTERNATIONAL JOURNAL OF MICROWAVE AND OPTICAL TECHNOLOGY,
VOL.9, NO.1, JANUARY 2014
and small chip area occupation. Circuit behavior
is asymmetric in this case. In the present
contribution, the latter architecture has been
considered and analytically studied. A design
procedure is then proposed to properly select
devices and obtain target performance. A
monolithic circuit demonstrator is provided to
assess the methodology effectiveness.
II. THEORETICAL ANALYSIS
FET T/R switch reference architecture is visible
in Fig.1. Z1 represents L1 and the FET on the
same branch, while Y2 includes the second FET
and L2. The quarter-wavelength transformer has
50 Ω characteristic impedance.
Fig.1 can be rearranged as in Fig.2:
Fig.2. Rearrangement of the T/R switch scheme.
To gather S31, the product of 3 ABCD chain
matrixes can be computed:
 1
S31   1

 Z 0  Z1

0  0
 j
1 
  Z 0
j  Z0 
 1
0  Y2

0

1 
[4]
 j  2  ( Z 0  Z1 )
2  Z 0  Y2  Z 0  Y2  Y1  3  Z 0  2  Z1
2
In the same way, S21 is:
0
1 Z1  
S21  
 j
0 1   Z
 0
Fig.1. FET T/R switch reference architecture.
Terminating the switch ports (P1, P2 and P3) with
Z0 (normalizing impedance, typically 50 Ohm)
the network S-parameter description can be
derived, resulting in:
S11 
Z0  ( Z1Y2  1)
[1]
2  Z0  Y2  Z0  Y2  Y1  3  Z0  2  Z1
2
in which Y1 = 1/Z1, and
S22 
Z0  ( Z1Y2  1)  2  Z1
[2]
2
2  Z0  Y2  Z0  Y2  Y1  3  Z0  2  Z1
S33 
 Z0  ( Z1  2  Z 0  Z 2 )
[3]
3  Z0  Z 2  2  Z 2  Z1  2  Z0 2  Z0  Z1

j  Z0  
1 
  1 Y  Y  
0
2
 [5]
0  
1 
 0
 j  2  Z 0  (1  Y2  Z 0 )
2  Z 0 2  Y2  Z 0  Y2  Y1  3  Z 0  2  Z1
and S32:
 0 j  Z0 
1 Z1  
   1 0 
S32  
 j


 Y2 1 
0
0 1   Z

 0
 j  2  Z0

2
2  Z 0  Y2  Z 0  Y2  Y1  3  Z 0  2  Z1
[6]
By reciprocity, the complete S-matrix can be
filled. Impedance Z1 in the previous expressions
may or may not include L1: such series
inductance can be used in some cases to
compensate the effects of the FET parasitic
capacitance at high frequencies; on the other
hand, L2 is used to resonate the COFF of the
second FET, so its value is fixed to
IJMOT-2014-1-541 © 2014 IAMOT
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INTERNATIONAL JOURNAL OF MICROWAVE AND OPTICAL TECHNOLOGY,
VOL.9, NO.1, JANUARY 2014
L2 = 1/(COFF2∙ω02), ω0 being the central angular
frequency.
Derived expressions are independent on the
particular model used to represent FETs in its ON
and OFF states. To gather Z1 and Y2, a simplified
FET model can be used for X-Band applications.
In fact, a FET operating in its ohmic region can
be modeled by a RON resistor only; in the other
condition (pinch-off), it can be simply modeled
by a COFF capacitor, as shown in Fig.3 (a).
Parameters RON and COFF can be simply extracted
by means of a very simple test circuit such as the
one in Fig.3 (b).
and the whole S-matrix is expressed as a function
of RON1 and RON2, by which the FETs peripheries
can be easily sized, for instance by means of
design charts such as the ones depicted in Figs.45. For brevity, transmission parameters between
ports 1-2, 1-3 (Fig.4-5) only are here shown (at
9.6 GHz).
Using the so-obtained parameters RON and COFF
allows to specify the previously derived
equations. In particular, since the control voltage
is unique, two cases need to be considered,
namely with both FETs simultaneously ON or
OFF.
Fig.4. S21 design chart for FETs ON (top) and OFF
(bottom) states.
Fig.3. (a) Simplified FET’s model. (b) Reference
circuit for RON and COFF extraction.
Hence, all expressions computed above become
functions of RON1, COFF1 and RON2, considering
that COFF2 is resonated by L2.
Finally, it is to note that the mathematical
analysis can be further simplified by introducing
two technology-dependent parameters, namely
rON and cOFF, such that RON = rON/P and
COFF = cOFF∙P, where P is the device periphery
(N∙W). This yields:
COFF 
cOFF  rON
RON
[7]
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INTERNATIONAL JOURNAL OF MICROWAVE AND OPTICAL TECHNOLOGY,
VOL.9, NO.1, JANUARY 2014
Fig.6. Layout of the demonstrator switch.
Fig.5. S31 design chart for FETs ON (top) and OFF
(bottom) states.
III. FULL X-BAND DEMONSTRATOR
To design a full X-Band demonstrator, OMMIC’s
D01MH process has been selected, providing
depletion metamorphic HEMTs with 0.13 µm
gate
length.
For
this
technology,
rON = 1.04 Ω∙mm and cOFF = 450 pF/mm.
The resulting performance is plotted in Fig.7.
Port match in non-reflective operation is 15 dB
over the whole X-Band (8-12 GHz). Insertion
losses are 0.7 dB and 1.6 dB in the branch 1-3
and 1-2, respectively. This suggests that path 1-3
be chosen for the RX mode; in such case, a better
isolation is also obtained in TX mode between
ports 2 and 3, namely 21.5 dB at 9.6 GHz, and
over 20.5 dB over the whole X-Band. These
results well agree at center frequency with the
behavior predicted by the simplified analysis in
Section II.
By considering all the design charts, RON1 = 10 Ω
and RON2 = 3 Ω were chosen, from which the
FET peripheries can be determined (P = rON/RON).
The final switch layout, with size 1  1 mm2, is
depicted in Fig.6. A semi-lumped quarter-wave
line has been used to reduce the circuit insertion
loss.
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INTERNATIONAL JOURNAL OF MICROWAVE AND OPTICAL TECHNOLOGY,
VOL.9, NO.1, JANUARY 2014
Fig. 7. Switch performance.
[10]
substrate”, Electronics Letters, Vol 46: pp. 16271629, Nov. 2010.
R. Cory, D. Fryklund, “Solid State RF/Microwave
Switch Technology: Part 2” MPD Microwave
Product Digest, pp. 34-66, Jun. 2009.
IV. CONCLUSIONS
A design method for single control-voltage,
compact, asymmetric switches has been proposed.
A step-by-step procedure was outlined guiding
the designer to obtain the best performance that a
certain process technology can provide. A
compact SPDT switch has been designed to
demonstrate the methodology here discussed,
exhibiting performance in close agreement with
the theoretical analysis.
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[2]
[3]
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