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International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 1, January 2015
PERFORMANCE &COMPARISION WITH
HIGH SPEED OF DOUBLE CARRY
CHAIN ADDERS USING DOMINO LOGIC
A.Bharathi, M.Manikandan,R.Geetha,R.Malar

Abstract— This paper presents the Manchester carry chain
adder (MCC) with high speed,reduced delay and size within a
small chip with different technologies of length L=16nm.The
main objective is to reduce the delay and increase the
performance of the system in HSPICE Tool.To increase the
speed of the operation by operation the carry chain by using
independent double carry chain adders in parallel and thus
reduces the delay of the operations.
Index Terms—Manchester carry chain adders,domino logic,
Addition, Carry-Look ahead Adder (CLA), High Performance,
CMOS technology, HSPICE TOOL
less surface area, but are more difficult to design. Dynamic
logic has the capacitive loads are smaller so the overall power
consumption of dynamic logic may be higher or lower
depending on various tradeoffs. To design a high speed and
efficient Manchester Carry Chain Adders suitable for VLSI
processor applications.Manchester carry chain adder presents
a efficient implementation of multi-output domino CMOS
logic. The use of the proposed 8-bit adder as the basic block,
instead of the 4-bit MCC adder, can lead to high-speed adder
implementations.This proposed method analysis with
different technologies and results are observed using HSPICE
tool.
2.RELATED WORK
“ANALYSIS WITH HIGH SPEED MULTIOUTPUT
256-BIT MANCHESTER CARRY CHAIN ADDERS”
I. INTRODUCTION
ADDITION is the most commonly used in
arithmetic operation and also the speed-limiting element to
make faster VLSI processors. The objective of Computer
Arithmetic is to develop appropriate algorithms that are
utilizing available hardware in the most efficient way.
Definetely, speed, power and chip area are the most often
usually measured. Dynamic gates are faster than static gates
despite the extra fet in the pull down path because of the
reduction in self-loading and the limitation of the pull up
short-circuit current during the first part of the output
transition. Dynamic gates cannot be cascaded. In integrated
circuit design, dynamic logic is a design methodology in
combinatory logic circuits, implemented in MOS technology.
It is demonstrated from static logic by exploiting temporary
storage of information in stray and gate capacitances. It was
popular in a recent resurgence in the design of high speed
digital electronics, particularly computer CPUs. Dynamic
logic circuits are usually faster than static logic, and require
Manuscript received April, 2015.
A.Bharathi,ECE
Department
IFET
College
of
engineering,[email protected]). City Name, Country Name,
Phone/ Mobile M.Manikandan ECE Department, IFET College of
engineering, City Name, Country Name, Phone/ Mobile No., (e-mail:
[email protected]).
Third Author name, His Department Name, University/ College/
Organization Name, City Name, Country Name, Phone/ Mobile No.,
(e-mail: [email protected]).
In this paper presents the carry look-ahead adders in domino
circuits for faster requirement of the VLSI processors or
digital signal processors. The Manchester carry chain adder
(MCC) is the most popular dynamic (domino) CLA, is
proposed with an implementation in VLSI. The MCC have
enabled the development of multi-output domino gates which
have given area and speed improvement with respect to single
output. The efficiency of the MCC is trying to transfer its
structure to static logic. In a report has been made of dynamic
CMOS 4-bit CLA adder in multi-output logic which reduces
the number of transistors which considered to a conventional
schema. However, the simulation results shown any speed
improvement but reduce delay is been analyzed and compared
with different technologies having an supply voltage of
VDD=1.2V and 1V is defined.
The performance of the domino logic circuits of an 256-bit
CLA adder has the generate and propagate signal of AND or
XOR gates.When CLK is low, dynamic node is precharged
high and buffer inverter output is 0. NMOS in the next logic
block will be off condition. When CLK goes high, dynamic
node is conditionally discharged and the output will
conditionally go high. Since discharge can only happen once,
buffer output can only make one low-to-high transition. Like
dominos, once the internal node in a gate falls, it stays fallen
until it is “picked up” by the precharge phase of the next cycle.
Thus many gates may evaluate in one evaluate cycle. charge
sharing between nodes in the pull down network and the
dynamic node can unintentionally reduce the voltage of the
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ISSN: 2278 – 7798
All Rights Reserved © 2015 IJSETR
International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 1, January 2015
dynamic node enough to switch output buffer .The addition of
the output inverter makes domino gates non-inverting. One
can often design around this limitation, but some circuits
cannot be implemented solely. In existing literature, 256-bit
CLA & MCC adder circuit was designed using domino
logic.To make the domino circuits more robust and with low
leakage without significant performance degradation.Thus,
increased power consumption and delay was reduced.The
performance of the system has been increased.
3.CIRCUIT DESIGN
In Fig1,For the circuit design of present work has been
designed by the generate signal (g) for the new generate signal
(G) is represented by the equation as
Gi=gi+gi-1
Fig.3 schematic diagram for new propagate signal(Pi)
Fig.1 schematic diagram for new generate signal(Gi)
Figure 1 shows the implementation of generate
signal in domino logic. The circuit will possesses generally
two state precharge state and evaluation state. If the clock
signal goes to value ‘0’, then the circuit will enter into
precharge state and PMOS will get connected to ground and
output will maintain the value of 0. If the clock makes the
transition from 0 to 1 then the circuit will enter into evaluation
state and the output depends on the input value. Since
generate signal possess AND operation if both input are
maintained at 1, 1 then the output gi will be maintained at 1
else the output value will be maintained at 0 i.e gi=0.
Fig.3 shows When CLK is low, evaluate nfet is off
and precharge PMOS is on output node is precharged to
VDD, other nodes may precharge to VDD - Vth, depending
on values of inputs .When CLK goes, high evaluate nfet is on
and precharge PMOS is off output node may be discharged if
inputs have configured a conducting path to GND, otherwise
output node stays charged high. inputs must be stable before
CLK goes high because once output has been discharged it
won’t go high again until next cycle for same reason,
noise/glitches on inputs cannot exceed nfet threshold, a much
more stringent requirement than for static CMOS gates.
To determine whether a bit pair will propagate a
carry, either of the following logic statements work:
Pi=Ai xor Bi
Pi=pi*pi-1*ti-2
The layout diagram has been drawn using microwind tool has
shown below
The layout diagram has been describing about inputs
signal and output signal in a easier manner,the new generate
signal Gi =1,gi=0.The input signal depends on the clock
signal in the domino circiut.
Fig.4 layout diagram for propagate XOR signal
Fig.2 layout diagram for AND signal
In this paper mainly focus on reducing delay when
temperature increases from 25oc to 70 oc. when the
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ISSN: 2278 – 7798
All Rights Reserved © 2015 IJSETR
International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 1, January 2015
temperature increases power dissipation will occur, it may be
a static power or dynamic power. so, power consumed for the
circuit in the system is less. The system performance gets
reduced accordingly.
4. PROPOSED WORK
The Manchester Carry-Chain Adder is a chain of
pass-transistors that are used to implement the carry chain.
During precharge, all intermediate nodes are charged to Vdd.
During the evaluation phase, Cout_k is discharged if there is
an incoming carry Cin0 and the previous propagate signals
(P0...Pk-1) are high. Only 4 diffusion capacitances are present
at each node, but the distributed RC-nature of the chain results
in a delay that is quadratic with the number of bits. Transistor
sizing was performed to improve performance of the system.
The groups of even and odd new carries can be computed in
parallel by different carry chains in multi-output domino
CMOS logic.The new double carry chain adders are 1. Even
carry chain adder 2. Odd carry chain adders . The Manchester
carry chain was designed using dynamic logic and implements
the following logical function:
Coi=Gi+PiCoi−1
Fig 5 schematic diagram of votage vs temperature
In this paper three types of technologies with an
adders circuit are presented with L=0.12μm technology and
with a supply voltage of 1.2V. These high performance
domino styles improve the scalability of multiple bit domino
logic adders. Using these methods it is possible to implement
the adder circuits with a transistor gate length of L=22nm
,l=16nm along with a supply voltage of 0.8V,0.7V. These
adder circuits are superior in performance compared to
conventional static logic adders. These adder circuits
minimize the chip area, minimize the leakage power, and
improve the noise tolerance without much speed degradation.
Also the delay between the gates is now reduced to the order
of pico seconds. These types of domino logic circuits can be
used in high performance microprocessors.By considering
this below, comparing these technologies with static and
dynamic(domino) gates .Delay in nano seconds
Technique
90nm
65nm
22nm
Static CLA
2.7096 ns
2.3285 ns
2.0125 ns
Dynamic
CLA
2.9969 ns
2.9022 ns
2.0624 ns
MCC
1.9992 ns
1.9022 ns
1.8223 ns
5.SIMULATION RESULTS
The simulations were performed using L=0.12μm
technology along with the supply voltage VDD=1.2V. In this
paper a 256-bit adder is constructed using three different
domino technologies such as 90nm,65nm,22nm,16nm .This
adder circuit has the area overhead of an extra NMOS
transistor which is connected to the keeper from the
dynamic(domino) circuit. This adder circuit has much better
noise margin, low leakage current and low power
consumption compared to the adder circuits designed
L=16nm using domino logic styles with traditional feedback
keepers. The adder circuit designed using manchester carry
chain adder domino logic is used but it consumes some
additional power due to the transistors count has been
increased. The following simulation result is
Table1:comparision with technology and sum delay
Technique
90NM
65NM
22NM
Static CLA
3.9421 ns
3.6405 ns
3.0750 ns
Dynamic
CLA
2.9033 ns
2.9022 ns
2.8864 ns
MCC
1.9035 ns
1.9623 ns
1.8222 ns
Fig.7 simulation diagram of voltage vs time
Table2:comparision with technology and carry delay
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ISSN: 2278 – 7798
All Rights Reserved © 2015 IJSETR
International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 1, January 2015
Fig.8 simulation diagram of generate and propagate signal
16BIT
399.049
391.426
12.117
32BIT
240.32
234.568
16.156
64BIT
211.15
201.71
20.195
128BIT
199.45
198.852
24.234
256BIT
182.23
182.21
28.273
Table.3 comparison of sum delay,carry delay,and power
4.CONCLUSION
In this paper the performance of 256-bit adder circuit
is designed and analysed using in dynamic (domino) circuit
techniques is analyzed in detail and its performance is
compared with static adder circuits. The 256-bit adder circuit
is simulated using L=22nm,16nm technology along with
supply voltage VDD=0.7V,0.8V. The experimental results
shows that these adder circuits gives superior performance
compared to adder circuits designed using conventional
domino techniques and reduced the power dissipation of the
circuit has been analysed. Further, Manchester carry chain
adder is used as double carry chain adders for increasing high
speed and reduced delay in the domino circuit.
REFERENCES
Fig .9 comparison of temperature vs sum ,carry, power graph
The delay graph is plotted with rest to number of bits
and the gate length is L=22nm technology. In this graph
explain the proposed Manchester carry chain adder based
domino circuit has less delay but it will increase to increase
number of bits for many applications.
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