Download MOS Gate Dielectric Technology: Part 2

MOS Gate Dielectrics
Outline
•Scaling issues
•Technology
•Reliability of SiO2
•Nitrided SiO2
•High k dielectrics
araswat
tanford University
42
EE311 / Gate Dielectric
Incorporation of N or F at the Si/SiO2
Interface
Incorporating nitrogen or fluorine instead of hydrogen strengthens the
Si/SiO2 interface and increases the gate dielectric lifetime because Si-F and
Si-N bonds are stronger than Si-H bonds.
Nitroxides
Poly-Si Gate
Oxide
Si substrate
araswat
tanford University
N or F
– Nitridation of SiO2 by NH3 , N2O, NO
– Growth in N2O
– Improvement in reliability
– Barrier to dopant penetration from poly-Si gate
– Marginal increase in K
– Used extensively
Fluorination
– Fluorination of SiO2 by F ion implantation
– Improvement in reliability
– Increases B penetration from P+ poly-Si gate
– Reduces K
– Not used intentionally
– Can occur during processing (WF6 , BF2)
43
EE311 / Gate Dielectric
1
Nitridation of SiO2 in NH3
H
• Oxidation in O2 to grow SiO2 .
• RTP anneal in NH3 maximize N at the interface and minimize bulk incorporation.
• Reoxidation in O2 remove excess nitrogen from the outer surface
• Anneal in Ar remove excess hydrogen from the bulk
• Process too complex
araswat
tanford University
44
EE311 / Gate Dielectric
Nitridation in N2O or NO
Profile of N in SiO2
Stress-time dependence of gm degradation of a NMOS
SiO2
(Ref: Ahn, et.al., IEEE Electron Dev. Lett. Feb . 1992)
Ref. Bhat et.al IEEE IEDM 1994
•The problem of H can be circumvented by replacing NH3 by N2O or NO
araswat
tanford University
45
EE311 / Gate Dielectric
2
Oxidation of Si in N2O
N2O → N 2 + O
N2O + O → 2NO
Ref: Okada, et.al., A p p l. Phys. Lett. 63(2), 1993
•RTP oxidation shows N accumulation near the Si/SiO2 interface
•Furnace oxidation shows almost uniform N profile ⇒lower Qbd
araswat
tanford University
46
EE311 / Gate Dielectric
Dopant Penetration From Poly-Si Gate
Thick gate oxide
P+
Poly-Si Gate
B
Thin gate oxide
Thin nitrided gate oxide
B
B
B in SiO2
Si
SiOXNY
Si
Si
• Incorporation of nitrogen at the interface suppresses dopant diffusion
from gate poly-Si into the channel which can can cause VT shift.
• The problem is more serious for P+ poly-Si as boron diffuses more
readily in SiO2.
• It is desirable to use P+ gate for PMOS transistors, for scaled CMOS
technology to minimize short channel effects
araswat
tanford University
47
EE311 / Gate Dielectric
3
MOS Gate Dielectrics
Outline
•Scaling issues
•Technology
•Reliability of SiO2
•Nitrided SiO2
•High k dielectrics
araswat
tanford University
48
EE311 / Gate Dielectric
High-k MOS Gate Dielectrics
Ichannel ∝ charge x source injection velocity
∝ (gate oxide cap x gate overdrive) vinj
∝ Cox (VGS - VT) Esource µinj
Historically Cox has been increased by decreasing gate oxide
thickness. It can also be increased by using a higher K dielectric
ID " Cox "
K
thickness
40 Å
20 Å SiO2 K ≈ 4
!
Si3N4 K ≈ 8
Si
Higher thickness -> reduced gate leakage
araswat
tanford University
49
J DT " e#t ox
EE311 / Gate Dielectric
!
4
Benefits of High-κ
High-κ Gate Dielectrics
VDD
Low
leakage
VDD
κ=4
source
Gate
High
leakage
Gate
15 Å SiO2 e
e- drain
channel
Si substrate
κ = 16
e- 60 Å High-κ
VDD
J DT " e ! tox
e- drain
source
VDD
channel
Si substrate
Higher-κ film ⇒ thicker gate dielectric ⇒ lower leakage and
power dissipation with
the same capacitance
C ox =
!" 0 A
t ox
⇒
' ) high ()
t high () = %
% ) SiO
2
&
$
" ! t SiO
2
"
#
Historically Cox has been increased by decreasing gate oxide
thickness. It can also be increased by using a higher K dielectric
araswat
tanford University
50
EE311 / Gate Dielectric
Alternatives to SiO2: Silicon Nitride
(Ref: Guo & Ma, IEEE Electron Dev. Lett. June. 1998)
 A factor of 2 increase in K
 Reduction in bandgap ⇒ increased gate leakage
araswat
tanford University
51
EE311 / Gate Dielectric
5
Nitridation of Silicon
Thermal Nitridation of Si in NH3
Drain Current (mA)
Id - Vg of 1.5 µm Si3N4 gate NMOS
25 Å Si3N 4
Vg = 2V
1.5V
1V
0.5V
Drain Voltage (V)
(Ref: Moslehi & Saraswat, EEE Trans. Electron Dev. Feb. 1985)
• Si reacts with NH3 to grow Si3N4
– Excellent gate dielectric properties
– Reaction needs very high temperatures
• Si reacts with atomic nitrogen
– Reaction temperature could be reduced using nitrogen plasma
– More research needed
• Several deposition methods under investigations, e.g., rapid thermal CVD,
jet vapor deposition (JVD)
araswat
tanford University
52
EE311 / Gate Dielectric
Nitride / Nitroxide Sandwich Gate MOS
Id
1.2 nm EOT
Gate dielectric
Ig
Ref: Q. Xiang, et.al., (AMD), IEDM 2000
1.2 nm EOT
• 1.2 nm EOT (Equivalent oxide thickness)
gate dielectric can be formed by
- thermally growing ultrathin oxinitride
- CVD of Si3N4
• Low gate leakage
• 40 nm channel length CMOS
demonstrated
Ref: M. Bohr, (Intel), IEDM 2002.
araswat
tanford University
53
EE311 / Gate Dielectric
6
Requirements for the MOS gate dielectrics
• High dielectric constant ⇒ higher charge induced in the channel
• Wide band gap ⇒ higher barriers ⇒ lower leakage
• Ability to grow high purity films on Si with a clean interface.
• High resistivity and breakdown voltage.
• Low bulk and interfacial trap densities.
• Compatibility with the substrate and top electrode.
• minimal interdiffusion and reaction
• minimal silicon reoxidation during growth and device processing
- even a thin SiO2 layer would deteriorate the Cgate significantly.
• Thermal stresses — most oxides have larger thermal expansion
coefficients than Si.
• Good Si fabrication processing compatibility.
• Stability at higher processing temperatures and environments
• Ability to be cleaned, etched, etc.
araswat
tanford University
54
EE311 / Gate Dielectric
Candidates for High K Gate Dielectrics
Dielectric Permittivity
SiO2
Si3N4
Al2O3
TiO2
Ta2O5
Y2O3
La2O3
HfO2
ZrO2
ZrSiO4
HfSiO4
3.9
7
9
80
26
15
30
25
25
15
15
Band Gap
(eV)
9
5.3
8.8
3.5
4.4
6
6
6
5.8
6
6
!EC to Si
3.5
2.4
2.8
0
0.3
2.3
2.3
1.5
1.4
1.5
-
Ref : Rober tson, J., Appl. Sur f . Sci. (2002) 190 (1-4), 2
• Higher K materials have lower bandgap
• There are many performance, reliability and process integration issues
yet to be solved
• More research is needed to make these materials manufacturable
araswat
tanford University
55
EE311 / Gate Dielectric
7
Thermodynamic Stability of
High-K Dielectric Oxides
100 Å
75 Å K ≈ 20
K ≈ 20
10 Å Si3N 4
• Unstable oxides (e.g. TiO2, Ta2O5, BST)
– React with Si to form SiO2 and silicides upon thermal annealing
– Barrier (e.g. Si3 N 4) is required to prevent such a reaction
• Dielectric stack: poly-Si/nitride/unstable oxide/nitride/Si substrate
• A monolayer of nitride on both sides of gate dielectric already contributes 5 Å to
the physical oxide thickness
• Stable oxides (e.g. HfO2, ZrO2, Al2O3) and their silicates (e.g. ZrSixOy) and
aluminates (e.g. ZrAlxOy)
– Do not react with Si upon thermal annealing (up to 1000°C)
– May not require a barrier layer between Si and the metal oxide
• simple structure: poly-Si/stable oxide/Si substrate
araswat
tanford University
56
EE311 / Gate Dielectric
Stability of Metal Oxides with Si
After Beyers,J. Appl. Phys. 56, 157, 1984
And Wang and Meyer J. Appl. Phys. 64, 4711 , 1988
araswat
tanford University
57
EE311 / Gate Dielectric
8
Capacitance and Leakage for High-k Gate
Dielectric Films Grown Using ALCVD
Gate Leakage (A/cm2)
m
1
c
/
V
±
AB
(F
@
)e
2
g
a
k
a
e
L
10
10
-2
10
-4
10
-6
10
-8
10
Germanium
Silicon
0
Gate Current@ VFB+1V (A/cm2)
V
SiO2
2.5 nm
ALCVD
ZrO2
4 nm
-10
0
0.05
0.1
1/C
'
ox
0.15
0.2
2
(µm /fF)
Equivalent SiO2 Thickness (nm)
Perkins, Saraswat and McIntyre,
Stanford Univ.
Univ. 2002
araswat
tanford University
Chui, Kim, Saraswat and McIntyre,
Stanford Univ.
Univ. 2004
58
EE311 / Gate Dielectric
Atomic Layer CVD of Hi-κ Dielectric
Rotary Pump
Pump
ZrCl4
MFC
Loadlock
MFC
MFC
MFC
H2 O
HfCl4
Turbo Pump
Main Chamber
Throttle Valve
Turbo Pump
Carrier Gas (N2)
araswat
tanford University
Scrubber Rotary Pump
McIntyre, Saraswat, Stanford
59
EE311 / Gate Dielectric
9
Atomic Layer Deposition
ZrCl4/HfCl4 (g)
Substrate
ON
Reactant A
(ZrCl4/HfCl4)
Reactant B
(H2O)
araswat
tanford University
OFF
1 cycle
1/4 cycle :
Injection of reactant A
(ZrCl4/HfCl4)
Time (sec)
60
EE311 / Gate Dielectric
Atomic Layer Deposition
Zr " OH * + ZrCl4 # Zr " O " ZrCl3 + HCl !
Saturated adsorption
Substrate
ON
Reactant A
(ZrCl4/HfCl4)
Reactant B
(H2O)
araswat
tanford University
2/4 cycle :
Purging (N2)
OFF
1 cycle
Time (sec)
61
EE311 / Gate Dielectric
10
Atomic Layer Deposition
HCl (g)
H2O (g)
Substrate
ON
Reactant A
(ZrCl4/HfCl4)
Reactant B
(H2O)
araswat
tanford University
OFF
1 cycle
3/4 cycle :
Injection of reactant B
(H2O)
Time (sec)
62
EE311 / Gate Dielectric
Atomic Layer Deposition
Zr " Cl * + H 2O # Zr " OH * + HCl !
ZrO2/HfO2 (s)
Substrate
ON
Reactant A
(ZrCl4/HfCl4)
Reactant B
(H2O)
araswat
tanford University
4/4 cycle :
Purging (N2)
OFF
1 cycle
Time (sec)
63
EE311 / Gate Dielectric
11
Atomic Layer Deposition
ZrCl4 /HfCl4 (g)
Saturated adsorption
Substrate
Substrate
HCl (g)
H2O (g)
ZrO2/HfO2 (s)
Substrate
Substrate
- Surface saturation controlled process
- Layer-by-layer deposition process
- Excellent film quality and step coverage
araswat
tanford University
64
EE311 / Gate Dielectric
Microstructure of ALD HfO2 and HfO2
ZrO2=29Å
ZrO2=43Å
ZrO2=82Å
As-deposited ALDZrO2 is polycrystalline.
ZrO2
Chemical oxide
Si
HfO2=28Å
HfO2=45Å
HfO2=62Å
HfO2
Chemical oxide
As-deposited ALD-HfO2
is amorphous.
It crystallizes upon high
temperature annealing
Si
• There is always a thin layer of chemical SiO2 present at the interface
• There are charges and trap states at various interfaces and grain boundaries
araswat
tanford University
65
EE311 / Gate Dielectric
12
HR-XTEM
HfO2
GeOxNy
Ge
4 nm
Effective Mobility (cm2/V-s)
High-k Gate Dielectric Can Also be
Applied to Other Semiconductors
400
25 µm Ge hi-! pFET
30 µm Ge hi-! pFET
100 µm Ge hi-! pFET
300
200
Si Universal
Mobility
100
Si hi-! pFET
0
0.2
0.3
0.4
0.5
0.6
Effective Field (MV/cm)
Chui, et. al., IEDM 2002




Passivation of Ge with GeOxNy, ZrO2 and HfO2
1st demo of Ge MOSFETs with hi-κ
p-MOSFET with 3× mobility vs. Hi-k Si
Passivation of many other materials being experimented,
e.g., carbon nanotubes, GaAs, etc.
araswat
tanford University
66
EE311 / Gate Dielectric
Issues With High k Dielectrics
• How good is the interface with Si? ⇒ mobility
• Contamination of Si by metal atoms
• Compatibility with gate electrode ⇒ metal gate
• Device reliability and lifetime
• Minimum EOT achievable
• Technology integration
More research is needed to make these materials
manufacturable and reliable
araswat
tanford University
67
EE311 / Gate Dielectric
13
µ
Co
ulo
mb
ic
Reduced Mobility in High- K Gate Stacks
Phon
on
Surface
Roughness
1
1
1
1
=
+
+
µ eff µC µ ph µ sr
Eeff
Hole
Electron
araswat
tanford University
S. Saito, et al., IEEE IEDM, 2003.
68
EE311 / Gate Dielectric
Possible Sources for Reduced Mobility in
High- K Gate Stacks
S. Saito, et al., IEEE IEDM, Washington, DC, Dec., 2003.
Extensive research is needed to understand these mechanisms and
how to minimize their impact on device performance
araswat
tanford University
69
EE311 / Gate Dielectric
14
Effect of Interface states on CV curves
Large density of slow states
Small density of states
 Severe distortion, hysteresis and frequency dependence in C-V can be
observed if large number of slow states are present
 This causes degradation in device properties, such as, Vt, mobility, etc.
araswat
tanford University
70
EE311 / Gate Dielectric
Effect of Slow Dit states on CV Curves
C
Responding to
DC (Ideal)
Responding
to DC (Actual)
Effect of Cit
Downsweep
Up-sweep
Decreasing frequency
Responding to
DC (Actual)
Vt shift
Acceptor
-ve
V
 Measurement is like a regular C-V setup with a DC sweep from +ve to
–ve followed by a DC sweep from –ve to +ve.
 Hysteresis in C-V is due to the VERY slow states that do not empty
out fast enough and cannot even respond to the slow DC sweep.
araswat
tanford University
71
EE311 / Gate Dielectric
15
Effect of Interface States on Mobility in
High- K Gate Stacks
Eeff = 0.1 MV/cm
µeff, for HfO2 and SiO2 gate MOSFETs,
along with their three components,
including the components limited by
Coulomb scattering, µcoul, surface
roughness scattering, µsr, and the
phonon scattering, µph.
araswat
tanford University
Effect of interface traps on mobility.
Coulombic scattering reduces the
mobility
Ref: T. P. Ma, IEEE TED, Jan 04
72
EE311 / Gate Dielectric
High-K/Poly-Si Gate Transistors
 High-K/poly-Si gate transistors suffer from high VT, degraded channel
mobility and poor drive performance
 Phonon scattering limits channel mobility in high-K/poly-Si gate MOSFETs
araswat
tanford University
R. Chau, Intel, ICSICT 2004
73
EE311 / Gate Dielectric
16
Metal Gate Screens Surface Phonon Scattering and
Improves Mobility in High-K Transistors
1
1
="
µ i µi
R. Chau, Intel, ICSICT 2004
!
araswat
tanford University
74
EE311 / Gate Dielectric
Annealing Crystallization of ALD-HfO2
In-situ anneal at 520°C using 30Å HfO2 on 25Å thermal SiO2.
As-dep
10 min
20 min
50 min
60 min
70 min
 Upon annealing the amorphous films cryatsllize
 Grain boundaries cause statistical variation in the properties
 By adding other elements (e.g. N, Al, Si) to HfO2 crystallization can
be impeded
araswat
tanford University
75
EE311 / Gate Dielectric
17
Crystallization and Phase Separation
20% SiO2
3.1 MX
55% (21-12)
55%
SiO2
HfO2
SiO2
Si
SiO2
5 nm
SiO2
5 nm
65% SiO2
75 % (21-18)
75%
SiO2
65% SiO2 (21-15)
 Non-uniformity of k-value
leads to mobility degradation
 This can occure in the case
of silicates.
G.B. et al., MRS 2004
5 nm
araswat
tanford University
5 nm
B.Foran et al., ALD conference, 2004
76
EE311 / Gate Dielectric
Luigi Colombo, et al.,(T.I.) IWGI Nov 2003 Tokyo, Japan
araswat
tanford University
77
EE311 / Gate Dielectric
18
Mobility: N Incorporation in HfSiO
Hole
Electron
Luigi Colombo, et al.,(T.I.) IWGI Nov 2003 Tokyo, Japan
araswat
tanford University
78
EE311 / Gate Dielectric
Summary
•Scaling issues
•Technology
•Reliability of SiO2
•Nitrided SiO2
•High k dielectrics
araswat
tanford University
79
EE311 / Gate Dielectric
19