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Extreme Electron Density Perovskite Oxide
Heterostructures for Field Effect Transistors
THESIS
Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in
the Graduate School of The Ohio State University
By
Omor Faruk Shoron
Graduate Program in Electrical and Computer Science
The Ohio State University
2015
Dissertation Committee:
Prof. Siddharth Rajan, Advisor
Prof. Betty L. Anderson
Copyright by
Omor Faruk Shoron
2015
Abstract
Perovskite oxides are an interesting group of materials with diverse and unique
electronic, photonic, optical and magnetic properties. One of the recent discoveries in
perovskite oxide is the extreme high electron density at polar and non-polar oxide
heterojunction interfaces. GdTiO3/SrTiO3 heterostructure shows an electron density of
3x1014 cm-2 at the interface that is around one order higher than any conventional
semiconductor heterostructures. In this work, GdTiO3/SrTiO3 heterostructures were used
to demonstrate field effect transistors. This is the first demonstration of transistor with
such high charge density. We also investigated the factors that limit the charge
modulation in this heterostructure, and developed an analytical model that can predict
charge control characteristics of this heterostructure. Three methods were proposed and
demonstrated to improve the modulation, leading to record charge modulation of
1.5x1014 cm-2, which is the highest to date for any semiconductor system using electronic
gating.
ii
Dedication
This work is dedicated to my family
iii
Acknowledgments
I would like to thank my advisor and mentor Prof. Siddharth Rajan for guiding me for
this project. This work is done as a part of Multi University Research Initiative project
and this work is funded by Office of Naval research. I would like to thank all of the
members of this project for their collaboration. Specially, I would like to thank Prof.
Susanne Stemmer, Clayton Jackson, Santosh Raghavan, and MC Buffon for providing
great samples for this work. I would like to acknowledge the help of Dr. MC Boucherit,
who also worked in this project in the beginning.
I would like to thank my group mates – Dr. DN Nath, Dr. PS Park, Dr. S
Krishnamoorthy, TS Hung, S Bajaj, E Lee, F Akyol, Z Yang, Y Zhang and CH Lee for
their help, suggestion and academic discussion.
I was at OSU without my family and this journey was not an easy one. I would like to
thank all of my Bangladeshi friends here, especially Dr. S Arafat, Dr. NF Laboni, Saady
Amin, Dr. Sajedur Akand, Dr. Rubab Khan, ATM Sarwar, Sadia Nasrin, Faiza Faria,
iv
Rashedul Alam Zuboraj, Syed Ashraf, Syed Saqueb, Pran Paul, Shariq B Shafi, Rubayet
Ratul who are always beside me even in my bad time. I can never forget their help.
Finally, I would like to thank my parents – Mr. Shafiqul Islam and Mrs. Suriaya Islam.
They are the sole reason I am here today. They sacrificed their dreams to build my future.
My two younger brothers – Shovon and Sudeep, are the best brothers in this world. I am
very happy to have such loving brothers. I would like to thank them for their
encouragement. I thank my family for believing me.
v
Vita
2003................................................................ Secondary School Certificate
2005................................................................Higher Secondary School Certificate
2011 ...............................................................B.Sc. Electrical and Electronic Engineering
Bangladesh University of Engineering and
Technology
2012 to present ..............................................Graduate Research Associate, ECE
Department, The Ohio State University
Publications
Journals:
1.
M Boucherit, O Shoron, CA Jackson, TA Cain, MLC Buffon, C Polchinski, S
Stemmer, S Rajan, “Modulation of over 10 14 cm− 2 electrons at the SrTiO3/GdTiO3
heterojunction” Applied Physics Letters, Vol. 104, Issue 18 (2014).
2.
M Boucherit, OF Shoron, TA Cain, CA Jackson, S Stemmer, S Rajan, “Extreme
charge density SrTiO3/GdTiO3 heterostructure field effect transistors” Applied Physics
Letters, Vol. 102, Issue 24 (2013).
3.
SA Siddiqui, OF Shoron, A Zubair, QD Khosru, “Band to Band Tunneling
vi
Current of Surface Channel Strained InxGa1-xAs (x= 0.47, 0.65, 0.75) Double Gate
Planner TFET” ECS Transactions, Vol. 35, Issue 3 (2011).
4.
Subramaniam Arulkumaran , Geok Ing Ng , C. M. Manoj Kumar , Kumud
Ranjan , Khoon Leng Teo , Omor Faruk Shoron , Siddharth Rajan , Surani Bin Dolmanan
, Sudhiranjan Tripathy, “Electron Velocity of 6×107 cm/s at 300 K in Stress Engineered
InAlN/GaN nano-channel High-Electron-Mobility Transistors”, Accepted to Applied
Physics Letters
5.
OF Shoron, Pil Sung Park, S Bajaj, S Krishnamoorthy, S Rajan, “Effect of charge
dependent velocity on device characteristic of AlGaN/GaN HEMTs” (in preparation for
EDL)
6.
OF Shoron, M Boucherit, CA Jackson, TA Cain, MLC Buffon, C Polchinski, S
Stemmer, S Rajan, “Effect of high-k BaSrTiO3 gate dielectric layer on GdTiO3/SrTiO3
HFETs” (in preparation for APL)
7.
M Boucherit, OF Shoron, CA Jackson, TA Cain, MLC Buffon, C Polchinski, S
Stemmer, S Rajan, “High Electric breakdown field of 5.7 MV/cm in SrTiO3/GdTiO3
Heterostructure” (in preparation for APL)
Selected Conferences Presentations:
1.
O Shoron, M Boucherit, CA Jackson, TA Cain, MLC Buffon, C Polchinski, S
Stemmer, S Rajan, “Modulation of over 10 14 cm− 2 electrons at the SrTiO3/GdTiO3
heterojunction” 72nd Annual Device Research Conference (DRC), 2014, Santa Barbara,
USA
vii
2.
Omor F Shoron ,M. Boucherit ,C. A. Jackson ,S. Raghavan ,C. Polchinski ,S.
Stemmer ,S. Rajan, “Improvement of Charge Modulation in SrTiO3/GdTiO3 HFET”
MRS Spring Meeting, 2014, San Francisco, USA.
3.
OF Shoron, M Boucherit, CA Jackson, P Moetakef, S Stemmer, S Rajan, “SrTiO
3/GdTiO 3 heterostructure field effect transistors” 71st Annual Device Research
Conference (DRC), 2013, South Bend, USA
4.
O. F. Shoron, S. A. Siddiqui, A. Zubair, Q. D. M.Khosru “A simple physically
based model of temperature effect on drain current for nanoscale Si and GaAs TFET”
IEEE International Conference of Electron Devices and Solid-State Circuits, 2010, Hong
Kong.
5.
S. Arulkumaran, N. G. Ing, C. M. M. Kumar, K. Ranjan, K.L. Teo, O. F. Shoron,
S. Rajan, S. B. Dolmanan and S. Tripathy “In0.17Al0.83N/AlN/GaN Triple T-shape FinHEMT with gm=646 mS/mm, Ion=1030 mA/mm, Ioff=1.13 μA/mm, SS=82 mV/dec and
DIBL=28 mV/V at VD=0.5 V “ International Electron Device Meeting (IEDM) 2014
Fields of Study
Major Field: Electrical and Computer Engineering
viii
Table of Contents
Abstract ............................................................................................................................... ii
Dedication ......................................................................................................................... iiii
Acknowledgments.............................................................................................................. iv
Vita..................................................................................................................................... vi
List of Tables ..................................................................................................................... xi
List of Figures ................................................................................................................... xii
Chapter 1: Introduction ...................................................................................................... 1
1.1 Research on perovskite oxides………………………………………………...2
1.2 Motivation and research objective………………………………………….....8
1.3 Thesis Organization…………………………………………………………...9
Chapter 2: GdTiO3/SrTiO3 Heterojunction Field Effect Transistors (HFETs) ................. 10
2.1 GdTiO3/SrTiO3 Heterostructure……………………………………………...10
2.2 Inverted transistor Structure………………………………………………….16
2.3 Fabrication………………………………………………………………...…18
2.4 Transistor characteristics…………………………………………………….26
Chapter 3: Improvement of modulation in GdTiO3/SrTiO3 HFET……………………..33
3.1 Interfacial Layer……………………………………………………………..33
ix
3.2 Effect of SrTiO3 Thickness………………………………………………….38
3.3 Surface treatment…………………………………………………………….49
3.4 High k dielectric……………………………………………………………..60
Chapter 4: Perovskite oxide MESFET and FerroFET…………………………………...74
4.1 SrTiO3 MESFET……………………………………………………………..74
4.2 Ferroeletric FET……………………………………………………………...83
Chapter 5: Summary and Future Work…………………………………………………..90
References………………………………………………………………………………..91
x
List of Tables
Table 1: ICP-RIE etching test ......................................................................................... 25
Table 2: Calculated and experimental breakdown field of different materials……….…59
Table 3: Constants of field dependent permittivity………………………………………78
Table 4: Baliga Figure of Merits (BFOM) for different materials………………………81
xi
List of Figures
Figure 1.1: Crystal structure of perovskite oxide................................................................ 1
Figure 1.2: Mott Material………………………………………………………………...5
Figure 2.1: Origin of free electron (2DEG) at polar non-polar oxide interfaces………..11
Figure 2.2: (a) Sheet Carrier concentration versus number of interfaces
(b) TEM image of GdTiO3/SrTiO3 interface…………………………….13
Figure 2.3: (a) Sheet resistance versus temperature for different GdTiO3 and SrTiO3
thicknesses (b) Mobility of 2DEG for different SrTiO3 thickness………15
Figure 2.4: (a) Inverted transistor structure (b) Band diagram and electron profile……..17
Figure 2.5: Ohmic contact resistance for Al/Ni Au, without any surface processing…...19
Figure 2.6: (a) AFM image of sample after 10s of BOE dip (b) Cross section height..…20
Figure 2.7: Ohmic contact resistance for Al/Ni/Au metal stack………………………....21
Figure 2.8: Ohmic Contact resistance of Nb/Au metal stack…………………………….22
Figure 2.9: Schottcky contact behavior of different metals……………………………...23
Figure 2.10: Gate leakage for different gate length……………………………………...24
Figure 2.11: Effect of oxygen plasma treatment…………………………………………24
Figure 2.12: Etching profiles after 4 minutes for different etching recipe………………27
Figure 2.13: Thickness of (a) SPR 950 and (b) SPR 220 after spin coating…………….28
Figure 2.14: Fabrication process flow…………………………………………………...29
xii
Figure 2.15: Capacitance-Voltage (C-V) profile of GdTiO3/SrTiO3 HFETs……………31
Figure 2.16: ID-VD characteristic for different drain gate bias………………………….32
Figure 3.1: (a) Band diagram with interfacial layer (b) Capacitance model…………….34
Figure 3.2: (a) Band diagram at equilibrium and (b) Band diagram at breakdown……..35
Figure 3.3: Device structure for SrTiO3 thickness study………………………………...39
Figure 3.4: Band diagram and electron profile for different SrTiO3 thickness…………39
Figure 3.5: Capacitance-Voltage study for different SrTiO3 thickness…………………40
Figure 3.6: ID-VD characteristics for 28nm SrTiO3/5nm GdTiO3 HFET………………...41
Figure 3.7: ID-VD characteristics for 40nm SrTiO3/5nm GdTiO3 HFET………………...42
Figure 3.8: ID-VD characteristics for 96nm SrTiO3/5nm GdTiO3 HFET………………...43
Figure 3.9: Improvement in charge modulation with increasing SrTiO3 thickness……..44
Figure 3.10: Effective low field SrTiO3 permittivity for different SrTiO3 thickness…...45
Figure 3.11: Charge modulation versus gate bias for different SrTiO3 thicknesses……..48
Figure 3.12: Charge modulation versus electric field in interfacial layer………………..48
Figure 3.13: (a) Device structure for surface treatment
(b) Band diagram and electron profile of the sample……………………51
Figure 3.14: Gate leakage characteristic……………………………………………...….52
Figure 3.15: Capacitance-voltage characteristic with and without surface treatment…...53
Figure 3.16: Simulation of the charge modulation as a function of the gate bias………..54
Figure 3.17: ID-VD characteristics for 40nm SrTiO3/5nm GdTiO3 HFET……………….55
Figure 3.18: Transconductance characteristics for 40nm SrTiO3/5nm GdTiO3 HFET….56
Figure 3.19: Triangular barrier at the gate……………………………………………….57
xiii
Figure 3.20: Breakdown field calculation for different material………………………...59
Figure 3.21: Comparison of breakdown field of different materials…………………….60
Figure 3.22: Device structure with high-k dielectric (Ba0.5Sr0.5TiO3)…………………...61
Figure 3.23: Transfer length measurement (TLM) I-V characteristic for Al/Ni/Au
ohmic contact. No etching and BOE dip before metal deposition……………….62
Figure 3.24: Transfer length measurement (TLM) I-V characteristic for Al/Ni/Au
ohmic contact. 8 min etch etching and no BOE dip before metal deposition……63
Figure 3.25: Transfer length measurement (TLM) I-V characteristic for Al/Ni/Au
ohmic contact. 10 min etching and 10s BOE dip before metal deposition………64
Figure 3.26: Process flow for sample with high-k barrier layer…………………………65
Figure 3.27: Gate barrier for (a) SrTiO3/GdTiO3 and
(b) BaSrTiO3/ SrTiO3/GdTiO3 structures……………………………………….66
Figure 3.28: Tunneling probability of electron at gate barrier at different applied
electric field……………………………………………………………………..68
Figure 3.29: Gate leakage characteristics for sample with and without BaSrTiO3 layer. 69
Figure 3.30: Capacitance voltage characteristics……………………………………...…70
Figure 3.31: Charge modulation for different barrier thickness…………………………71
Figure 3.32: ID-VD profile of BaSrTiO3/SrTiO3/GdTiO3 transistor…………………….72
Figure 3.33: gm profile of BaSrTiO3/SrTiO3/GdTiO3 transistor…………………………73
Figure 4.1: MESFET device structure…………………………………………………...75
Figure 4.2: Gate leakage characteristic of HFET and MESFET with similar
SrTiO3 thickness…………………………………………………………………75
xiv
Figure 4.3: ID-VD profile of SrTiO3 MESFET………………………………………….76
Figure 4.4: gm profile of SrTiO3 MESFET and SrTiO3/GdTiO3 HFET with same
SrTiO3 thickness…………………………………………………………………77
Figure 4.5: Capacitance-Voltage characteristics of SrTiO3 MESFET…………………...79
Figure 4.6: 1/C2 versus gate voltage……………………………………………………..80
Figure 4.7: Field dependent dielectric constant of SrTiO3………………………………80
Figure 4.8: BFOM and BHFFM of different materials…………………………………..82
Figure 4.9: Hysteresis loop of ferroelectric materials……………………………………83
Figure 4.10: (a) Simulated device structure (b) ID-VG characteristics…………….........84
Figure 4.11: (a) Device structure of FerroFET (b) Effect of ferroelectricity on
band diagram………………………………………………………………….....85
Figure 4.12: Schottky diode characteristic of FerroFET………………………………...86
Figure 4.13: Capacitance-Voltage profile………………………………………………..87
Figure 4.14: ID-VD profile of FerroFET………………………………………………...88
Figure 4.15: ID-Vg and Gm profile of FerroFET………………………………………..88
Figure 4.16: (a) Hysteresis in C-V profile (b) Hysteresis in ID-VG profile………………89
xv
Chapter 1: Introduction
After discovering mineral CaTiO3, geologist Gustave Rose named it perovskite. The
‘Perovskite’ term was coined honoring renowned mineralogist Count Lev Alexevich von
Perovski. But now, perovskite represents a large group of compound that has the
chemical formula ABC3. Perovskite oxide is a subclass of this group with common
chemical formula ABO3. In these compounds, transition metal ion B is bonded with eight
oxygen ions, forming an octahedron. The crystal structure of perovskite oxide is shown
in figure 1.1.
Figure 1.1: Crystal structure of perovskite oxide. Here, B is transition metal surrounded
by 6 oxygen atoms (O). [1]
1
Because of interesting electronic, magnetic and optical properties, currently perovskite
oxides are one of the central attractions of research in the field of physics, chemistry,
material science and electronics. Perovskite oxide covers all aspects of solid state
phenomena – metallic (LaTiO3, NaWO3 etc.), insulating (BaTiO3, SrTiO3 etc.),
semiconducting (doped SrTiO3), magnetic (PbCrO3, LaFeO3 etc.), superconducting
(NaWO3, LiWO3 etc.), ferroelectric (BaTiO3), Mott transition material (GdTiO3, VO2).
Because of wide varieties of material properties and similar chemical formula, integration
between different typed of perovskite materials can lead to new phenomena that could be
interesting for both physics and engineering. For example, polar and non-polar
heterostructures can produce high electron density two dimensional electron gases, a
heterojunction of Mott and band insulators can lead to insulator to metal transition. In this
chapter, I will summarize present status of perovskite oxide research, motivation of my
research and a brief overview of this dissertation.
1.1 Research on perovskite oxides
One of the most interesting properties that many perovskite oxides have is
ferroelectricity. In ferroelectric material, we can switch macroscopic polarization. A large
number of ferroelectric materials with technological significance are perovskites. The
first ferroelectric material was discovered in 1941 by Thurnaurer and Deaderick [2].
BaTiO3 ceramic was the first discovered ferroelectric perovskite oxide. BaTiO3 exhibited
very unique dielectric properties with very high relative permittivity – exceeding 1000 [3-
2
5]. Von Hippel [6] and Wul and Goldman [7] demonstrated ferroelectric behavior of
BaTiO3 for the first time.
To understand the origin of ferroelectricity in perovskite oxides, lot of experimental and
theoretical works have been done. Ronald E. Cohen [8] showed electronic calculation of
two very common ferroelectric perovskite oxides – BaTiO3 and PbTiO3 and suggested
that hybridization between 3d orbital of titanium atoms and 2p orbital of oxygen atoms is
necessary for ferroelectricity in perovskite titanates. In another study, Helen D. Megaw
[9] showed that perovskites that have bonds allowsing parallel dipoles with small
displacement and small barrier at potential maxima show ferroelectricity.
Because of ferroelectric behavior, perovskite oxide is a potential candidate for volatile
and non-volatile memory applications. Solid-state dynamic and static random access
memory (DRAM and SRAM) allow faster data storage for computers. But one of the
major drawbacks of conventional solid-state RAM is that when power is disconnected,
stored data is lost. In ferroelectric RAM (FRAM), the polarization state stores the data.
So, these devices can store data even without any power. So, in principle FRAM can be
operated in low power. In 1989, Gnadinger and Bondurant [10] showed how a metalferroelectric-metal (MFM) sandwich capacitor can be used as a memory device.
But one of the major problems with tradition ferroelectric materials is degradation over
time or fatigue [10-12]. Araujo et al. [13] showed ferroelectric capacitors using
3
perovskite oxides such as SrBi2Ta2O9, SrBiNbTaO9 and SrBi4Ta4O15 can overcome
fatigue problem. They found no sign of degradation even after 1012 switching cycles. B.
H. Park et al. [14] showed that lanthinum substituted bismuth titanate ferroelectric
capacitors could be a viable alternative for fatigue free FRAM. Uong Chon et al. [15]
showed that Bi4-xNdxTi3O12 could be an excellent material for FRAM because of its giant
spontaneous polarization.
By switching the polarity of polarization, it is possible to use ferroelectric insulators as
voltage step up transformers. By replacing dielectric insulators with ferroelectric
insulators in a MOSFET, it is possible to get negative differential capacitance and by
choosing appropriate thickness, theoretically it is possible to get subthreshold swing
below 60mV/dec at room temperature. This concept was first proposed by Salahuddin
and Datta [16]. In 2011, A.I Khan et al. [17] demonstrated the first experimental evidence
of negative differential capacitance using Pb(Zr0.2Ti0.8)O3 (PZT), a ferroelectric
perovskite. But in that work they used a ferroelectric and band insulator bilayer. In 2015
they demonstrated direct evidence of differential negative capacitance from pure
ferroelectric capacitor [18].
Another important property that some perovskite oxides have is Hubbard-Mott transition
or metal to Insulator transition (MIT). In late 1920’s, Beth, Bloch and Sommerfeld
developed a model that can describe metallic and insulating properties of material. This
model is the band-theory of materials. In this theory, electrons are considered
4
independent and if there is any partially filled band, that material is considered as metal.
On the other hand if the band is completely filled or empty, that material is an insulator.
But later, it was found that many transition metal oxides (perovskites) exhibit poor
conductivity, though those materials have partially filled d-orbital. According to band
theory, those materials should be metal, but in reality they are not. Later N. Mott came up
with a theory that can exhibit this unusual behavior [19,20]. In band theory, electronelectron interaction was not considered. But in some perovskite oxide, electron-electron
interaction is very strong and that can split the partially filled band into two bands –
upper Hubbard band and lower Hubbard band. If one of those bands is completely filled,
it makes the material insulating. This class of material is called Mott insulator in the
honor of N. Mott. The origin of insulating behavior in Mott material is shown in figure
1.2.
Figure 1.2: In the left, band is shown predicted by band theory. It shows half-filled band
that is a characteristic of metal. But strong electron-electron interaction splits the band
into two – upper Hubbard band (UHB) and lower Hubbard band (LHB). Now one band is
completely filled and another one is completely empty. So it shows insulating behavior.
5
But if we can change the electron configuration in the Hubbard band, we can make a
transition from insulator to metal. We can perturb the system by injecting electrons,
changing temperature, photoluminescence and electric field. M. M. Qazilbash et al. [21]
induced metallic state in insulating vanadium dioxide by increasing the temperature. The
result was confirmed by infrared spectroscopy. S. Lupi et al. [22] showed that by
lowering temperature Mott-Hubbard transition is possible in Cr-doped V2O3 and this
induced metallic state can coexist with insulating background. G Stefanovich et al. [23]
demonstrated electric field induced MIT. By electric field they injected electrons and that
induced MIT in VO2. They also found that critical electron density for MIT is in the order
of 1018-1019 cm-3. D. M. Newns et al. [24] demonstrated a field effect transistor based on
metal to insulator transition. They used back-gated transistor structure. A Mott insulator
cuprate layer, Y1-xPrxBa2Cu3O7-δ (YPBCO), was used as channel material.
Perovskite oxides have taken the superconductor research to the next level by introducing
high-Tc superconductor. Bednorz and Muller demonstrated [25] high-Tc superconductor
for the first time in 1986. They reported super conductance with onset temperature 90K.
This finding drew a lot of attention and made it possible to use the superconductor for
practical application such as electric motor, generator, magnet, transmission line,
connecting wires etc.
6
D. Mateika et al. [26] reported mixed perovskite (cations of Al based perovskites are
replaced by Sr2+, Ca2+, Ta5+, Nb5+ ions) for high-Tc superconductor. S. Takekawa et al.
[27] reported high temperature superconductivity in Nd1+xBa2-xCu3Oy. They also
demonstrated that they can vary onset of superconductivity from 93.5K to 40K by
changing mole fraction, x. Z. Ren et al. [28] demonstrated superconductivity in rare-earth
perovskite, ReFeAsO1-δ (Re = rare-earth metal, Sm, Nd, Pr, Ce, La). They showed that
Perovskite with Sm has highest Tc (55K) and Perovskite with La has the lowest Tc (25K).
A. Schilling et al. [29] demonstrated superconductor with highest Tc. They reported that
HgBa2Ca2Cu3O1+x is the superconductor with highest Tc (133K).
Another application of perovskite oxide is Resistance change Random Access Memory
(RRAM). This device has two different resistance states or bistable resistivity. Resistivity
changes because of the drift of anions (usually oxygen ions) by applied electric field.
This device is usually metal-insulator-metal (MIM) capacitor structure.
First reported RRAM was Al/Al2O3/Al MIM structure [30]. Later same characteristics are
demonstrated using NiO [31] and SiO2 [32]. All of these devices were unipolar or nonpolar devices. First bipolar structure was demonstrated using perovskite oxide – Nb2O5
[33]. In this case asymmetric electrodes of Nb and Bi were used. SrZrO3 was first used to
demonstrate reproducible resistive switching devices at +/- 0.5 V [34]. Pr0.7Ca0.3MnO3
(PCMO) shows reversible resistance change effect in epitaxial grown structures [35].
7
Perovskite oxides are also used for high efficient and low temperature Solid Oxide Fuel
Cells (SOFC). In 1994, Ishihara first demonstrated SOFC using lanthanum strontium
gallium magnesium oxides (LSGM) [36, 37]. Then a lot of works have been done to
make it more efficient and lower the operating temperature [38-42]. In 2007, SOFC
system was demonstrated for residential application for the first time [43].
Because of unique dielectric properties of perovskite oxides (i.e. high permittivity and
field dependent permittivity), these materials are used for reconfigurable high frequency
(> 1GHz) microwave capacitors [44-45].
One of the major advancements in perovskite oxide material is two dimensional electron
gases (2DEG) at polar non-polar oxide interface [46]. There are lot of perovskite oxide
heterostructures that exhibit 2DEG at the interface, such as - LaTiO3/SrTiO3, [47]
LaAlO3/SrTiO3, [48-49] LaVO3/SrTiO3, [50] SrTiO3/GdTiO3, [51] and NdTiO3/SrTiO3
[52]. This 2DEG could be used for electronic applications [53-55].
1.2 Motivation and research objective
The main motivation of my research was to use perovskite oxide for electronic
applications. In 2011, J. Son et al. demonstrated a very high 2DEG density (3x1014 cm-2)
at GdTiO3/ SrTiO3 interface [51]. In this work, my motivation was to use this extreme
electron density for electronic applications. We demonstrated the first heterojunction
field effect transistor (HFET) in the GdTiO3/SrTiO3 material system. We also analyzed,
8
proposed and demonstrated different mechanisms that can improve charge modulation in
this heterostructure. We also analyzed the prospect of SrTiO3 for high power application.
We also investigated the effect of ferroelectric gate in GdTiO3/SrTiO3 HFETs. This work
could be very important for high power electronics and tunable plasmonic applications.
1.3 Thesis Organization
In Chapter 2, I will discuss the origin of 2DEG at GdTiO3/SrTiO3 interface. Then I will
describe the transistor structure I used. Then I will summarize the fabrication technique
that we developed. Finally, I will show the electrical characterization of the HFET.
In Chapter 3, I will discuss the factors that are responsible for limiting charge modulation
in GdTiO3/SrTiO3 HFETs. Then I will discuss three mechanisms that can improve charge
modulation. I will also show an analytical model that can predict device performance.
In Chapter 4, I will discuss two other device structures – MESFET and Ferroelectric
gated FET (FerroFET). I will also analyze the prospect of SrTiO3 for high power
application.
Finally, in Chapter 5, I will summarize my results and discuss possible future works.
9
Chapter 2: GdTiO3/SrTiO3 Heterojunction Field
Effect Transistors (HFETs)
GdTiO3/SrTiO3 heterostructure exhibits extreme two dimensional electron gases (2DEG)
at the interface. In this chapter, at first I will discuss the origin of 2DEG at the interface.
Then I will discuss growth mechanism and electrical characteristic of the heterostructure.
Then I will describe fabrication steps to fabricate transistors in this material system.
Finally, I will show the electrical characterization of the HEFTs.
2.1 GdTiO3/SrTiO3 Heterostructure
Recently, 2-dimensional electron gas (2DEG) at polar and non-polar perovskite oxide
interfaces has become one of the center foci of condensed matter physics research.
Because of unique properties, such as extreme high charge density [47-52],
superconductivity, magnetism, metal-insulator transition (MIT), strong electron
correlation etc., researchers from different communities are working on understanding
and development of this unique material system [56-61]. The pioneer discovery of 2DEG
at LaTiO3/SrTiO3 interface [47] led to discover many more oxide combinations that
exhibit 2DEG such as LaAlO3/SrTiO3 [48,49] LaVO3/SrTiO3, [50] SrTiO3/GdTiO3,
[51,62] and NdTiO3/SrTiO3 [52].
10
The origin of this 2DEG is the polar discontinuity at the interface [46]. In polar material,
there is an alternating layer of positive and negatively charged sheets. Positively charged
sheet shares give their electrons to the adjacent negatively charged layers. But at the
interface, if the other material is non polar, the electron released by the positively charged
layer are not captured by any atoms. These free mobile electrons are the origin of 2DEG
at oxide interfaces. As every unit cell releases on electron and electrons are shared by two
layers (top and bottom), electron density at 2DEG should be half of the density of unit
cell at the interface, around 3x1014 cm-2. This phenomenon is clearly shown in figure 2.1.
Figure 2.1: Origin of free electron (2DEG) at polar non-polar oxide interfaces [63]
11
Though theory predicts a very high electron density at polar/non-polar oxide interfaces,
different issues, such as macroscopic fields, traps, non-stoichiometry, intermixing at the
interfaces etc., can lower the electron density by one order of magnitude. So we need a
very controlled growth mechanism where the interface is very sharp, defect and trap free.
So far most of the works done in oxide interfaces were focused on LaAlO3/SrTiO3 and
LaTiO3/SrTiO3 interfaces. These materials are mainly grown by pulsed laser deposition
(PLD) that requires high energy. Electron density at LaAlO3/SrTiO3 interface is around
1013 cm-3, that is, at least one order lower than the predicted by interface reconstruction
theory [64-66]. LaTiO3/SrTiO3 shows electron density that is close to the predicted value
[67,68], but the origin of free electron is still not clear [67,69].
Recently, Pouya Moetakef et al. developed a technique to grow a heterostructure between
Mott insulator GdTiO3 and band insulator SrTiO3 by Molecular Beam Epitaxy (MBE) on
LSAT substrate [62]. Because of controlled growth mechanism, the interface between
GdTiO3 and SrTiO3 is very smooth that can be seen in TEM image 2.2 (b). Because of
very sharp interface and 50:50 mixture of Ti3+ and Ti4+ at the interface, this
heterostructure exhibits a 2DEG of electron density 3x1014 cm-2, exactly same as
predicted by interface reconstruction theory. To verify the origin of this 2DEG, they grew
supper lattices of GdTiO3/SrTiO3 with different number of interfaces and they found that
2DEG electron density increases linearly with number of interfaces [62]. This confirms
12
that the origin of 2DEG at GdTiO3/SrTiO3 is the electronic reconstruction of the
interface, not artifacts due to growth issues or traps. This fact is shown in figure 2.3 (a).
Figure 2.2: (a) Sheet Carrier concentration versus number of interfaces (b) TEM image of
GdTiO3/SrTiO3 interface [62]
13
The electrical transport properties of SrTiO3/GdTiO3 heterostructures are shown in figure
2.3. In figure 2.3 (a), sheet resistance is shown for different GdTiO3 and SrTiO3
thickness. In figure 2.3 (b), mobility, electron density are shown. From these figures it is
evident that even a 1nm SrTiO3 layer can exhibit 2DEG electron at the interface and the
electron density is independent of SrTiO3 thickness, which is another proof of electronic
reconstruction of the interface. Above 20 nm SrTiO3 thickness mobility of 2DEG is
independent of SrTiO3 thickness. Room temperature mobility of 2DEG is 8 cm2/V-s and
at low temperature it becomes 400 cm2/V-s [62]. The mobility of a 2DEG is Optical
Phonon (OP) limited at room temperature and impurity scattering limited at low
temperature [70].
14
Figure 2.3: (a) Sheet resistance versus temperature for different GdTiO3 and SrTiO3
thicknesses (b) Mobility of 2DEG for different SrTiO3 thickness [62]
15
2.2 Inverted transistor Structure:
As there is a huge mobile 2DEG at GdTiO3/SrTiO3 interface, it could be an interesting
material to explore from device engineering point of view. To make a transistor out of
this material system, our first concern was what should be the preferable device structure
for electronic application.
Because of staggered band line-up between SrTiO3 and GdTiO3, 2DEG electrons are
confined in SrTiO3 layer [71]. The bandgaps of GdTiO3 and SrTiO3 are 3.25eV and 1.8
eV respectively [72,62]. The dielectric constant of SrTiO3 is 300ε0 at low field and it
varies with electric field [73]. GdTiO3 has a lower dielectric constant - 30ε0 [62]. The
conduction band offset between GdTiO3 and SrTiO3 is 0.7eV measured by Hard X-ray
Photoelectron Spectroscopy (HXPS) [71]. As the 2DEG density is very high, electrons
occupy multiple sub-bands with different effective masses. The effective mass of this
2DEG electron is 1-2m0. As these electrons are d-orbital electrons, these electrons have
very high effective mass. Based on this information we calculate the band and charge
profile using 1D Poisson, a self-consistent Schrodinger-Poisson solver [74]. The band
diagram and 2DEG profile for GdTiO3/SrTiO3 are shown in figure 2.4 (b). From this
figure, it is clear that the 2DEG is highly confined because of high effective mass.
16
(a)
(b)
Figure 2.4: (a) Inverted transistor structure (b) Band diagram and electron profile
17
Based on our study of material properties and band diagrams, we found that the inverted
structure will be good for Heterojunction Field Effect Transistors (HFETs). Inverted
structure means SrTiO3 will be the top layer and 2DEG channel will be just below the
gate contact as shown in figure 2.4 (a). Inverted structure has some benefits over normal
structure where GdTiO3 is on top. Advantages of inverted structure are:
 Higher Breakdown strength for SrTiO3
 Better short channel scaling
 Simple contacts (no barrier)
 Reduced CGS degradation due to wavefunction spread
2.3 Fabrication
As GdTiO3/SrTiO3 is a very new material system, we had to optimize each fabrication
step. We started our processing with the ohmic contact. As SrTiO3 has an electron
affinity of 4.1 eV and oxygen deficient growth condition makes the SrTiO3 layer slightly
n-type, a low workfunction metal would be a good choice for an ohmic contact. At first
we used Aluminum (Al) that has a workfunction 4.09 eV. It gives a contact resistance 3.6
Ω-mm that is shown in figure 2.5. As there is a barrier of SrTiO3 thin film between 2DEG
and ohmic metal, it causes higher contact resistance. As GdTiO3 can decompose at high
temperature, we could not use rapid thermal annealing (RTA) to reduce contact
resistance. Later we found out that if we dip our sample in Buffer Oxide Etchant (BOE)
(HF:H2O=1:10) for several seconds, it creates some holes in the epitaxial layer, shown in
figure 2.6. These holes may help to create contact between the metal and the 2DEG. So
18
we repeated the experiment with same metal stack (Al/Ni/Au), but this time we dipped
our sample in BOE for 10s just before depositing the metal. This time we got a contact
resistance of 0.5 Ω-mm that is shown in figure 2.7. High electron density at 2DEG is the
reason for this low contact resistance [75].
Figure 2.5: Ohmic contact resistance for Al/Ni Au, without any surface processing
19
(a)
(b)
Figure 2.6: (a) AFM image of sample after 10s of BOE dip (b) Cross section height
analysis shows holes with depth 40~80 nm
20
Figure 2.7: Ohmic contact resistance for Al/Ni/Au metal stack. Contact resistance after
10s BOE dip is 0.5 Ω-mm
21
We tried other metals for ohmic contacts, too. Niobium (Nb) is another low workfunction
(4.3eV) material. We deposited Nb/Au metal stack with BOE dip, and transfer length
measurement (TLM) gives a contact resistance 0.3 Ω-mm (figure 2.8). But the sticking
coefficient between Nb and SrTiO3 is very low. So we used Al/Ni/Au metal stack as
ohmic contact for all of our device fabrication.
Figure 2.8: Ohmic Contact resistance of Nb/Au metal stack. Contact resistance after 10s
BOE dip is 0.3Ω-mm
22
After the ohmic contact, we optimized Schottky contact. For Schottky, we tried different
high workfunction materials – Platinum (Pt), Nickel (Ni) and Silver (Ag). Schottky diode
characteristics are shown in figure 2.9. From the figure, it is clear that Pt gives the best
Schottky behavior. Gate leakage current also depends on the area of the gate contact. For
higher contact area leakage current density is higher (figure 2.10) and it is because of
non-uniformity of the sample. We can also improve gate leakage characteristics by O2
treatment just before depositing gate metal. It is shown in figure 2.11. O2 plasma helps to
clean the surface. Moreover, there are oxygen vacancies in SrTiO3 and O2 plasma helps
to fill up O2 vacancies and make it more insulating. All these help to reduce gate leakage.
Figure 2.9: Schottky contact behavior of different metals. Pt shows best rectification
behavior
23
Figure 2.10: Gate leakage for different gate length. Larger gate causes higher leakage
Figure 2.11: Effect of oxygen plasma treatment. Oxygen plasma improves gate leakage.
24
Perovskite oxides are very hard materials to etch. So we used Reactive Ion Etching (RIE)
to etch SrTiO3 and GdTiO3. We used Chlorine based etching recipe (Cl2/BCl3). We used
100W RIE power with different Cl2/BCl3 ratio. Chamber pressure was fixed at 5mT. We
used three different conditions to run the etching test – 5 sccm BCl3 & 50 sccm Cl2, 35
sccm BCl3 & 5 sccm Cl2 and 50 sccm BCl3 & 5 sccm Cl2. Samples were etched for 5min
under each condition. Etching profiles are shown in figure 2.12 and the results are
summarized in the table below:
RIE Power: 100W, Base Pressure: 5mT, Etch Time: 5min
Condition
Etch Depth
Etch rate (nm/min)
5 sccm BCl3 & 50 sccm Cl2
20nm
4 nm/min
35 sccm BCl3 & 5 sccm Cl2
12nm
2.4 nm/min
50 sccm BCl3 & 5 sccm Cl2
13nm
2.6 nm/min
Table 1: ICP-RIE etching test
From our result we found that 5sccm BCl3 and 50sccm Cl2 with 100W RIE power gives
best etch rate. As we used very high power etching, it created burnt photoresist residue on
the sample that contaminates the surface and increases the gate leakage. So instead of
etching continuously for long period, we divided our etch time into 2 minute segments, so
that the sample can cool down and prevent the burnt photoresist issue.
We used GCA i-line stepper for optical photolithography and for that we use SPR 950
photoresist. This photoresist has a thickness of 750 nm (figure 2.13 (a)) and the etch rate
25
of photoresist under our selected RIE condition is around 100nm/min. So we cannot etch
more than 25 nm at a time using SPR 950. So we used SPR 220 that is denser and gives
thicker coverage (around 7 μm) (figure 2.13 (b)). We can etch more than 100nm at a time
using this process recipe.
A complete process flow of transistor fabrication is shown in figure 2.14.
2.4 Transistor characteristics
Using the process flow described above, we fabricated GdTiO3/SrTiO3 HFETs. We are
the first to demonstrate HFET characteristics in GdTiO3/SrTiO3 material system. We
observed modulation from capacitance-voltage (C-V) characteristics. We also observed
drain current modulation with gate bias that also confirms 2DEG electron modulation.
26
(a)
(b)
(c)
Figure 2.12: Etching profiles after 4 minutes for different etching recipe (a) 50sccm
Cl2/5sccm BCl3 (b) 5sccm Cl2/50sccm BCl3 (c) 5sccm Cl2/35sccm BCl3
27
(a)
(b)
Figure 2.13: Thickness of (a) SPR 950 and (b) SPR 220 after spin coating
28
Figure 2.14: Fabrication process flow
29
The C-V characteristic is shown in figure 2.15. From the C-V profile we found that the
charge modulation is 6x1013 cm-2, which was the highest charge modulation for any
material system. The zero bias capacitance is very high (1.45 μF/cm2) compared to
conventional materials and it corresponds to a relative dielectric constant of 40 that is
very low compared to the bulk relative dielectric constant of SrTiO3 (350). This low
relative dielectric constant is due to the interfacial layer just below the gate. We will
discuss more about this interfacial layer and mechanisms to reduce the effect of
interfacial layer in next chapter.
The I-V characteristic is shown in figure 2.16. The I-V characteristic shows 20%
modulation in current. As the total 2DEG density is 3x1014 cm-2, 20% current modulation
corresponds to charge modulation of 6x1013 cm-2 that is consistent with our C-V result.
Though 6x1013 cm-2 electron modulation is the highest for any material system, still it is
only 20% of the total charge. In the next chapters we will discuss three mechanisms to
improve charge modulation.
30
Figure 2.15: Capacitance-Voltage (C-V) profile of GdTiO3/SrTiO3 HFETs. From C-V
profile, total modulated charge is 6x1013 cm-2
31
Figure 2.16: ID-VD characteristic for different drain gate bias. Gate voltage is varied from
0V to -10V. The source to drain spacing of the transistor is 3.5 μm, the source to gate
spacing is 0.5 μm and the gate length is 1 μm
32
Chapter 3: Improvement of modulation in
GdTiO3/SrTiO3 HFET
In the previous chapter we described GdTiO3/SrTiO3 HFET and concluded that
modulation in these HFETs are mainly limited by the interfacial layer. In this chapter I
will investigate the effect of the interfacial layers more qualitatively and develop a model
to explain charge modulation in GdTiO3/SrTiO3 HFETs including interfacial layers. Then
I will discuss three techniques to improve charge modulation. The first technique is
increasing the thickness of SrTiO3 layer. The second technique is surface treatment and
the final method is using high-k gate dielectric. I will discuss the high breakdown field of
SrTiO3, too.
3.1 Interfacial Layer
As mentioned in last chapter, an interfacial dead layer is one of the major factors that
limit the charge modulation of GdTiO3/SrTiO3 HFETs. There is always a thin dead
interfacial layer with low dielectric constant on SrTiO3 surface [76]. So the gate
capacitance consists of two series capacitors – the interfacial layer capacitance and the
SrTiO3 thin film capacitance. This is shown in figure 3.1.
33
If there is no charge at the interface, perpendicular electric fields of interfacial layer and
SrTiO3 layer can be related using the boundary condition:
𝜀𝑆𝑇𝑂 𝐸𝑆𝑇𝑂 = 𝜀𝑖𝑛𝑡 𝐸𝑖𝑛𝑡 …………………………… (1)
Here, εSTO and εint are the dielectric constants of SrTiO3 and interfacial layers respectively
and ESTO and Eint are the perpendicular electric fields of SrTiO3 and interfacial layers
respectively. As the interfacial layer has a very low dielectric constant compared to
SrTiO3 [76], the field at the interfacial layer is very high, causing early breakdown at the
interfacial layer that is shown in figure 3.2. This early breakdown at the interfacial layer
limits the gate bias that can be applied to modulate 2DEG electrons and hence limit
charge modulation.
Figure 3.1: (a) Band diagram with interfacial layer (b) Capacitance model
34
1
At Equilibrium
Energy (eV)
0
-1
-2
-3
-4
-5
-20
0
20
40
60
80
100 120
Thickness (nm)
(a)
Energy (eV)
20
At Breakdown Voltage
10
0
-20
0
20
40
60
80
100 120
Thickness (nm)
(b)
Figure 3.2: (a) Band diagram at equilibrium and (b) Band diagram at breakdown
35
Now we will use a very simple parallel plate capacitor model to analyze the effect of the
interfacial layer. The calculation is based on the model shown in figure 3.1. This is a very
simple model and we assumed 2DEG is highly confined so that we can consider it as
sheet charge. Moreover we will not consider field dependent dielectric constant of SrTiO3
in this calculation. We will show more accurate and modified capacitance model using a
field dependent dielectric constant later in this chapter.
As mentioned earlier, the gate capacitance, CG, has two components – capacitance due to
interfacial layer (Cint) and capacitance due to SrTiO3 layer (CSTO). Let the thickness of
SrTiO3 and interfacial layers be tSTO and tint respectively. If the dielectric constant of
SrTiO3 and interfacial layer are εSTO and εint respectively, we can define CSTO and Cint as
below:
𝐶𝑆𝑇𝑂 =
𝐶𝑖𝑛𝑡 =
𝜀𝑆𝑇𝑂
𝑡𝑠𝑡𝑜
𝜀𝑖𝑛𝑡
𝑡𝑖𝑛𝑡
…………….. (2)
…………………… (3)
So, total gate capacitance, CG can be written as –
1
𝐶𝐺
=
=>
1
𝐶𝑆𝑇𝑂
1
𝐶𝐺
=
=> 𝐶𝐺 =
+
1
𝐶𝑖𝑛𝑡
𝑡𝑆𝑇𝑂
𝜀𝑆𝑇𝑂
+
𝑡𝑖𝑛𝑡
𝜀𝑖𝑛𝑡
𝜀𝑆𝑇𝑂 𝜀𝑖𝑛𝑡
𝜀𝑆𝑇𝑂 𝑡𝑖𝑛𝑡 +𝑡𝑆𝑇𝑂 𝜀𝑖𝑛𝑡
……………………. (4)
36
So the total charge modulation can be described as
𝑄 = 𝐶𝐺 𝑉𝐺,𝑚𝑎𝑥 …………………. (5)
Now, VG,max can be related to the electric field at SrTiO3 at the breakdown of interfacial
layer (EBR). As the interfacial layer is very thin compared to the SrTiO3 barrier thickness,
we can assume all of the gate voltage drops at SrTiO3 barrier layer and in that case we
can write –
𝑉𝐺.𝑚𝑎𝑥 = 𝐸𝐵𝑅 𝑡𝑆𝑇𝑂 …………………… (6)
Combining (4), (5) and (6) we can write –
𝑄=
𝜀𝑆𝑇𝑂 𝜀𝑖𝑛𝑡 𝐸𝐵𝑅 𝑡𝑆𝑇𝑂
𝜀𝑆𝑇𝑂 𝑡𝑖𝑛𝑡 +𝑡𝑆𝑇𝑂 𝜀𝑖𝑛𝑡
…………………… (7)
If we rewrite (7) we can find that –
𝜀
𝜀
𝑆𝑇𝑂 𝑖𝑛𝑡
𝑄 = 𝜀𝑆𝑇𝑂
𝑡𝑖𝑛𝑡
𝑡𝑆𝑇𝑂
𝐸𝐵𝑅
+𝜀𝑖𝑛𝑡
…………………… (8)
From (8), it is evident that if we can increase the SrTiO3 layer thickness, it will reduce the
effect of the interfacial layer and improve charge modulation. We can rewrite (7) in a
different way, too 𝑄=
𝜀𝑖𝑛𝑡 𝐸𝐵𝑅 𝑡𝑆𝑇𝑂
𝑡
𝜀𝑖𝑛𝑡
𝑡𝑖𝑛𝑡 + 𝑆𝑇𝑂
𝜀
…………………… (9)
𝑆𝑇𝑂
From (9), it is clear that if we can increase effective SrTiO3 dielectric constant, we can
improve charge modulation.
Based on the discussion above, we find couple of ways that can improve charge
modulation. In next three section, three different mechanisms will be discussed that cam
37
improve charge modulation in GdTiO3/SrTiO3 HFETs. At first, I will discuss how
SrTiO3 thickness improves charge modulation. Then I will explain a surface treatment
mechanism that can reduce interfacial layer effect and hence improve charge modulation.
And finally I will describe the effect of high-k gate dielectric layer that increases
effective capacitance and thus increases charge modulation.
3.2 Effect of SrTiO3 Thickness
As discussed in previous section, thickness of SrTiO3 layer can reduce the effect of
interfacial layer and hence increase charge modulation. To verify this idea we run an
experiment, where we varied SrTiO3 thickness in SrTiO3/GdTiO3 heterostructures. We
used three samples where SrTiO3 thicknesses are 28 nm, 40 nm and 96 nm. In all cases,
GdTiO3 thickness is 5nm. Hall measurement shows 2DEG electron density 3x1014 cm-2
in each sample. So in this experiment all heterostructures are identical except SrTiO3
thickness. Device structure is shown in figure 3.3. Band diagram is shown in figure 3.4.
After preparing the samples, we fabricated these samples using the process flow
described in previous chapter. Ohmic contact was good in all samples and we also got
very good Schottky behavior. Schottky breakdown increased with increasing SrTiO3
thickness. After Ohmic contact deposition, mesa isolation and gate contact deposition,
electrictical characterization was carried out.
38
Figure 3.3: Device structure for SrTiO3 thickness study. Gate length is 1μm, Source to
drain spacing is 3.5μm and source to gate separation is 0.5μm
Figure 3.4: Band diagram and electron profile for different SrTiO3 thickness
39
Capacitance voltage characteristic of all three device structures are shown in figure 3.5.
By integrating the area of C-V curve, we can get the total charge modulation. From C-V
profile, charge modulations are 5.5x1013 cm-2, 8.5x1013 cm-2 and 1.05x1014 cm-2 for
26nm, 40nm and 96nm device structure respectively. From, C-V profile, it is evident that
charge modulation increases with SrTiO3 barrier thickness. So this result undoubtedly
verifies our idea described in previous section.
Figure 3.5: Capacitance-Voltage study for different SrTiO3 thickness. From C-V profile,
charge modulations are 6x1013, 8.5x1013 and 1.05x1014 cm-2 for 28nm, 40nm and 96nm
SrTiO3 layer respectively
40
In figure 3.6, ID-VD characteristic for different gate bias is shown for 26nm SrTiO3/ 5nm
GdTiO3 HFETs. From ID-VD characteristic, we can observe 20% of current modulation.
From C-V profile, we observed charge modulation of 5.5x1013 cm-2 that is around 20% of
total charge in 2DEG. So ID-VD and C-V results are consistent.
Figure 3.6: ID-VD characteristics for 28nm SrTiO3/5nm GdTiO3 HFET. Gate voltage is
varied from 0V to -5V. Total current modulation is 20%. Gate length is 1μm, Source to
drain spacing is 3.5μm and source to gate separation is 0.5μm
41
In figure 3.7, ID-VD characteristic for different gate bias is shown for 40nm SrTiO3/ 5nm
GdTiO3 HFETs. From ID-VD characteristic, we can observe 30% of current modulation.
From C-V profile, we observed charge modulation of 8.5x1013 cm-2 that is around 30% of
total charge in 2DEG. So ID-VD and C-V results are consistent.
Figure 3.7: ID-VD characteristics for 40nm SrTiO3/5nm GdTiO3 HFET. Gate voltage is
varied from 0V to -10V. Total current modulation is 30%. Gate length is 1μm, Source to
drain spacing is 3.5μm and source to gate separation is 0.5μm
42
In figure 3.8, ID-VD characteristic for different gate bias is shown for 96nm SrTiO3/ 5nm
GdTiO3 HFETs. From ID-VD characteristic, we can observe 35% of current modulation.
From C-V profile, we observed charge modulation of 1.05x1014 cm-2 that is around 35%
of total charge in 2DEG. So ID-VD and C-V results are consistent.
Figure 3.8: ID-VD characteristics for 96nm SrTiO3/5nm GdTiO3 HFET. Gate voltage is
varied from 0V to -20V. Total current modulation is 35%. Gate length is 1μm, Source to
drain spacing is 3.5μm and source to gate separation is 0.5μm
43
As ID-VD and C-V profiles are giving same amount of charge modulation, it indicates that
the charge modulated by gate bias is mobile charge. So it is an indication of modulation
2DEG, not the effect of traps or other artifacts. The charge and percentage of current
modulation is shown in figure 3.9. This figure clearly shows the trend of increasing
modulation with increasing SrTiO3 thickness. This is a clear verification of our model
described in previous chapter. We also measured zero bias relative dielectric constant of
SrTiO3 from C-V profile. Here capacitance is the combination of the contribution of both
SrTiO3 and interfacial layer. So, calculated relative dielectric constant is the effective
relative dielectric constant of the barrier layer. In figure 3.10, effective dielectric constant
of barrier is plotted for different SrTiO3 thickness and it can be seen that effective
dielectric constant increases with barrier thickness. This result suggests that effect of
interfacial layer reduces when SrTiO3 thickness is increased, as suggested by our theory.
Figure 3.9: Improvement in charge modulation with increasing SrTiO3 thickness
44
Figure 3.10: Improvement in effective low field SrTiO3 permittivity with increasing
SrTiO3 thickness. This trend suggests that effect of interfacial layer is reduced with
increasing SrTiO3 thickness
To understand how SrTiO3 thickness affects change modulation, previous simple
capacitance model is modified incorporating field dependent dielectric constant of SrTiO3
in calculation. In this modified model, we still considered two serial capacitors – CSTO
and Cint. As electron of 2DEG is highly confined due to high effective mass of electron in
SrTiO3, we ignored 2DEG spreading.
Electric Field dependent dielectric constant of SrTiO3 can be given by [77], -
45
𝜀𝑆𝑇𝑂 =
𝐴
√𝐵+𝐸𝑆𝑇𝑂 2
… … … … … … … .. (10)
We know, capacitance is defined by –
𝐶𝑆𝑇𝑂 =
𝑑𝑄
𝑑𝑉𝑆𝑇𝑂
… … … … … … … …. (11)
For 2-dimension sheet charge, electric field and sheet charge density can be related by the
following relation –
𝑄 = 𝜀𝑆𝑇𝑂 E𝑆𝑇𝑂 … … … … … … … … …. (12)
So, from (11) and (12) we get,
𝐶𝑆𝑇𝑂 =
𝑑(𝜀𝑆𝑇𝑂 𝐸𝑆𝑇𝑂 )
𝑑𝑉𝐺
= 𝜀𝑆𝑇𝑂
𝑑𝐸𝑆𝑇𝑂
𝑑𝑉𝐺
𝑑𝜀𝑆𝑇𝑂
+ 𝐸𝑆𝑇𝑂
𝑑𝑉𝐺
… … … … … ….(13)
But, field in SrTiO3 depends on the voltage drop in SrTiO3 (VSTO) and SrTiO3 layer
thickness (tSTO) and the relation between these terms are –
𝑉𝑆𝑇𝑂 = 𝐸𝑆𝑇𝑂 𝑡𝑆𝑇𝑂 … … … … … … …. (14)
Using this relation in (10) we get –
𝜀𝑆𝑇𝑂 =
𝐴
𝑉
√𝐵+( 𝑡 𝑆𝑇𝑂 )2
… … … … … … … .. (15)
𝑆𝑇𝑂
So,
𝑑𝜀𝑆𝑇𝑂
𝑑𝑉𝐺
=−
𝐴𝑉𝑆𝑇𝑂
2 3
𝑉
2
𝑡𝑆𝑇𝑂 (𝐵+( 𝑡 𝑆𝑇𝑂 ) )2
𝑆𝑇𝑂
… … … … … … (16)
So, from (10)-(16) we can get capacitance due to SrTiO3 barrier, and that is
𝐶𝑆𝑇𝑂 (𝑉𝑆𝑇𝑂 ) =
𝐴
𝑡𝑆𝑇𝑂 √𝐵+𝐸𝑆𝑇𝑂 2
−
𝐴𝑉𝑆𝑇𝑂 2
𝑉
2 3
𝑡𝑆𝑇𝑂 3 (𝐵+( 𝑡 𝑆𝑇𝑂 ) )2
… … … … … ….(17)
𝑆𝑇𝑂
On the other hand, capacitance for interfacial layer is given by –
𝐶𝑖𝑛𝑡 =
𝜀𝑖𝑛𝑡
𝑡𝑖𝑛𝑡
… … … … … … … .. (18)
46
From (17) and (18), we can get total gate capacitance using the relation 1
𝐶𝐺
=
1
𝐶𝑆𝑇𝑂
+
1
𝐶𝑖𝑛𝑡
… … … … … … .. (19)
We can also calculate the total gate bias using following equation –
𝑉𝐺 = 𝑉𝑆𝑇𝑂 + 𝑉𝑖𝑛𝑡 = 𝑡𝑆𝑇𝑂 𝐸𝑆𝑇𝑂 + 𝑡𝑖𝑛𝑡 𝐸𝑖𝑛𝑡 = 𝑡𝑆𝑇𝑂 𝐸𝑆𝑇𝑂 + 𝑡𝑖𝑛𝑡
𝑡𝑖𝑛𝑡 𝑉𝑆𝑇𝑂
𝐴
𝑡𝑆𝑇𝑂 𝜀𝑖𝑛𝑡
√𝐵+𝐸𝑆𝑇𝑂 2
𝜀𝑆𝑇𝑂 𝐸𝑆𝑇𝑂
𝜀𝑖𝑛𝑡
= 𝑉𝑆𝑇𝑂 +
… … … … … … … … (20)
So, if we vary VSTO, we can get the CG-VG relation for GdTiO3/SrTiO3 heterostructure
including interfacial layer effect using equations (17)-(20).
To verify our model, we compare our experimental results with this model. We calculate
charge modulation for different field and gate bias and then compared it with our results.
For our calculation, we assumed the dielectric constant of interfacial layer is 10ε0 and
thickness is 1nm. Modulation for different gate bias and field are shown in figure 3.11
and figure 3.12, respectively. The comparison between model and experimental results is
shown in figure 3.12. This figure clearly shows that our model matches quite accurately
with experimental data. This result not only verifies our model, but also confirms that
charge modulation is limited by interfacial layer.
47
Figure 3.11: Charge modulation versus gate bias for different SrTiO3 thicknesses
Figure 3.12: Charge modulation versus electric field in interfacial layer (left). Proposed
model is compared with experimental data (right) and it shows good agreement with
experimental data
48
3.3 Surface treatment
From our previous discussion, it is clear that interfacial layer is one of the main reasons
that limit charge modulation in GdTiO3/SrTiO3 FETs. Increasing SrTiO3 layer thickness
we can increase charge modulation. But we cannot modulate huge 2DEG electron at
GdTiO3/SrTiO3 heterostructure completely just by increasing SrTiO3 thickness. There are
three problems with this approach:
Firstly, to grow good quality SrTiO3 on top of GdTiO3 by MBE technique, it needs to
grow in oxygen deficient condition. It creates oxygen vacancies in SrTiO3 layer and make
it n-type doped. Doping is in the order of 1019 cm-3 (will be discussed in next chapter). So
if we increase SrTiO3 thickness, it will increase the charge, too. So it will be more
difficult to pinch off the device. Moreover, if SrTiO3 is not insulating, then the layer
between 2DEG and gate metal will be depleted that will increase the electric field and
may cause early breakdown.
Secondly, if we can fix the growth issue and make the SrTiO3 layer insulating, in that
case it will be difficult to make a good ohmic contact through insulating layer.
Finally, from figure 3.12, it is clear that charge modulation trends to be saturated with
SrTiO3 thickness. So, even if we increase the SrTiO3 thickness indefinitely, we might not
be able to deplete the whole channel.
49
So we need to apply different approach to solve this problem. To minimize the effect of
interfacial layer we did a surface treatment that improves charge modulation. For this
experiment, we used SrTiO3/GdTiO3 heterostructure with thickness 40 nm and 5nm
respectively. Hall measurement shows 2DEG density 3x1014 cm-2. Device structure and
Band diagram is shown in figure 3.13.
We start our fabrication with usual recipe of ohmic contact deposition and mesa isolation.
We used Al/Ni/Au metal stack as ohmic contact that gives ohmic resistance 0.5 Ω-mm.
After mesa isolation an extensive O2 plasma treatment was done. We used ICP/RIE
technique for this treatment. We used 50 sccm O2 with ICP power 300 W and RIE power
100 W. Chamber base pressure was 5 mTorr. We run ran this treatment for 30 min. This
extensive treatment cleaned the surface and removed all burnt resist residue created by
high power RIE etching for mesa isolation. Moreover, O2 diffusion helped to fill O2
vacancies in SrTiO3 layer that makes the layer more insulating and increased breakdown
field. After O2 treatment, we deposited Pt/Au metal stack as gate contact.
We also co-processed a same type of sample as reference without O2 surface treatment to
compare our results.
50
(a)
(b)
Figure 3.13: (a) Device structure for surface treatment (b) Band diagram and electron
profile of the sample
51
Schottky behavior of these two samples is shown in figure 3.14. From figure it is clear
that, Schottky reverse breakdown increases from 10V to around 25V after O2 treatment.
So, O2 plasma definitely improving breakdown field – either breakdown field of SrTiO3
or breakdown field of interfacial layer. In either case, it should improve charge
modulation.
Figure 3.14: Gate leakage characteristic. Gate breakdown voltage increases after surface
treatment
52
We measured capacitance-voltage (C-V) characteristics of these two samples and that is
shown in figure 3.15. By integrating C-V profile, we calculated charge modulation with
and without O2 plasma treatment. Without surface treatment charge modulation is
8.5x1013 cm-2. After surface treatment, it became 1.5x1014 cm-2, almost double. This is
the highest charge modulation in any semiconductor system using electronic gating found
in literature.
Figure 3.15: Capacitance-voltage characteristic with and without surface treatment.
Charge modulation increases by around 75%
53
In C-V profile, one interesting point is both C-V curves coincide. It suggests that O2
plasma treatment is not changing the dielectric constant of the interfacial layer, but
increasing the breakdown field of either interfacial layer or SrTiO3 layer. We used our
model described in previous section to calculate the effect of interfacial layer and we
found that dielectric constant of interfacial layer is 10ε0 (figure 3.16) that is exactly same
of that we found previously. So O2 plasma treatment is not changing dielectric constant,
but just improving breakdown field.
14
i 
-2
Charge modulation (cm )
2.0x10
i 
14
1.5x10
i 
14
1.0x10
Breakdown
13
5.0x10
0.0
0
1
2
3
4
5
6
Average Field (MV/cm)
Figure 3.16: Simulation of the charge modulation as a function of the gate bias. Star mark
shows the modulation in this experiment.
54
ID-VD profile of both devices is shown in figure 3.17. Current levels of both devices are
same, but we achieved more current modulation (50%) in device with surface treatment.
The reason of this high modulation is the high breakdown field of gate that allows us to
apply more gate bias. 50% current modulation is consistent with our C-V measurement
(1.5x1014 cm-2 electron modulation). In figure 3.18, transconductance (Gm) profile is
shown for device with O2 plasma treatment. We measured peak gm 5mS/mm that is
highest for GdTiO3/SrTiO3 HFETs.
(a)
(b)
Figure 3.17: ID-VD characteristics for 40nm SrTiO3/5nm GdTiO3 HFET: (a) with and (b)
without surface treatment. Gate length is 1μm, Source to drain spacing is 3.5μm and
source to gate separation is 0.5μm.
55
Figure 3.18: Transconductance characteristics for 40nm SrTiO3/5nm GdTiO3 HFET.
Drain voltage was 5V. Highest transconductance is 5mS/mm. Gate length is 1μm, Source
to drain spacing is 3.5μm and source to gate separation is 0.5μm
One of the interesting facts of figure 3.14 and 3.15 is the gate breakdown voltage – that is
around 23V. This voltage drops in between gate contact and 2DEG, and this distance is
around 40nm. So from this result it is clear that average field in SrTiO3 layer is
5.6MV/cm that is much higher than expected value. We know traditional semiconductor
follows ‘square law’ for breakdown field. According to ‘square law’, breakdown field is
proportional to the square of bandgap (EBR ∝ Eg2). As bandgap of SrTiO3 is 3.25eV,
56
close to bandgaps of SiC and GaN, we expect similar breakdown field for SrTiO3 that is
around 2MV/cm. But as average field in SrTiO3 is 5.6MV/cm, SrTiO3 should have
breakdown field at least 5.6MV/cm. But we are still not sure about the reason of
breakdown of gate. It could be due to SrTiO3 breakdown or interfacial layer breakdown.
If it is because of interfacial layer, in that case breakdown could be higher.
Figure 3.19: Triangular barrier at the gate
To understand the reason of high breakdown field of SrTiO3, we did simple calculation.
We did our calculation assuming band-to-band tunneling for Zener breakdown. For bandto-band tunneling, tunneling barrier is triangular (shown in figure 3.19) and we can use
Fowler-Nordheim tunneling approximation:
3
4√2𝑚∗ 𝐸2
𝑔
𝑇 = 𝑒−
3𝑒𝐸ħ
… … … … … … … … … … … … .. (21)
57
Here, m* is the effective mass of electron, Eg is the bandgap, E is the applied electric
field, e is the charge of an electron and ħ is Planck constant. If we compare two materials
assuming that breakdown happens at same tunneling probability, we can relate the
breakdown field of those two materials using following equation:
𝐸𝐵𝑅1 = 𝐸𝐵𝑅2 √
𝑚1∗
𝐸𝑔1
∗
𝑚12
(𝐸 )
3/2
𝑔2
… … … … … … … … … … .. (22)
In most of the semiconductor m*∝Eg1/2, so EBR∝Eg2 and this is the origin of square law.
But because of the presence of transition metal (Ti), SrTiO3 has mobile electron
contributed by d-orbital. So SrTiO3 has a very high effective mass of electron. For GaN,
bandgap is 3.4 eV with electron effective mass 0.2m0. On the other hand, SrTiO3 has
effective mass around 2m0 with bandgap 3.25eV. If we plug these values in (22) and
assume GaN breakdown field 2MV/cm, we found breakdown field 5.8MV/cm for SrTiO3
that is consistent with our experimental finding.
We calculated band to band tunneling for different materials (Si, GaN, SiC, SrTiO3) and
that is shown in figure 3.20. Taking Si breakdown field as reference we calculated the
breakdown field of these materials. Calculation confirms that breakdown field of SrTiO3
does
not
follow
“square
law”
(shown
in
figure
3.21).
Our calculated result is very consistent with experimental result that is shown in
following table:
58
Calculation
Experimental value [78]
Si
0.3 MV/cm
0.3 MV/cm
GaN
2.2 MV/cm
2 MV/cm
SiC
2.4 MV/cm
2.2 MV/cm
SrTiO3
5.9 MV/cm
5.6 MV/cm
Table 2: Calculated and experimental breakdown field of different materials
So, from the discussion above, it is clear that SrTiO3 has a very high breakdown field
because of high effective mass of electron. This could be a very important feature for
power electronics. We will discuss this later in next chapter.
10
Tunneling Probability
10
STO
Si
GaN
SiC
Breakdown
0
10
-10
10
2.2MV/cm
-20
0.4MV/cm
5.9MV/cm
2.4MV/cm
10
0
1
2
3
4
Field (MV/cm)
5
6
Figure 3.20: Breakdown field calculation for different material
59
7
Figure 3.21: Comparison of breakdown field of different materials.
3.4 High k dielectric
As we discussed earlier, another approach to improve charge modulation is to improve
effective dielectric constant of SrTiO3 barrier layer. But SrTiO3 itself has a very high
dielectric constant - 350ε0 at low electric field and 25ε0 at very high electric field
(6MV/cm). So traditional gate dielectric material will not be a good choice for gate
dielectric material here. For example, Al2O3 has dielectric constant of 9ε0 and HfO2 has
dielectric constant of 24ε0. Moreover, these materials are deposited using Atomic Layer
Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) or sputtering
60
method. These processes may create fixed charge or traps at the interface. So we need a
material that has a very high dielectric constant and can be grown by MBE.
Ba0.5Sr0.5TiO3 (BST) is such a material that has dielectric constant over 1000ε0 and lattice
parameter is close to that of SrTiO3. So it can be grown in MBE. For this experiment, we
used BaSrTiO3/SrTiO3/GdTiO3 sample with thickness 15nm, 20nm and 5nm
respectively. Hall measurement shows 2DEG density 2x1014 cm-2. The device structure is
shown in figure 3.22.
Figure 3.22: Device structure with high-k dielectric (Ba0.5Sr0.5TiO3)
61
As there is an insulating layer on top of SrTiO3 layer (BaSrTiO3 layer), we need to
optimize the ohmic contact. At first, we deposited ohmic metal (Al/Ni/Au) without
etching BaSrTiO3 layer away. As BaSrTiO3 is insulating, it did not give good ohmic
contact and there is little nonlinearity in the I-V characteristics. I-V characteristic is
shown in figure 3.23.
Figure 3.23: Transfer length measurement (TLM) I-V characteristic for Al/Ni/Au ohmic
contact. No etching and BOE dip before metal deposition
62
Then, we etched the sample for 8min using Chlorine based recipe discussed in previous
chapter, before depositing ohmic contact. Still there is nonlinearity as seen in figure 3.24.
Surface roughness due to high power etching could be a reason of this non linearity in IV characteristics.
Figure 3.24: Transfer length measurement (TLM) I-V characteristic for Al/Ni/Au ohmic
contact. 8 min etch etching and no BOE dip before metal deposition
63
Finally, we etched the sample for 10min and dipped the sample for 10s in Buffer Oxide
Etchant (BOE) just before depositing ohmic metal. Finally we got good ohmic behavior
in I-V characteristic that is shown in figure 3.25. Then we continued our usual processing
steps. Process flow diagram of complete fabrication is shown in figure 3.26.
Figure 3.25: Transfer length measurement (TLM) I-V characteristic for Al/Ni/Au ohmic
contact. 10 min etching and 10s BOE dip before metal deposition
64
Figure 3.26: Process flow for sample with high-k barrier layer
65
BaSrTiO3 is helping this modulation in two ways –
Firstly, it is increasing capacitance. So we can get higher charge modulation.
Secondly, Because of the low field in the BaSrTiO3, high-k layer helps to reduce gate
leakage. So we can apply high gate bias and get high charge modulation.
Schematic diagrams of conduction band are shown in figure 3.27. Without BaSrTiO3
layer, gate barrier is triangular. When there is BaSrTiO3 layer, because of high dielectric
constant of BaSrTiO3, field is lower in this layer to satisfy boundary condition. So, in this
case barrier is combination of trapezoidal barrier followed by triangular barrier. By
simple calculation, we can compute the gate leakage probability for both cases.
Figure 3.27: Gate barrier for (a) SrTiO3/GdTiO3 and (b) BaSrTiO3/ SrTiO3/GdTiO3
structures
66
When there is no high-k layer, tunneling probability can be calculated by FowlerNordheim tunneling approximation:
𝑇𝐹𝑁 = 𝑒
3
4√2𝑚∗ 𝜑2
𝑏
− 3𝑒𝐸
𝑆𝑇𝑂 ħ
… … … … … … … … … … … … .. (23)
Here, φB = barrier height of Schottky contact and ESTO is the field in the SrTiO3 layer.
When there is a high-k layer, tunneling happens in two steps. First there is a direct
tunneling through trapezoidal barrier and that can be expressed as:
3
3
2)
4√2𝑚∗ (𝜑2
−𝜑
1
2
𝑇𝐷 = 𝑒
−
3𝑒𝐸𝐵𝑆𝑇 ħ
… … … … … … … … … … … … .. (24)
Then there is a Fowler-Nordheim tunneling through triangular barrier that can be
expressed as:
𝑇𝐹𝑁 = 𝑒
3
4√2𝑚∗ 𝜑2
2
−
3𝑒𝐸𝑆𝑇𝑂 ħ
… … … … … … … … … … … … .. (25)
Here, ESTO and EBST are the electric field in SrTiO3 and BaSrTiO3 layer respectively.
Here φ1= φB = barrier height of Schottky contact and φ2= φB-q x EBST x tBST , where tBST
is the thickness of the BaSrTiO3 layer.
67
So we can calculate total tunneling probability combining Fowler-Nordheim and Direct
tunneling. The result is shown in figure 3.28, where we compared tunneling probability
for different BaSrTiO3 thickness. It is obvious that BaSrTiO3 layer improves gate leakage
and device with thick cap layer has lower gate leakage.
Figure 3.28: Tunneling probability of electron at gate barrier at different applied electric
field. Gate leakage can be reduced by using thicker BaSrTiO3 layer
68
This observation can also be verified from experimental results. In figure 3.29, we
compared the gate leakage of two device – device with high-k layer and device without
any high-k layer. For both devices cap thickness is 35nm, but in one device complete cap
is SrTiO3 and in another one there is 15nm of BaSrTiO3. But from figure it is clear that,
sample with BaSrTiO3 shows low gate leakage. BaSrTiO3 is reducing gate leakage as we
expected from our simple calculation.
Figure 3.29: Gate leakage characteristics for sample with and without BaSrTiO3 layer
69
Capacitance-Voltage (C-V) characteristics are shown for these two devices in figure 3.30.
BaSrTiO3 layer boosts the capacitance. Zero bias capacitance is almost double for high-k
device compared to GdTiO3/SrTiO3 HFET, though both devices have same cap thickness.
This high capacitance is due to high dielectric constant of BaSrTiO3. From C-V profile,
total charge modulation is 1.4x1014 cm-2. If we compare this results with our thickness
series study described earlier, this modulation is almost 40% higher than conventional
GdTiO3/SrTiO3 structure. The comparison is shown in figure 3.31.
Figure 3.30: Capacitance voltage characteristics. Charge modulation increased from
7.5x1013 cm-2 to 1.4x1014 cm-2 after using BaSrTiO3 layer
70
Figure 3.31: Charge modulation for different barrier thickness. BaSrTiO3 layer shows a
boost in charge modulation.
ID-VD characteristic is shown in figure 3.32. From figure we can see 65% modulation in
current that corresponds to 1.4x1014 cm-2 charge modulation. In figure 3.33, gm profile is
shown.
71
Figure 3.32: ID-VD profile of BaSrTiO3/SrTiO3/GdTiO3 transistor. Gate voltage is varied
from 0V to -10V. Total current modulation is 65%. Gate length is 1μm, Source to drain
spacing is 3.5μm and source to gate separation is 0.5μm
72
Figure 3.33: gm profile of BaSrTiO3/SrTiO3/GdTiO3 transistor. Drain bias is 5V. Gate
length is 1μm, Source to drain spacing is 3.5μm and source to gate separation is 0.5μm
73
Chapter 4: Perovskite oxide MESFET and FerroFET
In last two chapters, I discussed GdTiO3/SrTiO3 HFETs. In this chapter, I will introduce
two new device structures – MESFETs and FerroFETs. Because of very high 2DEG
density, it was difficult to pinch off transistor. So it was not possible to evaluate device
and material performance. But it is possible to pinch off MESFET easily. So, it is
possible to compare SrTiO3 with other materials for high power applications. Moreover
Ferroelectric gate material acts both as high-k gate dielectric and polarization switched
material. So we can observe higher modulation with hysteresis.
4.1 SrTiO3 MESFET
As we discussed in previous chapter, SrTiO3 has a very high breakdown field. This huge
breakdown field can be exploited for power electronics. But in traditional GdTiO3/SrTiO3
FET, it is very difficult to pinch off the device. As the origin of this 2DEG is electronic
reconstruction of the interface, it is very difficult to lower 2DEG charge density. So in
this chapter we will discuss about SrTiO3 Metal Semiconductor Field Effect Transistor
(MESFET).
For our study, we used sample of 100nm SrTiO3 grown on LSAT by MBE method
(figure 4.1). This sample was grown in oxygen deficient condition that creates oxygen
74
vacancies and made the SrTiO3 layer n-type. Doping density of the sample was in the
order of 1019 cm-3.
We processed this sample following the procedure described in chapter 2. Gate leakage
characteristic of MESFET is shown in figure 4.2. Gate current of MESFET is also
compared with conventional HFET with same SrTiO3 thickness. From this figure it is
very clear that gate leakage in MESFET is very low. Internal field due to 2DEG might
increase gate leakage in HFETs.
Figure 4.1: MESFET device structure
75
Figure 4.2: Gate leakage characteristic of HFET and MESFET with similar SrTiO3
thickness
Current reduces significantly after depositing gate. It is because of the depletion of
SrTiO3 layer by barrier height potential. ID-VD characteristic of transistor is shown in
figure 4.3. This figure shows clear pinch off in the device. Pinch off voltage is -3.5V. In
figure 4.4, ID-VG and Gm profiles are shown.
76
Figure 4.3: ID-VD profile of SrTiO3 MESFET. Gate voltage is varied from 0V to -4V.
Gate length is 1μm, Source to drain spacing is 3.5μm and source to gate separation is
0.5μm
77
Figure 4.4: gm profile of SrTiO3 MESFET and SrTiO3/GdTiO3 HFET with same SrTiO3
thickness. Drain voltage is 5V. Gate length is 1μm, Source to drain spacing is 3.5μm and
source to gate separation is 0.5μm
Capacitance voltage characteristic is shown in figure 4.5. SrTiO3 has field dependent
dielectric constant of form [77]:
𝜀(𝐸) =
𝐴𝜀0
√𝐵+𝐸 2
… … … … … … … … …. (1)
78
For this type of material, capacitance can be expressed as [77]:
1
𝐶2
=
2√𝐵
(𝑉𝑏𝑖
𝐴𝜀0 𝑞𝑁𝐷
− 𝑉) +
1
𝐴2 𝜀02
(𝑉𝑏𝑖 − 𝑉)2 … … … … … … … … … .. (2)
In figure 4.6, 1/C2 vs. VG is plotted. From the fitting of this curve we can get Vbi, ND, A
and B. From fitting we got ND=1019 cm-3, Vbi = 1.5V, A = 7.7938x107 and B =
1.4594x1011. In the following table these value are compared with literature.
This work
Literature [77]
A
7.7938x107
1.42x108
B
1.4594x1011
1.64x1011
Table 3: Constants of field dependent permittivity
As we know A and B from our experiment, we can plot field dependent dielectric
constant for SrTiO3. The profile is shown in figure 4.7 and we also compared it with
literature. Our result is lower than that of described in literature. This could be due to low
dielectric constant interfacial layer.
79
Figure 4.5: Capacitance-Voltage characteristics of SrTiO3 MESFET
80
Figure 4.6: 1/C2 versus gate voltage
Figure 4.7: Field dependent dielectric constant of SrTiO3. Red line (this work) and black
line [77]
81
To evaluate the prospect of SrTiO3 for high power application, we calculated Baliga
Figure of Merits (BFM) and Baliga High Frequency Figure of Merits (BHFFM). BFM
describes the resistive loss of the device and BHFFM describes switching loss. BFM and
BHFFM can be given by [79] –
3
𝐵𝐹𝑀 = 𝜀𝜇𝐸𝐵𝑅
… … … … … … … … … (3)
3
𝐵𝐻𝐹𝐹𝑀 = 𝜇𝐸𝐵𝑅
… … … … … … … … … (4)
To compare SrTiO3 as power electronics material, basic parameters of other conventional
materials are tabulated in the following table.
Si
Eg (eV)
1.12
GaN (Bulk)
[78]
3.4
GaN
[78]
3.4
(epi) 4H-SiC [78] SrTiO3
(this work)
3.26
3.25
Eps_r
11.9
9
9
10.1
24 (at 5.6 MV/cm)
Kth (W/K.m)
150
230
130
490
11
FBR (MV/cm)
0.3
3.3
2
2.2
5.6
Vsat
(107 1
cm/s)
Mobility
1350
(cm2/V-s)
3
3
2
0.03
1150
1150
900
10
BFM
1
850
190
223
97
BHFFM
1
98
36
45
48
Table 4: Baliga Figure of Merits (BFOM) for different materials
82
Based on the parameters we calculated BFM and BHFFM and those are shown in figure
4.8. This figure shows that figure of merits of SrTiO3 is already comparable to traditional
material. Moreover, we underestimate the parameters to calculate figure of merits of
SrTiO3. For example, we used break down field 5.6MV/cm. But it could be higher as we
discussed before. Moreover we used dielectric constant 25ε0. This value is for very high
field. For Ron, gate bias is zero and drain bias is also low, so dielectric constant is very
high during Ron. So we need better theory that can describe BFM for field dependent
dielectric constant materials and BFM will of course increase in that case.
Figure 4.8: BFOM and BHFFM of different materials
4.2 Ferroeletric FET
In ferroelectric material spontaneous polarization can be switched using a critical field.
Electric field versus polarization shows hysteresis loop below Curie temperature (fig.
83
4.9). Single crystal material shows higher hysteresis. This material could be used for
many applications, such as ferroelectric memory devices, Electro optic devices,
ferroelectric waveguides etc. S. Salahuddin et al. [16] predicted that ferroelectric material
could be used as gate dielectric material in FET to get differential negative capacitance.
This negative differential capacitance can be used to lower subthreshold swing below
60mV/decade. Recently A.I. Khan et al. [17] demonstrated first experimental evidence of
negative differential capacitance.
Figure 4.9: Hysteresis loop of ferroelectric materials [80]
To understand the effect of ferroelectric gate material, we simulated a HFET structure in
Silvaco. For simulation we used frictions material as channel, as field dependent
84
dielectric constant of SrTiO3 cannot be incorporated in Silvaco. The device structure of
simulation is shown in figure 4.10 (a). ID-VG profile of this device is shown in figure 4.10
(b). From this figure, we can see that threshold voltage is shifted while sweeping gate
bias in reverse direction. This shift in threshold voltage is because of polarization switch
in ferroelectric material due to gate bias.
Figure 4.10: (a) Simulated device structure (b) ID-VG characteristics of simulated
transistors. There is a shift in threshold voltage because of polarization inversion
To study the effect of ferroelectric gate, we use BaTiO3 as gate dielectric material.
BaTiO3 has a very high dielectric constant (over 1000ε0). It has critical field of 150
kV/cm and spontaneous polarization of 15μC/cm2 [81]. But it can vary for thin film.
85
Device structure of this experiment is shown in figure 4.11 (a). We used 15nm
BaTiO3/5nm SrTiO3/5nm SmTiO3 grown on LSAT substrate for this experiment.
SmTiO3 and GdTiO3 are electrically similar material and for this case we can consider
these two materials equal. Hall measurement shows 2DEG charge density of 2.2x1014 cm2
. Band diagram of the device is shown in figure 4.11 (b). In this figure, effect of
ferroelectricity on band diagram is also shown.
Figure 4.11: (a) Device structure of FerroFET (b) Effect of ferroelectricity on band
diagram
We used the process flow for device fabrication as described in figure 3.26. We used
Al/Ni/Au as ohmic contact and contact resistance is 8.1 Ω-mm. Contact resistance is
much higher as the surface is rough because of high power etching just before ohmic
metal deposition. Figure 4.12 is showing the Schottky behavior of the device. It shows
around 4 order rectification up to -7V.
86
Figure 4.12: Schottky diode characteristic of FerroFET
In figure 4.13, capacitance-voltage characteristic is shown. Zero bias capacitance is very
high ~ 9 μF/cm2. From C-V profile, Total charge modulation is 1.8x1014 cm-2 that is
highest for any material system till reported.
87
Figure 4.13: Capacitance-Voltage profile. Charge modulation in 1.8x1014 cm-2
In figure 4.14, ID-VD characteristic is shown. This figure shows 70% modulation in
current. ID-VG and gm profile is shown in figure 4.15.
88
Figure 4.14: ID-VD profile of SrTiO3 MESFET. Gate voltage is varied from 0V to -5V.
Gate length is 1μm, Source to drain spacing is 3.5μm and source to gate separation is
Figure 4.15: ID-VG and Gm profile of SrTiO3 MESFET. Drain voltage is 5V. Gate length
is 1μm, Source to drain spacing is 3.5μm.
89
As we are using ferroelectric gate, we are expecting hysteresis in C-V or ID-VG profile.
We observed a hysteresis when we measured C-V in both directions. It is shown in figure
4.16 (a). We also observed hysteresis in ID-VG profile. It is shown in figure 4.16 (b). As
we could not pinch off the device, we could not observe the effect of ferroelectric gate on
threshold voltage and subthreshold swing.
Figure 4.16: (a) Hysteresis in C-V profile (b) Hysteresis in ID-VG profile
90
Chapter 5: Summary and Future Work
In this work, for the first time GdTiO3/SrTiO3 HFET is demonstrated. A whole process
recipe is developed to fabricate this transistor. In this work, we found that interfacial
layer limits the charge modulation in such type of high electron density heterostructure.
We developed an analytical model to understand the effect of interfacial layer. We
demonstrated three mechanisms that can improve charge modulation. We observed
charge modulation up to 1.3x1014 cm-2 that is highest for any material system. We also
found that high breakdown field of SrTiO3 makes it a suitable candidate for power
electronics. We also reported the effect of ferroelectric gate on GdTiO3/SrTiO3 HFET.
We observed hysteresis in C-V and I-V profiles because of ferroelectric gate.
This work could be interesting for oxide based high power electronics. Moreover, this
high charge modulation technique could be used for Mott transition based transistors that
can allow subthreshold swing below 60mV/dec. Moreover, ferroelectric gate can
introduce negative differential capacitance that can be useful for low power electronics.
This high modulation could be integrated with microwave circuit for tunable plasmonic
waveguide. We can improve modulation further by using high-k dielectric gate with very
thin SrTiO3 layer (3~4nm).
91
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