Download Abstract - ICMAGMA

Topic Code:
Perpendicular Spin Orbit Torque Magnetic Random Access Memories
Jean-Pierre Nozières2, Gilles Gaudin1,2, Marc Drouard1,2, Ioan-Mihai Miron1, Olivier Boulle1, M.
Cubukcu1, C. Hamelin1, N. Mikuszeit1, T. Brächer1, N. Lamard3, M.-C Cyrille3, L. Buda-Prejbeanu1, K.
Garello4, P. Gambardella4, J. Langer5, B. Ocker5,
1
SPINTEC, CEA-INAC/CNRS/Univ. Grenoble Alpes, 38054 Grenoble, France, Grenoble, France.
2
Antaïos, F-38000, Grenoble, France, 3 CEA Leti, F-38000, Grenoble, France
4
Department of Materials, ETH Zurich, Hönggerbergring 64, CH-8093 Zürich, Switzerland
5
Singulus Technologies, Hanauer Landstr, 103, 63796, Kahl am Main, Germany
[email protected]
Abstract: Spin-Orbit Torque memory technology offers the promise of SRAM-speed with Flash non-volatility,
e.g. the capability to preserve data when power is turned off. There remains however a number of roadblocks to
be removed before the technology can be deemed to be ready for industrialization. We review here the latest
developments of SOT materials for magnetic field-free fast switching in perpendicular SOT bit cells.
Advanced processors require large amounts of
memory to save programs and data on-the-fly. There
is however a huge latency gap between the processor,
clocked at multi-GHz, and the main working memory
(aka. DRAM), which operates at 100s of MHZ at best.
The result is a a complex memory hierarchy,
involving multiple levels of memory cache (aka.
SRAM) and a complex data management. A memory
technology that would be fast enough to be embedded
within the processor core, yet dense enough to offer
increased on-chip capacity would be a major step
forward. If such can memory can have the added
benefit of being non-volatile to retain data when the
power is turned off, then it is becoming close to the
holy grail of memory technology.
Recently, we have proposed a novel memory concept,
named Spin-Orbit Torque Magnetic Random Access
Memory (SOT-MRAM) [1,2,3], that combines the
advantages of MRAM as an emerging non-volatile
memory technology, with a writing speed in the deep
sub-ns regime [4], compatible with the processor
multi-GHz frequency. Besides, unlike existing current
MRAM technologies, there is no write current (e.g.
voltage stress) flowing through the memory cell itself,
resulting in a truly infinite endurance. Moreover, read
and write can now be separately optimized to achieve
higher read speed, improved reliability and greater
process margins. Finally, with a similar core
technology (materials, process) as the recently
developed STT-MRAM, one can expect an easy path
to industrialization.
Bit-cell level proof of concept was performed using
state-of-the-art magnetic tunnel junctions using
(magnetically)
perpendicular
Ta/FeCoB/MgO
materials stack [3]. The basic write (e.g. switching)
and read (e.g. signal detection through Tunnel
Magneto-Resistance signal) operations have therein
been demonstrated in 100nm magnetic dots with
current pulse width down to 50ns.
We then demonstrated that deterministic bipolar
switching can be achieved using sub-500ps current
pulses, with a linear scaling of the critical current Ic on
pulse width p as 1/p [4]. Micromagnetic simulations
show that the reversal process is governed by a nucleation
/ propagation process, with domain nucleation at the edge
of the dot.
Fast switching of perpendicularly magnetized bit cells,
however, implies the presence of a static in-plane
magnetic field, in order to break the symmetry between
the final up (logic “1”) and down (logic “0”) states.
Getting rid of this external magnetic field is a prerequisite for memory applications. Several alternative
have been proposed to trigger fast switching in the
absence of an external magnetic field, amongst which
using non symmetric shapes of the magnetic dot.
Preliminary studies have shown that such approach is
indeed extremely efficient, yet final refinements will be
required in order to match product implementation
constraints.
Provided that solutions for field-less switching can be
implemented in “real” devices, SOT MRAM will be king
for applications where speed and endurance are key, such
as cache memories in high end Micro Processor Units,
from processor cores in PC and servers, to advanced
System-On-Chip in mobile applications (tablets, cell
phones, ...), replacing SRAM at a lower cost (e.g. silicon
area) with the added value of non-volatility (e.g. zero
standby power).
[1] G. Gaudin, I. M. Miron, P. Gambardella, and A.
Schuhl, Patents US12/899,072; US12/899,091;
US12/959,980
[2] I. M. Miron et al. , Nature 476, 189-193 (2011).
[3] M. Cubukcu et al., Appl. Phys. Lett. 104, 042406
(2014)
[4] K. Garello et al., Appl. Phys. Lett. 105, 212402
(2014)