Download a 500-nanosecond main computer memory utilizing plated

A 500-NANOSECOND MAIN COMPUTER MEMORY
UTILIZING PLATED-WIRE ELEMENTS
James P. McCallister and Carlos F. Chong
UNIVAC Division of Sperry Rand Corporation
Philadelphia, Pennsylvania
INTRODUCTION
6. A practical nondestructive readout
(NDRO) mode using identical read
and write word currents can be used
with plated wires, thereby permitting
faster cycle times and economical organization.
7. Plated-wire memories can be inexpensively constructed.
From its earliest use in digital data processing
systems, plated wire has shown great potential as a
practically ideal element for high-speed, randomaccess computer memories. 1 Some of the advantages
of the plated-wire element are as follows:
1. It can be manufactured in a continuous
process.
2. It can be tested in a continuous process.
3. It has a very rapid switching time,
about 80 nanoseconds, when driven
with a current pulse having a 40-nanosecond rise time.
4. Its output, when driven with a pulse
having a 40-nanosecond rise time, is
5 to 10 millivolts; this is sufficient to
permit practical sense-amplifier designs and good signal-to-noise ratios.
5. The word current is 800 milliamperes,
and the bit current is 40 milliamperes;
these are reasonable values for good
system design. Furthermore, the back
voltage on the drive lines is very small,
so that the power dissipation of the
driving circuits can be kept low.
Initial applications of the plated-wire element to
memories for aerospace use have successfully demonstrated many of these advantages; notably, the
switching time, the output, the low drive currents
with their associated low-power drive circuits, and
the NDRO mode.'2,3 Also, work has been reported
using the destructive readout mode/,5 and other
modes of operation. 6
This paper describes an engineering model of a
150,000-bit (16,384 words by 9 bits) plated-wire
memory. One-half of the maximum capacity was
constructed and tested.
REVIEW OF PLATED-WIRE PROPERTIES
The plated wires are made by electroplating an
iron-nickel alloy onto a beryllium-copper wire which
has first been electroplated with copper. The wire is
0.005 inch (0.13 millimeter) in diameter, and the
iron-nickel alloy is approximately 10,000 Angstroms
305
From the collection of the Computer History Museum (www.computerhistory.org)
306
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
thick. The wire is plated in the presence of a circumferential magnetic field which is generated by passing current through the wire. The result is an anisotropic magnetic structure that has an easy axis in the
circumferential direction.
To make use of the magnetic coating, a combination of circumferential and axial fields is used. The
circumferential field is produced by a current through
the plated wire; the axial field is produced by current
through a loop surrounding this wire (in practice,
many plated wires are surrounded by one loop). The
loop which carries the word current is referred to as
a word line, word strap, or solenoid. Each intersection of a plated wire and a word strap is a storage
cell for an information bit. Figure 1 is a simple representation of a plated-wire memory bit. The magnetization of the film can rest in either the clockwise
or counterclockwise sense of the circumferential easy
direction. These two senses represent the binary one
and binary zero identities of the information being
stored.
In reading, the plated wire serves as its own sense
line. The word current establishes an axial magnetic
field that causes the magnetization of the film to
rotate toward alignment with the axial field. This rotation changes the flux normal to the loop formed by
the sense wire and its ground return and causes a
voltage to be generated. The voltage generated may
be of either polarity, depending on the binary identity of the information stored in the wire. In the
NDRO mode, the film magnetization returns to its
original orientation when the word current is removed, thus completing the read cycle.
In writing, -the plated wire serves as its own bit
wire. At the same time that the magnetization vector
is partially rotated by a word-current field, a small
current is driven through the bit wire. This bit cur-
BIT CURRENT
BIT FIELD
FOR ONE
MAGNETIZATION VECTOR-ONE
STORED-REST POSITION
Figure 1. Information storage· on plated wire.
221-13
rent provides a circumferential field which steers the
magnetization to the proper sense. Writing is thus a
coincident-current operation in which the bit current
must be large enough to switch the film under the
active word strap but small enough not to switch the
films under the inactive word straps. Writing will be
successful as long as there is at least a minimum
time-overlap between the word and bit currents. The
magnitudes of the word and bit currents can be established by using the same principles applied to
planar thin films. 7,8
Because the individual bits are not physically discrete elements but are actually portions of a continuous magnetic cylinder, there is a tendency for interference between bits. This interference, which is reversible, occurs when information of the same polarity is repeatedly written into one bit cell. The bits
under adjacent word straps may be. reversed and
cause the wrong information to be read out. An effective technique has been devised to prevent this
interference. During a single write cycle, first the
complement· of the information is written, and then
the desired information. Thus, in every case, the
magnetic history of a particular bit is balanced in
ones and zeros, and no more than two write operations of the same polarity can occur consecutively at
anyone bit location.
LOGICAL ORGANIZATION OF THE MEMORY
SYSTEM
With the introduction of 21h D and other similar
core memory systems, various methods of address
selection in the bit and sense dimensions have come
into use. 9 The bit-sense matrix used in the memory
described herein is a highly efficient and economical
method for reducing the number of word lines. Figure 2a shows a 16,384-word memory of conventional word-organized design. Figure 2b shows the
modified· word-selection system which uses the bitsense matrix. The matrix consists of 144 switches
between the sense amplifiers and bit drivers on the
one side and the plated wires on the other. The function of the matrix is to route the desired signals from
the plated wires to the sense amplifiers and to route
the bit currents from the bit drivers to the desired
wires. The same switch serves both routing functions.
Each sense-amplifier, bit-driver combination is associated with 16 plated wires, one of which is selected
by the bit-sense matrix. The selection of one of the
16 switches is controlled by 4 bits of the address.
From the collection of the Computer History Museum (www.computerhistory.org)
A 500 NANOSECOND MAIN COMPUTER MEMORY
p..:......
9
READ
AMPLIFIERS
9
BIT
DRIVERS
I
I
9
PLATED
WIRES
I
----------i---------r·
I
I
I
1
rr
J IJ
I
SELECTION SYSTEM FOR
16,384 WORD STRAPS
o. Conventional
..........
.....
I
It
lL
1
1
1
1
9 LINES
9
READ
AMPLIFIERS
1
1
9 x 16
BIT-SENSE
MATRIX
SWITCHES
I
I
I
I
9x16=144
PLATED
WIRES
1
I
I
------1------
I
I
1
1
1
I
1
1
1
1
1
1
I
9
BIT
DRIVERS
I
I
i
I
II
281-27R2
J",
SELECTION SYSTEM
FOR 1024
WORD STRAPS
I
b. Modified
Figure 2. Block diagram of a conventional and a modified
word-organized memory.
307
Figure 3 is a block diagram of all elements of the
selection process. The complete memory array is arranged on four planes. Each plane contains 144
plated wires which intersect 256 one-turn word
straps; the 144 bits under each word strap comprise
16 words. Each word line is in series with a diode,
and all the word lines are arranged electrically into
a matrix. The selection lines (called A and B lines)
at opposite ends of the matrix are orthogonal to each
other. On each plane there are 16 B-selection lines
and 16 A-selection lines. Physically, two planes are
mounted to a single base plate, one on each side. On
each 2-plane assembly, 1 set of 16 A-lines serves
both sides, but there is a separate set of 16 B-lines
for each side. In the complete array of 4 planes, the
16 A-lines of each 2-plane assembly are driven by
separate sets of switches, which have identical inputs.
That is, the same A-line is selected on both assemblies simultaneously. Thus, logically, the 1024 wordline diodes are in a 64B-by-16A array, but electrically there are two 32B-by-16A arrays.
The bit-sense matrix consists of 144 W-selection
switches which connect 9 wires out of 144 to the .9
sense amplifiers and 9 bit drivers. The W-selection
switches are in turn driven by circuits which derive a
l-out-of-16 selection from 4 bits of the address.
OVERALL PACKAGING
Thus, what was basically a 16,384-by-9 stack becomes a 1024-by-16-by-9 stack. Also, the length of
the bit-sense line in the array is reduced by a factor
of 16, thus making large arrays a practicality. The
switch accommodates a bipolar bit current of approximately 40 milliamperes and sense signals of a
few millivolts without contributing noise. (The
switch circuit will be discussed later.) Because of the
NDRO mode, the action of the active word strap on
the 15 unselected wires per bit channel does not destroy information. The bit-sense circuits which would
otherwise be needed for regeneration are not required.
This memory organization is possible only with
an element which has NDRO characteristics for both
read word current and write word current. Its economy lies in the fact that a single switch element controls selection for both sense and bit drive functions
and thus requires an array with a common wire for
both functions. A small back voltage on the bit-sense
wire during the bit-writing pulse is desirable for sense
dimension recovery and for realizing the dual-function switch element.
Figure 4 is a front view of the complete memory
system, and Figure 5 is the rear view. The circuits
t4-BIT
ADDRESS
Figure 3. Selection system.
From the collection of the Computer History Museum (www.computerhistory.org)
308
PROCEEDING~FALL
JOINT COMPUTER CONFERENCE, 1966
MEMORY PLANE AND STACK
The memory plane design successfully meets three
different sets of requirements: mechanical, electrical,
and magnetic. In the first step of the construction of
the plane, oversize pilot wires are sandwiched between two sheets of Teflon*-coated Kapton*, the
Kapton being toward the outside. Heat and pressure
are applied, and the Tefl()n flows, conforming to the
wires. Next, the ground sheet, the spacer, the bottom
word~strap layer, the~ire sandwich, and the top
word-strap layer are laminated onto a unified assembly, as shown in Fig. 6. The pilot wires in the sandwich are then pulled out, leaving tunnels 0.008 inch
(0.2 millimeter) in diameter. Since the plated wires
used in the memory are 0.005jnch (0.13 millimeter)
in diameter, they can be inserted into the tunnels
easily with very little force.
The word straps are etched on a substrate of glass
epoxy. Separate sheets are used for the top and bottom, and the ends are soldered together to form a
* Registered trademarks
of the duPont Company.
Figure 4. Complete memory system-front view.
are assembled onto 6-inch-by-6-inch (15.3 centimeters by 15.3 centimeters) printed circuit boards.
The W-selection switches are assembled on special
oversized boards approximately 6 inches by 12
inches (15.3 centimeters by 30.5 centimeters). One
such board mounts all W-switches associated with
two sense amplifiers. A complete set for one sense
amplifier consists of 16 switches for the l-out-of-16
plated-wire selection plus one switch for a noisecanceling channel. Thus, each board holds 34
switches. These boards contain three copper layers:
signal, ground, and selection. Because the dielectric
between the signal and ground layers is very thin,
noise coupling into the signal paths is held to a low
value. The two assemblies containing the four planes
are mounted behind the main card library frame.
Connectors are mounted directly on each of the twoplane assemblies, which hold the printed circuit
boards for A-switch and B-switch selection of word
lines and associated circuits. The 144 plated-wire
circuits and the 9 noise-canceling wire circuits are
connected to the W-switch matrix boards by means
of the disconnectable cable assemblies shown at the
top of the picture.
Figure 5. Complete memory system-rear view.
From the collection of the Computer History Museum (www.computerhistory.org)
A 500 NANOSECOND MAIN COMPUTER MEMORY
309
Table 1. Electrically Significant Memory-Plane
Dimensions
KAPTON
Word-line spacing, center to center
Word-line width
Word-line solenoid thickness, inside,
face-to-face
Word-line conductor thickriess
Tupnel inside diameter
Plated-wire diameter
Tunnel spacing, center-to-center'
Plated wire spacing, center-to-center
ALUMINUM
GROUND PLANE
Figure 6. Memory-plane construction.
complete one-turn solenoid. The electrically significant dimensions are given in Table L
For every 16 magnetic wires, there is one nonmagnetic, noise-canceling' wire which serves as the
other half of a differential-input pair. In order to
avoid discontinuities in the magnetic structure, it is
necessary that the spacing of the magnetic wires not
be interrupted by the noise-canceling· wire. Therefore, the plated wires ar.e inserted into every other
tunnel, and the noise-canceling wires are inserted between two plated wires at appropriate intervals. Figure 7 is a closeup photograph of the wire termination
area of a plane and shows the plated wires ·on
O.030-inch (0.76 millimeter) centers soldered to
etched copper pads. Figure 8 is an overall photograph of one plane and shows the 256 word-line
diodes, the wire ends, and the active plane area.
Inches
Milli
meters
0.060'
0.040
1.52
1.02
0.011
0.0015
0.008 . .·
0.005
0.015
0.030
0.28
0.038
0.20
0.13
0.38
0.76
transistor emitter-follower output stage (Fig. 10) .
Worst-case turn-on and turn-off delays are each 10
nanoseconds.
A delay flop (Fig. 11) was designed. ,to' generate
.timing and control pulses. The . delay· period can be
varied from 40 to 250· nanoseconds by adjusting the
timing capacitor. The delay flop 'has the same input
and output loading as the inverter.
W ord.;.Selection Circuits
The word-selection circuits select 1 of 1024 wordline solenoids. Figure 12 is.a simplified diagram of
the word-selection system. A conventional diode matrix is selected by 16 A-switches and 64 B-switches.
A current regulator is used to supply a word current
of up to 1 ampere with a maximum rise time of 30
nanoseconds. A current sink quiescently accepts the
current from. the .current regulator during standby.
After an A-switch and a B-switch are turned on, the
current sink is turned off; as a result, the current
CIRCUITS
Logic and Control Circuits
The basic logic element chosen is a three-input
positive AND inverter (Fig. 9). It is a single-transistor DTL circuit. By adding. a diode gate structure
to the input, two-level AND/OR logic can be performed. Maximum dissipation is 285 milliwatts, and
worst-case delays are 10 nanoseconds for turn-on
and 14 nanoseconds for turn-off. Maximum input is
6, and maximum output is 31h logic loads plus 50
picofarads of capacity.
A 3-transistor, high-power amplifier was designed
to drive a maximum of 15 logic loads plus 250 picofarads of capacity. The circuit has a complementary
Figure 7. Closeup of wire termination area.
From the collection of the Computer History Museum (www.computerhistory.org)
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
310
Figure 8. Memory plane.
from the regulator is forced down the selected word
line via the· selected switches. The B-switch transistors are 2N3015, and the A-switch transistors are
2N3725. The word-line diodes are FD-6's.
Figure 13 is a schematic of the A-switch. Diodes
D 1, D2, and D3 form an input AND gate for a timing signal and two decoded and amplified address
signals. Transistors 01 and 02 are emitter-follower
CI
C2
R2
1.47K
V2
fl2V
VI
+3V
V2
+12V
Op
stages with the collector of 02 driven by the current
source.
Figure 14 is a schematic of the B-switch. Six bits
of the address are decoded into two groups of eight
outputs. One group is amplified and drives the bases
of the B-switch transistors. The other group is amplified and drives the emitters of the B-switch tran-
+~
+~
RI
154Sl
+--__-
01
02
INPUTS
[
VINJ\
-i4--+---<.....,~~..-~--t-I
R3
4.42K
V2
01'
02'
INPUTS
[
=
R2'
1.47K
-f4--+--4~~
-12V (f'C3
V3
~
NOTE:
ALL DIODES TYPE IN914
Figure 9. Inverter circuit.
-12V
V3
NOTE:
ALL DIODES lN914
RESISTANCE IS IN OHMS UNLESS
OTHERWISE SHOWN
Figure 10. High-power amplifier.
From the collection of the Computer History Museum (www.computerhistory.org)
OUTPUTS
A 500 NANOSECOND MAIN COMPUTER MEMORY
311
RI3
100
E2
+12Y
E3
H.IY
+ 15V
01
TIMING
OUTPUT
at
02
2N3015
ADDRESS [
NOTES:
ALL DIODES TYPE IN914
TRANSISTORS 01,02,04 ARE TYPE 2N30ll, 03 IS TYPE 2N3012
RESISTANCE IS IN OHMS UNLESS OTHERWISE SHOWN
03
~_---4-
02
2N3725
+3Y
-----1
Figure 11. Delay-flop circuit.
sistors. By matrixing in this way, the number of
transistors required in the B-switch system is reduced. One other input of the B-switch transistor is
a charging circuit. This charger is an emitter-follower
circuit that pulls the collector of Q 1 back up to 12
volts after the word current ends. One charger serves
the whole memory.
W-Matrix Switch (Bit-Sense Matrix)
The W-matrix switches are a set of gates between
the plated wires and the read amplifiers and bit
drivers. Because of the modified word-selection
structure described earlier, 16 words are energized
by each word-group line. During a read operation,
9 W-switch elements gate the 9 signals from 1 word
selected out of 16 into the read amplifiers. During
the write operation, the same elements gate the bipolar bit currents into the desired plated wires. The
W-switch matrix element consists of two complementary transistors, as shown in Fig. 15. When a
AOO
AOI
A02
16
A-SWITCHES
A03
-3V
'---~Ir---...../
circuit is selected, turn-on currents are applied to the
bases of both transistors. The PNP transistor, when
thus selected, has a collector-to-emitter drop of 1 to
2 millivolts and a dynamic resistance of 18 ohms.
For a write operation, the PNP transistor conducts
the positive bit current, and the NPN transistor conducts the negative bit current.
Read Amplifier
There are four different causes of a DC shift,
which operates on the signal as it enters the read
amplifier. These causes are listed as follows:
1. The W-switch adds a DC offset voltage
directly.
2. The average value of the actual signal
beyond the switch is not zero, since the
wire output is switched into the amplifier only part of the time.
3. The writing process impresses a very
large, non,...zero-average voltage on the
amplifier terminals.
I
I
AI7
I
I
'"
r
L
_ - - T O A-SWITCHES
+=
WORD - LINE DIODE
(TYPE FD -6666)
WORD
LINE
- - - TO B - SWITCHES
Figure 12. Word-line selection system.
32
WORD-LINE
DIODES
Figure 13. A-switch circuit.
I
. ---+--I
FROM
CURRENT
SOURCE
i
ADDRESS
AMPLIFIER
16
WORD LINES
ADDRESS
PREAMPLIFIER
Figure 14. B-switch circuit.
From the collection of the Computer History Museum (www.computerhistory.org)
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
+12V
TO READ
AMPLIFIER!
BIT DRIVER
-12V
+12V
SELECT LINES
NOTES:
TRANSISTOR Qt SIMILAR TO TYPE 2N30tt,
Q2 SIMILAR TO TYPE 2N30t2
DIODES TYPE tN914
Figure 15. Bit-sense matrix circuit.
4. The sense line itself takes a significant
amount of time to recover completely
from the bit current.
Several configurations of read-amplifier design
were tried in which AC coupling, noise-protection
switches, common-mode rejection chokes, and other
devices were used. The most successful design, and
the one used in this model, employs a DC differential-input amplifier followed by a DC restorer. The
DC restorer might more properly be. called a DC
corrector. Its function is to shift the amplifier output
so that just prior to readout the amplifier is at zero
reference level regardless of any DC shifts which
may actually exist at the input.
Figure 16 is a block diagram of the complete bit
dimension circuitry associated with each of the nine
bit-channels. It was found convenient to package all
elements shown in this diagram on a single-printed
circuit board, one board for each bit channel. This
made a considerable reduction in backboard wiring,
noise pickup, and wiring delays. A single register
serves for either input or output information. During
write cycles, the contents of the register are gated
against two timing signals to generate first the complement writing pulse and then the normal writing
pulse, as described earlier. These two timing signals
are referred to as Phase 1 and Phase 2, respectively.
During read cycles, the one-zero decision is made
by applying the signal and a 20-nanosecond-wide
strobe pulse to 2 transistors with a common collector
resistor. If both transistors cut off, an output results.
Preceding this stage are the DC amplifier and DC
restorer, previously described.
Because of the bipolar wire output signal, the
strobed detector can be biased very close to a zerovoltage input, so that a one-signal will trip the detector, while a zero-signal will reverse and provide
noise protection. Hence, the AC signal-to-noise ratio
is quite good and permits the use of high-gain sense
amplifiers. A limitation on gain does exist, however,
because of the following constraints:
The DC restoration process unavoidably
introduces some noise, which must be
kept small compared with the signal
level at the restorer. This calls for gain
ahead of restoration.
DC offsets (or DC noise) at the input
must not drive the amplifier out of linearity ahead of the DC restorer. This
limits gain ahead of the restorer to less
(total output range
)
h
t an
total DC input noise range •
Thus, the signal-to-noise ratio at the detector will be
expressed as
signal pulse amplitude X gain ahead of restorer
noise introduced by DC restorer
Gain following the restorer cannot improve this ratio.
Figure 17 is a schematic of the amplifier and DC
restorer. The amplifier has a differential gain of 52
decibels, with an 8-megahertz cutoff frequency. The
common-mode-rejection ratio at 10 megahertz is 46
decibels. The amplifier output continuously charges
capacitor C1 through its own low impedance plus
that of the restorer transistor, Q8, which is turned
on. Just prior to the time a signal is expected, Q8 is
DATA
OUT
DATA
IN
FROM
PLATED
WIRE
-+_+---.
FROM NOISE
CANCELLING - . . - - - - - '
WIRE
Figure 16. Block diagram of bit dimension circuitry.
From the collection of the Computer History Museum (www.computerhistory.org)
A 500 NANOSECOND MAIN COMPUTER MEMORY
+12V
+12V
C2~+12V
3.31'F
56K
OUTPUT
Q9
61.9
-3V
L~========::t=======-.J
+12V
NOTE:
~~~EN~~361~~NSISTORS
ARE
UNLESS OTHERWISE SHOWN
RESISTANCE IS IN OHMS.
Figure 17. Read amplifier and DC restorer.
turned off, and all variations in output are transmitted to the next stage. While Q8 is on, the time
constant of Cl is less than 5 nanoseconds; while Q8
is off, the time constant is 1 microsecond. Capacitor
C2 was necessary to isolate the DC conditions of Q9,
and as such is a compromise in performance. Variations in waveshape cause DC shifts on this capacitor
which are equivalent to a I-millivolt input signal. In
operation, the overall signal-to-noise ratio is typically 5: 1.
The test includes simple operation, nondestructive
readout operation in the presence of many disturbs,
and operation in the presence of adjacent-bit disturbs. After a normalizing history, every other bit
along each wire is written one time. These are called
test bits, and those which are skipped are called
adjacent bits. The test bits are never again written
during a given test. A fourfold cycle of passes
through the memory is continued indefinitely: A first
pass reads all bits, the second pass writes adjacent
bits to be the same as the test bits, the third pass
reads all bits, and the fourth pass writes adjacent
bits to be opposite from test bits. In this manner, the
cycle is continued.
The system operated successfully with this set of
patterns for extended periods of time representing
many millions of word disturbs and bit disturbs on
every test bit. It was also used successfully for several months as a main store for a small computer.
CONCLUSIONS
The construction and operation of the memory
system described indicate that such a system is indeed a practicality. It seems a certainty that plated
wire memories will become a very important member
in the hierarchy of storage systems to be used in the
computers of tomorrow.
SYSTEM OPERATION
Figure 18 is a timing diagram of the system functions. The basic objective was to perform noisy operations as quickly as possible, so that the wire
output signals could occur at a quiet time. No objectionable noise is introduced by the rise of the word
current proper. The most sense-line noise is caused
by turning on the B-switch, which moves 16 wordline solenoids through a large voltage excursion, and
by turning on the low-level W-matrix switch, where
momentary unbalances in base current during tumon become a direct input to the amplifier. When
operated and tested, the memory had a 500-nanosecond cycle time and a 300-nanosecond access time.
The limitations on cycle time in this unit are almost
entirely in the circuits. In every case techniques are
now available to improve upon the demonstrated
performance.
TEST AND RESULTS
313
TIME (NANOSECONDS)
o
100
200
300
400
500
START
W-SWITCH
a-SWITCH
A-SWITCH I - - - - J
IW~----
Ial-----~
,,'-....... ) -_ _ _ _ _ _ _ _
SIGNAL 1--_ _ _""'<
AT WIRE
STROBE
AT GATE
~
~_ _ _ _ _ _.... _-------~
INFORMATION
OUTPUT I--_ _ _ _ _ _ _.J
GATE
Figure 19 shows the test pattern sequence which
is the worst-case for the memory system described.
407-.0
Figure 18. Timing diagram of system functions.
From the collection of the Computer History Museum (www.computerhistory.org)
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
314
1. HISTORY:
ALL I's
ALL I O's
:
I
ALL I's
ALL O's
2. LOAD:
(TEST BITS ONLY)
WRITE I
lit
t
ttl
I
3. TEST:
READ I 0 I 0 I 0 I
WRITE
ttl
[ READ t ttl til
WRITE
0 0 0
0 I 0 I 0 lOt
tIl I
Itt 1 ttl t
0 0 0 0
0 I ------I -----t t -----0 -------
READ tOt 0 tOt 0 lOt 0 tOt 0 t ------WRITE
I t I t I I t I ------[ READ ttl t I I I I I t I I Itt I I -------
TESTW~:: J J J J J J J J L~~~~~~~
JO JO JO JO JO JO JO JO
ADJACENT BITS
POSITION ALONG WIRE
Figure 19. Worst-case test pattern.
ACKNOWLEDGMENTS
The significant contributions to this work are too
numerous to list. However, we especially wish to
acknowledge the work of Dr. J. S. Mathias, who
made the wire; Mr. G. R. Reid, who was responsible
for the design and construction of the planes; Mr. P.
Zakarian, who did much of the circuit-design work;
and Messrs W. J. Bartik and G. A. Fedde, under
whose direction the project resulting in this memory
was undertaken.
REFERENCES
1. T. R. Long, "Electrodeposited Memory Elements for a Nondestructive Memory," l. Appl.
Physics, vol. 31, p. 123S (1960).
2. G. A. Fedde, "Design of a 1.5 Million-Bit
Plated-Wire Memory," Proc. Eleventh Annual Conf.
on Magnetism and Magnetic Materials, l. Appl.
Phys., vol. 37, pp. 1373-75 (1966).
3. - - , and G. H. Guttroff, "A Reliable Very
Low Power Plated Wire Spacecraft Memory," Proc.
National Electronics Conference, vol. 20, pp. 681-86
(1964) .
4. H. Maeda and A. Matshushita, "Woven ThinFilm Wire Memories," Proc. Intermag. Conference,
Apr. 1964, pp. 8-1-1 to 8-1-6.
5. T. R. Finch and S. Waaben, "High-Speed
DRO Plated-Wire Memory System," Proc. Intermag.
Conference, Apr. 1966, paper 12.3.
6. M. Bienhoff, J. Camarata and M. Sherman,
"Some Considerations in the Design of Plated Wire
Memory Systems," Proc. IEEE National Symposium
on Batch Fabrication, Apr. 1965, pp. 88-102.
7. A. V. Pohm and E. N. Mitchell, "Magnetic
Film Memories, A Survey," I.R.E. Trans. on Electronic Computers, EC-9, p. 308 (1960).
8. H. J. Oguey, "Theoretical Hysteresis Loops of
Thin Magnetic Films," Proc. of I.R.E., vol. 48,
p. 1165 (1960).
9. T. J. Gilligan and P. B. Persons, "High Speed
Ferrite 2~D Memory," Proc. Fall loint Computer
Conf., 1965, pp. 1011-21.
BIBLIOGRAPHY
Fedde, G. A., "A Low Power Plated-Wire Memory
System," Sperry Engineering Review, Fall 1965,
pp.19-22.
Bartik, W. J., C. F. Chong and A. Turczyn, "A 100Megabit Random Access Plated-Wire Memory," Proc. Intermag. Conference, Apr. 1965,
pp. 11.5-1 to 11.5-7.
Danylchik, I., A. J. Perneski and M. W. Sagal,
"Plated Wire Magnetic Film Memories," Proc.
Intermag. Conference, Apr. 1964, pp. 5-4-1 to
5-4-6.
Oshima, S., K. Futami and T. Kamibayashi, "The
Plated Wire Memory Matrix," ibid, pp. 5-1-1
to 5-1-6.
From the collection of the Computer History Museum (www.computerhistory.org)