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Chapter
p
1
Introduction to CMOS Circuit
Design
Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Department of Electrical Engineering
N
National
l Central
C
l University
U
Jhongli, Taiwan
Outline
†
†
†
†
Introduction
MOS Transistor Switches
CMOS Logic
Ci
Circuit
i and
d System Representation
R
i
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
2
Binary Counter
a
Present
state
Next state
a
b
A
B
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
A = a’b + ab’
B = a’b’ + ab’
A
b
B
CK
CLR
Source: Prof. V. D. Agrawal
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
3
1-bit Multiplier
A
C
B
C=AxB
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
4
Switch: MOSFET
† MOSFETs are basic electronic devices used
to direct and control logic signals in IC design
„ MOSFET: Metal-Oxide-Semiconductor FieldEffect Transistor
„ N-type MOS (NMOS) and P-type MOS (PMOS)
„ Voltage-controlled
g
switches
† A MOSFET has four terminals: gate, source,
drain and substrate (body)
drain,
† Complementary MOS (CMOS)
„ Usin
Using two
t
types
t p s of
f MOSFETs tto create
t logic
l i
networks
„ NMOS & PMOS
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
5
Silicon Lattice and Dopant Atoms
† Pure silicon consists of a 3D lattice of atoms
„ Silicon is a Group
p IV element and it forms covalent
bonds with four adjacent atoms
„ It is a poor conductor
† N-type (P-type) semiconductor
„ By introducing
ntroduc ng small amounts of Group V
V-As
As (Group
III-B) into the silicon lattice
Si
Si
Si
Si
Si -
Si
Si
Si
Si
Si
Si
+
As
Si
Si
Si
Si
Si
Si
Si
Lattice
L
tti of
f pure
Silicon
Advanced Reliable Systems (ARES) Lab.
Lattice
L
tti of
f N-type
N t
Semiconductor
Jin-Fu Li, EE, NCU
Si
Si
Si
+
B
Si
Si
Si
Si
Lattice
L
tti of
fP
P-type
t
Semiconductor
6
P-N Junctions
† A junction between p-type and n-type
semiconductor forms a diode.
† Current flows only in one direction
p-type
p
yp
n-type
yp
anode
cathode
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
7
NMOS Transistor
† Four terminals: gate, source, drain, body
† Gate
Gate–oxide–body
oxide body stack looks like a capacitor
„
„
„
„
Gate and body are conductors
SiO2 ((oxide)) is a very
y good
g
insulator
Called metal–oxide–semiconductor (MOS) capacitor
Even though gate is no longer made of metal
Source
Gate
Drain
Polysilicon
SiO2
n+
n+
p
Advanced Reliable Systems (ARES) Lab.
bulk Si
Jin-Fu Li, EE, NCU
8
NMOS Operations
† Body is commonly tied to ground (0 V)
† When the gate is at a low voltage:
„ P-type body is at low voltage
„ Source-body
Source body and drain-body
drain body diodes are OFF
„ No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
Advanced Reliable Systems (ARES) Lab.
D
bulk Si
Jin-Fu Li, EE, NCU
9
NMOS Operations (Cont.)
† When the gate is at a high voltage:
„
„
„
„
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n
n-type
type
Now current can flow through n-type silicon from
source through channel to drain,
dra n, trans
transistor
stor iss ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
Advanced Reliable Systems (ARES) Lab.
D
bulk S
bu
Si
Jin-Fu Li, EE, NCU
10
PMOS Operations
† Similar, but doping and voltages reversed
„
„
„
„
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
Advanced Reliable Systems (ARES) Lab.
bulk Si
Jin-Fu Li, EE, NCU
11
Threshold Voltage
† Every MOS transistor has a characterizing
parameter called the threshold voltage VT
† The specific value of VT is established during
the manufacturing process
† Threshold voltage of an NMOS and a PMOS
NMOS
PMOS
VA
Drain
VDD
Gate
Mn
VA +
VGSn
GS
Source
VA=1
Mn On
VTn
0
Gate-source voltage
VGSp
Advanced Reliable Systems (ARES) Lab.
VA Gate
VA=0
Mn Off
Logic translation
VA
Source
+ VDD
Mp
VDD
VDD-|VTp|
Drain
Gate-source voltage
Jin-Fu Li, EE, NCU
0
VA=1
Mp Off
VA=0
Mp On
Logic translation
12
MOS Transistor is Like a Tap…
Source: Prof. Banerjee, ECE, UCSB
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
13
MOS Switches
† NMOS symbol and characteristics
Vth
5v
5v
0v
5v-Vth
0v
† PMOS symbol
y
and characteristics
0v
Vth
5v
5v
0v
Advanced Reliable Systems (ARES) Lab.
Vth
Jin-Fu Li, EE, NCU
14
CMOS Switch
† A complementary CMOS switch
„ Transmission gate
-s
Symbols
a
C
b
s
a
-s
b
a
b
s
s
0v
5v
Characteristics
5v
0v
0v
5v
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
15
CMOS Logic-Inverter
† The NOT or INVERT function is often
considered the simplest
p
Boolean operation
p
„ F(x)=NOT(x)=x’
Vin
Vout
Vdd
0
Vdd
Vin
Vout
Vdd
1
1
Advanced Reliable Systems (ARES) Lab.
Vdd
0
Vdd/2
Jin-Fu Li, EE, NCU
Indeterminate
logic level
16
Combinational Logic
† Serial structure
a
S1=0
S2 0
S2=0
S1=0
S2 1
S2=1
S1=1
S2 0
S2=0
S1=1
S2 1
S2=1
S1
0
S1
1
0 a!=b
a!=b
1 a!=b
a=b
S2
S2
b
a
S1=0
S2=0
S2
0
S1=0
S2=1
S2
1
S1=1
S2=0
S2
0
S1=1
S2=1
S2
1
S1
S1
0
1
0
a=b
a!=b
1
a!=b
a!=b
S2
S2
b
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
17
Combinational Logic
† Parallel structure
S1=0
S2=0
a
S1=0
S2=1
S1=1
S2=0
S1=1
S2=1
S1
0
S1
S2
1
0 a!=b
a=b
1
a=b
S2
a=b
b
S1=0
S2=0
S2
0
a
S1=0
S2=1
S2
1
S1=1
S2=0
S2
0
S2
S1
S1=1
S2=1
S2
1
S1
0
1
0
a=b
a=b
1
a=b
a!=b
S2
b
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
18
NAND Gate
Output
A
0
1
0
1
1
1
1
0
A
B
B
A
B
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Output
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19
NOR Gate
A
A
B
0
1
0
1
0
1
0
0
Output
B
A
B
Advanced Reliable Systems (ARES) Lab.
Output
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20
Compound Gate
† F = (( AB ) + (CD ))
A
C
B
A
B
D
F
A
C
B
D
Advanced Reliable Systems (ARES) Lab.
C
D
Jin-Fu Li, EE, NCU
F
21
Structured Logic Design
† CMOS logic gates are intrinsically inverting
„ The output always produces a NOT operation
acting on the input variables
† For example
example, the inverter shown below
illustrates this property
1
a=1
VDD
f=0
0
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
22
Structured Logic Design
† The inverting nature of CMOS logic circuits
allows us to construct logic circuits for AOI
and OAI expressions using a structured
approach
† AOI logic function
„ Implements the operations in the order AND then
OR then NOT
„ E.g.,
E g g ( a , b , c , d ) = a .b + c .d
† OAI logic function
„ Implements the operations in the order OR then
AND then NOT
„ E.g.,
E g g ( a , b, c, d ) = (a + b ) ⋅ (c + d )
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
23
Structured Logic Design
† Behaviors of nMOS and pMOS groups
„ Parallel
Parallel-connected
connected nMOS
† OR-NOT operations
„ Parallel-connected pMOS
p
† AND-NOT operations
„ Series-connected nMOS
† AND-NOT operations
„ Series-connected pMOS
† OR-NOT operations
† Consequently, wired groups of nMOS and
pMOS are logical duals of another
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
24
Dual Property
† If an NMOS group yields a function of the form
g = a ⋅ (b + c )
then an identically wired PMOS array gives the
dual function
G = a + (b ⋅ c )
where
h
the
h AND and
d OR operations
i
h
have b
been
interchanged
† This
h is an interesting property of
f NMOS-PMOS
NM
PM
logic that can be exploited in some CMOS designs
Advanced Reliable Systems (ARES) Lab.
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25
An Example of Structured Design
† X = a + b ⋅ (c + d )
VDD
c
b
d
a
Group 2
Group 1
X
b
Group 3
a
c
Advanced Reliable Systems (ARES) Lab.
d
Jin-Fu Li, EE, NCU
26
An Example of XOR Gate
† Boolean equation of the two input XOR gate
„ a ⊕ b = a ⋅ b + a ⋅ b, this is not in AOI form
„ But, a ⊕ b = a ⋅ b + a ⋅ b, this is in AOI form
„ Therefore,
Therefore a ⊕ b = ( a ⊕ b ) = a ⋅ b + a ⋅ b
VDD
a
VDD
b
•
a
•
•
a
b
•
b
a
b
a⊕b
•
•
•
•
a⊕b
a
a
a
a
b
b
b
b
XOR Gate
Advanced Reliable Systems (ARES) Lab.
XNOR Gate
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27
Multiplexer
A
B
1
0
Y
Y
S S0
S1
S
S
-S
A
A
Y
S
11
10
01
00
A
B
C
D
B
Y
C
B
-S
D
S1
S
Advanced Reliable Systems (ARES) Lab.
-S1
Jin-Fu Li, EE, NCU
S0
-S0
28
Static CMOS Summary
† In static circuits at every point in time (except
when switching),
g), the output
p is connected to
either Vdd or Gnd through a low resistance path
„ Fan-in of n (or n inputs) requires 2n (n N-type and n Ptype) devices
† Non-ratioed logic: gates operate independent of
PMO or NMOS
PMOS
NMO sizes
i
† No path ever exists between Vdd and Gnd: low
static power
† Fully-restored logic (NMOS passes “0” only and
PMOS passes “1” only
† Gates must be inverting
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
29
Circuit and System Representations
† Behavioral representation
„ Functional,
Functional high level
„ For documentation, simulation, verification
† Structural representation
„
„
„
„
„
System level – CPU, RAM, I/O
Functional level – ALU,
ALU Multiplier,
Multiplier Adder
Gate level – AND, OR, XOR
Ci
Circuit
it level
l
l – Transistors,
T
sist s R,
R L,
L C
For design & simulation
† Physical
Ph i l representation
i
„ For fabrication
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
30
Behavior Representation
† A one-bit full adder (Verilog)
module fadder(sum,cout,a,b,ci);
output sum, cout;
i
input
a, b,
b ci;
i
reg sum, cout;
ci
always @(a or b or ci) begin
sum = a^b^ci;
cout = (a&b)|(b&ci)|(ci&a);
end
endmodule
Advanced Reliable Systems (ARES) Lab.
b
a
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fadder
cout
sum
31
Structure Representation
† A four-bit full adder (Verilog)
b
a
module adder4(s,c4,a,b,ci);
(
)
output[3:0] sum;
output c4;
a[0]
b[1] a[2]
b[2] a[3]
b[3]
b[0] a[1]
input[3:0] a,
a b;
co[1]
co[2]
co[0]
input ci;
ci
a0
a1
a2
a3
reg[3:0] s;
s[0]
s[1]
s3]
s[2]
reg c4;
wire[2:0] co;
s
adder4
adde
fadder a0(s[0]
a0(s[0],co[0],a[0],b[0],ci);
co[0] a[0] b[0] ci);
fadder a1(s[1],co[1],a[1],b[1],co[0]);
fadder a2(s[2],co[2],a[2],b[2],co[1]);
fadder a3(s[3],c4,a[3],b[3],co[2]);
endmodule
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
32
Physical Representation
† Layout of a 4-bit NAND gate
Vdd
Vdd
in1
in2
in3
in1
Out
in4
Out
in2
in3
in4
Gnd
in1 in2
in3 in4
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
33
Design Flow for a VLSI Chip
S
Specification
ifi ti
Function
Behavioral Design
Function
Structural Design
Function
Timing
Power
Physical Design
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
34