Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
CCD77-00 Back Illuminated High Performance IMO Device FEATURES * 512 by 512 Image Format * Image Area 12.3 x 12.3 mm * Full-Frame Operation * 24 mm Square Pixels * Back Illuminated for High Quantum Efficiency * Low Noise Output Amplifiers * 100% Active Area * Inverted Mode Operation APPLICATIONS * Spectroscopy * Scientific Imaging * Star Tracking * Medical Imaging INTRODUCTION TYPICAL PERFORMANCE The CCD77 family of sensors are full-frame devices with readout registers above and below the image section. The top register, image section and bottom register are designated A, B and C respectively. Each register has a single output at one end and a charge injection structure at the other end for test purposes. Standard three-phase clocking and buried channel charge transfer are employed. The image section of the device operates in inverted mode for minimum dark current. To maximise the dynamic range, the CCD is manufactured without anti-blooming structures. The e2v technologies back thinning process ensures high quantum efficiency over a wide range of wavelengths. Several different anti-reflection coatings are available to suit a range of applications. Designers are advised to consult e2v technologies should they be considering using CCD sensors in abnormal environments or if they require customised packaging. Maximum readout frequency Output responsivity . . . Peak signal . . . . . . Dynamic range (at 20 kHz) . Spectral range . . . . . Readout noise (at 20 kHz) . . . . . . . . . . . . . . . . . 7 MHz . . . . 2.5 mV/e7 . . . 300 ke7/pixel *100 000:1 200 – 1060 nm . . . . 3.0 e7 rms . . . . . . . . . 12.3 x 12.3 . . . 512 . . . 512 . . 24 x 24 GENERAL DATA Format Image area . . Active pixels (H) (V) Pixel size . . . . . . . . . . . . . . . . . . . Number of output amplifiers mm mm . . . . . . . . . . 2 15 additional pixels are provided for over-scanning purposes in each register. Package Package size . . . . . . Number of pins . . . . . Inter-pin spacing . . . . Inter-row spacing . . . . Window material . . . . Type . . . . . . . . Weight (approx, no window) . . . . . . . . . . . . . . . . . . . . . 22.6 x 29.9 mm . . 24 . . . 2.54 mm . . 22.86 mm . . removable glass . ceramic DIL array . . . 6 g e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU, UK Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492 e-mail: [email protected] Internet: www.e2v.com Holding Company: e2v technologies plc e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148 e-mail: [email protected] # e2v technologies (uk) limited 2006 A1A-100034 Issue 4, March 2006 411/9572 PERFORMANCE Min Typical Max e7/pixel Peak charge storage (see note 1) 300k 350k – Peak output voltage (no binning) – 875 – mV Dark signal at 293 K (see notes 2 and 3) – 700 1500 e7/pixel/s Dynamic range (see note 4) – 100 000:1 – Charge transfer efficiency (see note 5): parallel serial – – 99.9999 99.9993 – – Output amplifier responsivity (see note 3) 1.8 2.5 % % mV/e7 3.5 3.0 7 Readout noise at 253 K (see notes 3 and 6) – 5.0 Maximum readout frequency (see note 7) – 1000 7000 kHz Dark signal non-uniformity at 293 K (std. deviation) (see notes 3 and 8) – 175 375 e7/pixel/s Output node capacity – – electrons 600k rms e /pixel Spectral Response (at 253 K) Wavelength (nm) Minimum Response (QE) (all Basic Process) Midband Coated Broadband Coated Uncoated Maximum Response Non-uniformity (1s) 350 15 25 10 5 % 400 40 55 25 3 % 500 85 75 55 3 % 650 85 75 50 3 % 900 30 30 30 5 % The uncoated process is suitable for soft X-ray and EUV applications. NOTES 1. Signal level at which resolution begins to degrade. 2. Measured between 253 and 293 K and VSS +9.5 V typically. Dark signal at any temperature T (kelvin) may be estimated from: Qd/Qd0 = 1.14 x 106T3e79080/T where Qd0 is the dark signal at T = 293 K (20 8C). 3. Test carried out at e2v technologies on all sensors. 4. Dynamic range is the ratio of full-well capacity to readout noise measured at 253 K and 20 kHz readout speed. 5. CCD characterisation measurements made using charge generated by X-ray photons of known energy. 6. Measured using a dual-slope integrator technique (i.e. correlated double sampling) with a 20 ms integration period. 7. Readout at speeds in excess of 7 MHz can be achieved but performance to the parameters given cannot be guaranteed. 8. Measured between 253 and 293 K, excluding white defects. BLEMISH SPECIFICATION Traps Pixels where charge is temporarily held. Traps are counted if they have a capacity greater than 200 e7 at 253 K. Slipped columns Are counted if they have an amplitude greater than 200 e7. Black spots Are counted when they have a signal level of less than 80% of the local mean at a signal level of approximately half full-well. 100034, page 2 White spots White column Black column Are counted when they have a generation rate 50 times the specified maximum dark signal generation rate (measured between 253 and 293 K). The typical temperature dependence of white spot defects is different from that of the average dark signal and is given by: Qd/Qd0 = 122T3e76400/T A column which contains at least 9 white defects. A column which contains at least 9 black defects. GRADE 0 1 2 Column defects: black or slipped white 0 0 2 0 6 1 Traps 4200 e7 2 5 10 White spots 20 30 100 Black spots 20 30 60 Grade 5 Devices which are fully functioning, with image quality below that of grade 2, and which may not meet all other performance parameters. Note The effect of temperature on defects is that traps will be observed less at higher temperatures but more may appear below 253 K. The amplitude of white spots and columns will decrease rapidly with temperature. # e2v technologies TYPICAL OUTPUT CIRCUIT NOISE 8026 18 16 NOISE EQUIVALENT SIGNAL (e— rms) 14 12 10 8 6 4 2 0 10k FREQUENCY (Hz) 50k 100k 500k 1M 5M TYPICAL SPECTRAL RESPONSE 100 8012 90 BASIC MIDBAND COATED 80 BASIC BROADBAND COATED 70 60 BASIC UNCOATED 50 40 QUANTUM EFFICIENCY (%) 30 20 10 0 200 300 400 500 600 700 800 900 1000 1100 WAVELENGTH (nm) # e2v technologies 100034, page 3 TYPICAL VARIATION OF DARK SIGNAL WITH SUBSTRATE VOLTAGE AT 20 8C 106 8035 105 TYPICAL RANGE DARK SIGNAL (e7/pixel/s) 104 103 102 0 1 2 SUBSTRATE VOLTAGE (V) 3 4 5 6 7 8 9 10 11 12 TYPICAL VARIATION OF DARK SIGNAL WITH TEMPERATURE (VSS = +9.5 V) 104 8034 103 102 DARK SIGNAL (e7/pixel/s) 10 1 1071 1072 740 720 PACKAGE TEMPERATURE (8C) 100034, page 4 0 20 40 # e2v technologies DEVICE SCHEMATIC 8033 IDA 1 24 OSA B13 2 23 B11 TGA 3 A13 4 21 B12 OG 5 20 IG A REGISTER 512 + 15 ELEMENTS 6 22 TGC 19 IMAGE (B) SECTION 512 x 512 PIXELS SS 7 18 SS 1R 8 17 C13 A12 9 16 C12 A11 10 C REGISTER 512 + 15 ELEMENTS 15 C11 OD 11 14 RD OSC 12 13 IDC # e2v technologies 100034, page 5 CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS PIN REF DESCRIPTION 1 IDA Input diode A CLOCK LOW TYPICAL PULSE AMPLITUDE OR DC LEVEL (V) Min Typical Max 0 see note 9 MAXIMUM RATINGS with respect to VSS +20 V 2 B13 Image clock 0 10 12 15 +20 V 3 TGA Transfer gate A 0 10 12 15 +20 V 4 A13 Register clock A 1 8 10 15 +20 V n/a 1 3 5 +20 V 5 OG Output gate (A and C) 6 – No connection 0 – 9.5 – 7 SS Substrate n/a 8 11 – 8 1R Reset (A and C) 0 8 12 15 +20 V 9 A12 Register clock A 1 8 10 15 +20 V 10 A11 Register clock A 1 8 10 15 +20 V 11 OD Output drain (A and C) 0 27 29 32 70.3 to +35 V 12 OSC Output source C 0 see note 10 70.3 to +35 V 13 IDC Input diode C 0 see note 9 70.3 to +25 V 14 RD Reset drain (A and C) 0 15 17 19 70.3 to +25 V 15 C11 Register clock C 1 8 10 15 +20 V 16 C12 Register clock C 1 8 10 15 +20 V 17 C13 Register clock C 1 8 10 15 +20 V 18 SS Substrate 0 8 11 – 19 – No connection 0 20 IG Input gate 0 15 +20 V 21 B12 Image clock 0 10 12 15 +20 V 22 TGC Transfer gate C 0 10 12 15 +20 V 23 B11 Image clock 0 10 12 15 +20 V 24 OSA Output source A 0 Maximum voltages between pairs of pin 11 (OD) to pin 24 (OSA) . pin 11 (OD) to pin 12 (OSC) . . Maximum output transistor current pins: . . . . . +15 V . . . . . +15 V . . . . . . 10 mA 9.5 – 8 10 see note 10 – +20 V NOTES 9. For normal operation, the input gate should be set to 0 V and the input diode to approx. 22 V. To inject charge for test purposes, the input gate should be pulsed high during the period when A11 is high and the input diode should be adjusted for the required charge injection. Typical uses for such charge injection include assessing charge transfer efficiency, and the measurement of output responsivity using the reset drain current method. 10. 3 to 5 V below OD. Connect to ground using a 5 mA current source or appropriate load resistor (typically 5 kO). 11. All devices will operate at the typical values given. However, some adjustment within the minimum to maximum range may be required to optimise performance for critical applications. It should be noted that conditions for optimum performance may differ from device to device. 12. With the B1 connections shown, charge is transferred to the top register, A. In order to transfer charge to the bottom register, B11 and B12 connections should be reversed. Refer to the waveform diagram. 100034, page 6 # e2v technologies ELECTRICAL INTERFACE CHARACTERISTICS An approximate equivalent circuit to represent the load presented by the image section or output registers is shown below. 11 8028 R1 COV COV C1 C3 C2 SS R2 R3 13 COV 12 Typical Electrode Capacitances (measured at mid-clock level) I1/I1 interphase (COV) . . I11/SS and I12/SS (C1, C2) I13/SS (C3) . . . . . . R1/R1 interphase . . . R1/SS . . . . . . . 1R/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 . . 3.5 . 12 . 30 . 60 . 20 nF nF nF pF pF pF Typical Electrode Series Resistance I11 and I12 (R1, R2) . . . I13 (R3) . . . . . . . R11, 2, 3 . . . . . . . Output amplifier impedance at typical operating conditions # e2v technologies . . . . . . . . . . . . . . . . . . . . . 20 14 20 O O O . . . . . . . 400 O 100034, page 7 DETAIL OF LINE TRANSFER 8030 Towards A Towards C B11 B12 t2 t3 B12 B11 t1 t3 t2 B13 & TGA B13 & TGC TGC TGA tdri tdir A11 C11 A12 C12 A13 C13 1RA 1RC Clocking Sequence During the integration period, all B1 electrodes should be low – the IMO implant takes care of charge gathering. For transfer to the A register, use the labelling of waveforms on the left of the diagram. Charge is transferred to the register when B13 and TGA are taken from high to low. For transfer to the C register, use the labelling of waveforms on the right of the diagram. Charge is transferred to the register when B13 and TGC are taken from high to low. If only one register is used, the recommended approach for the unused register is to tie its clocks high and its TG low. Any charge collected in the unused register would then spill over OG and drain out through RD, thus keeping unwanted charge out of the image section. Continuous clocking of the unused register can be used but may generate extra heat, potentially causing more dark current in the image area. 100034, page 8 # e2v technologies DETAIL OF OUTPUT CLOCKING 8036 R11 Tr tor R12 R13 twx tdx 1R OUTPUT VALID SIGNAL OUTPUT OS RESET FEEDTHROUGH LINE OUTPUT FORMAT 8031 15 BLANK 512 ACTIVE OUTPUTS CLOCK TIMING REQUIREMENTS Symbol t1 t2 t3 tri tfi tdri tdir tlt Tr trr tfr tor twx trx, tfx tdx Description Image clock overlap/delay Image clock overlap/delay Image clock overlap/delay Image clock pulse rise time (10 to 90%) Image clock pulse fall time (10 to 90%) Post register clocking delay Pre register clocking delay Line transfer/vertical shift time Output register clock cycle period Clock pulse rise time (10 to 90%) Clock pulse fall time (10 to 90%) Clock pulse overlap Reset pulse width Reset pulse rise and fall times Delay time, 1R low to R13 low Min Typical Max 10.0 0.65 1.1 0.1 tri 1.0 1.65 16.0 140 20 trr 10 20 0.2twx 30 20.0 1.0 2.0 5 tri 2.0 3.0 32.0 1000 0.1Tr 0.1Tr 0.5trr 0.1Tr 0.5trr 0.5Tr see note 13 see note 13 see note 13 Ti 7 2twi Ti 7 2twi see note 13 see note 13 see note 13 see note 13 0.3Tr 0.3Tr 0.1Tr 0.3Tr 0.1Tr 0.8Tr ms ms ms ms ms ms ms ms ns ns ns ns ns ns ns NOTES 13. No maximum other than that set by system constraints on the total readout period. # e2v technologies 100034, page 9 FUNCTIONAL DIAGRAM Output A 1 8029 16 A13 A12 A11 A13 A12 A11 A13 Column 1 ROW 1 ROW 256 ROW 257 ROW 512 IDC A12 A11 A13 A12 A11 A13 A12 A11 A13 A12 A11 A13 A12 A11 A13 A12 A11 IGA TGA TGA TGA TGA TGA TGA TGA TGA B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 B13 B13 B13 B13 B13 B13 B13 B13 B12 B12 B12 B12 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B11 B11 TGC TGC TGC TGC TGC TGC TGC TGC IGC C11 C12 C13 C11 C12 C13 C11 C12 C13 C11 C12 C13 C11 C12 C13 C11 C12 IDA Column 512 OGA SWA A12 A11 A13 527 Optical Centreline Output C C13 C11 C12 C13 C11 C12 C13 527 16 C13 C11 C12 SWC OGC 1 = Gate with IMO implant OUTPUT CIRCUIT 11 12 SW OG 1R RD 8032 OD TG (INTERNAL CONNECTION) OS OUTPUT EXTERNAL LOAD Cn SUBSTRATE SS 0V NOTE 14. SW is joined to 13 in the package. 100034, page 10 # e2v technologies OUTLINE (All dimensions without limits are nominal) 8037 A 24 13 IMAGE CENTRE B C 1 12 PIN 1 INDICATOR TEMPORARY COVERGLASS D IMAGE PLANE E F G H PITCH K # e2v technologies J Ref Millimetres A B C D E F G H J K 29.94 + 0.30 22.61 + 0.25 22.86 + 0.25 2.70 + 0.27 1.65 + 0.25 5.6 + 0.5 0.46 + 0.05 2.54 + 0.13 27.94 + 0.13 1.0 + 0.3 100034, page 11 ORDERING INFORMATION HANDLING CCD SENSORS Options include: CCD sensors, in common with most high performance MOS IC devices, are static sensitive. In certain cases a discharge of static electricity may destroy or irreversibly degrade the device. Accordingly, full antistatic handling precautions should be taken whenever using a CCD sensor or module. These include: * Temporary Glass Window * Permanent Window; ask for details * UV Coating * X-ray Phosphor Coating In common with other e2v technologies CCD Sensors, a front illuminated CCD77-00 is available with a fibre-optic window or taper. For further information on the performance of these and other options, please contact e2v technologies. * Working at a fully grounded workbench * Operator wearing a grounded wrist strap * All receiving socket pins to be positively grounded * Unattended CCDs should not be left out of their conducting foam or socket. Evidence of incorrect handling will invalidate the warranty. HIGH ENERGY RADIATION Device characteristics will change when subject to ionising radiation. Users planning to operate CCDs in high radiation environments are advised to contact e2v technologies. TEMPERATURE LIMITS Min Typical Max Storage . . . . . . . 153 – 373 K Operating . . . . . . 153 273 323 K Operation or storage in humid conditions may give rise to ice on the sensor surface on cooling, causing irreversible damage. Maximum device heating/cooling . . . . . 5 K/min Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. 100034, page 12 Printed in England # e2v technologies