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Bridging the Efficiency Gap in PoE Powered Device Designs Application Report Literature Number: SLUA592 October 1999 Application Report SLUA592 – October 2008 Bridging the Efficiency Gap in PoE Powered Device Designs _________________________________________________________________________________________ Donald V. Comiskey 1 Power Management Introduction The trend toward higher efficiency is becoming increasingly evident for Power over Ethernet (PoE) applications. Powered Device (PD) suppliers are looking for solutions that enable them to market their products as being “Green” or energy efficient. All of the components within the PD’s power path need to be closely examined to see if any significant improvements in efficiency can be made. This application report focuses on the full-wave bridge (FWB) rectifier used at the front end of most PD designs. Practical efficiency gains ranging from 2% to 3.5% are shown to be obtainable by using a FET FWB instead of the commonly used diode FWB. 2 PD Front-End Circuitry Figure 1 shows a partial schematic depicting the front-end circuitry commonly used for PoE PD designs. An input voltage of 48 VDC nominal is applied to the spare line or data line pairs associated with the RJ-45 input to power the PD. In some nonstandard cases, especially for higher power applications, the input voltage might be simultaneously applied to both the spare line and data line pairs. In any case, the PD needs to be insensitive to the polarity of the voltage applied at either of the input pairs, therefore requiring the two FWB rectifiers shown in the circuit. The FWB rectifiers at the front end of the PD are typically comprised of standard p-n diodes which can dissipate an appreciable amount of wasted power and lower the overall efficiency of the PD. The power dissipated by this type of FWB is equal to the forward voltage drop of two series diodes multiplied by the input current flowing through these diodes. It’s conceivable that an efficiency increase can be realized by replacing these diode FWB rectifiers with those constructed using MOSFETs. This application report explores the benefits of using the FET FWB to increase the overall efficiency of the various PD power classes. To simplify discussions, the report will assume that the PD is being powered through only one of the FWB devices, such as the data line pair FWB highlighted in Figure 1. PoE PD Data Line Pair FWB PoE Input 1 2 3 4 5 6 7 8 Texas Instruments TPS23750PWP RJ-45 1 20 FREQ 19 BL 18 VBIAS 17 MODE 16 AUX 15 SENSP GATE 14 VDD COM 13 DET RSN 12 CLASS RSP 11 VSS RTN PWPD 21 TMR 2 FB 3 COMP 4 SEN 5 9 10 11 14 15 16 6 7 8 9 10 8 7 6 3 2 1 Figure 1. Typical PoE PD front-end circuitry including input FWB rectifiers for polarity insensitivity. Bridging the Efficiency Gap in PoE Powered Device Designs 1 Application Report SLUA592 – October 2008 3 Diode FWB vs. FET FWB Operation Figures 2 and 3 show the operation of the diode FWB for both polarity configurations of the input voltage. The red highlighted path in Figure 2 indicates that diodes D1 and D4 conduct for the polarity A configuration, while the blue highlighted path in Figure 3 indicates that diodes D2 and D3 conduct for the polarity B configuration. Diode FWB - Input Polarity A D1 Diode FWB - Input Polarity B D1 D2 48Vin Vout D3 48Vin Vout D3 D4 Figure 2. Diode FWB operation for polarity A. D2 D4 Figure 3. Diode FWB operation for polarity B. For each of the above configurations, the power dissipation of the diode FWB is equal to the voltage drop across the two conducting diodes multiplied by the input current: Pdiss = 2 x VF x Iin Bridging the Efficiency Gap in PoE Powered Device Designs 2 Application Report SLUA592 – October 2008 Figures 4 and 5 show the corresponding operation of the FET FWB for both polarity configurations of the input voltage. Note, in this case, that the upper FETs are P-channel devices and the lower FETs are N-channel devices. The red highlighted path in Figure 4 indicates that FETs Q1 and Q4 conduct for the polarity A configuration, while the blue highlighted path in Figure 5 indicates that FETs Q2 and Q3 conduct for the polarity B configuration. The gate drive components associated with each conducting pair of FETs are highlighted in green. FET FWB - Input Polarity A 15V FET FWB - Input Polarity B 15V 15V Q1 200K Q2 Q1 200K 200K 48Vin Vout 200K 200K Q3 15V 15V 48Vin Vout 200K Q4 15V 200K Q3 15V Figure 4. FET FWB operation for polarity A. Q2 200K Q4 15V Figure 5. FET FWB operation for polarity B. For each configuration, the power dissipation of the FET FWB is equal to the square of the input current multiplied by the total on-state resistance of the conducting FETs, plus the power dissipated by the active gate drive components: Pdiss = ( Iin2 x Rds-on total ) + ( 2 x (P200K res + P15V zener) ) The Rds-on of the FET FWB would normally be selected based on tradeoffs between efficiency gain and cost for the particular power class of PD involved. The power dissipated by the gate drive components (the second term of the above equation) is considered to be overhead power dissipation. This overhead power dissipation, which would be the same for all four PD power classes, should be considered when selecting the Rds-on for the desired efficiency gain, especially for the lower power classes. Bridging the Efficiency Gap in PoE Powered Device Designs 3 Application Report SLUA592 – October 2008 Efficiency Gain of FET FWB over Diode FWB The graph in Figure 6 shows the efficiency gains that can be obtained when using the FET FWB over the standard diode FWB. The series of plots indicate how the efficiency gain for each of the four PD power classes would depend on the selection of the FET FWB Rds-on. The plots take into consideration the overhead power dissipation discussed in Section 3 above and the different values of VF that would normally be encountered when using a standard diode FWB at the various current levels associated with the different PD classes. Operation at 48 VDC, full load, and +25°C has been assumed for each PD class. Efficiency Gain vs. FET FWB Rds-on (as com pared to standard diode FWB) 3.75% Class 1 (3.84W) 3.50% Class 2 (6.49W) Class 3 (12.95W) 3.25% Class 4 (25.5W) 3.00% 2.75% Efficiency Gain 2.50% 2.25% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.00% 4.5 4 FET FWB Total Rds-on (ohms) Vin = 48V Full Power +25°C Figure 6. Efficiency Gain vs. FET FWB Rds-on for the four PD power classes. Bridging the Efficiency Gap in PoE Powered Device Designs 4 Application Report SLUA592 – October 2008 Cost-Benefit Analysis of using FET FWB The decision to use a FET FWB over the standard diode FWB would normally be based on a cost-benefit analysis of the particular PD application. The graph in Figure 6 uses a minimum efficiency gain of 2% as a practical criteria for indicating when the benefits provided by a FET FWB may be worthwhile. The cost of the FET FWB would typically be inversely proportional to Rds-on. Use of a schottky diode FWB instead of a standard p-n diode FWB might also be considered when performing a cost-benefit analysis of the PD application. The schottky diode FWB would typically provide an efficiency gain on the order of 1% and its cost would normally be between that of the standard diode FWB and the FET FWB. Figure 7 shows an example of efficiency gain vs. FWB relative cost for the standard diode, schottky diode, and FET FWB options. The example is based on comparably sized and rated devices offered in an IC package. The FET FWB option is assumed to have an Rds-on of 1.2 ohms and uses the external gate drive components discussed in Section 3 above. All of the component costs are based on 1000 pc. pricing through distribution. This relative cost information on the three FWB options can be compared to the overall PD cost to provide an overall cost-benefit analysis. Efficiency Gain vs. FWB Relative Cost 3.5% Class 1 (3.84W) 3.0% 1.2 ohm FET FWB IC Class 2 (6.49W) Class 3 (12.95W) 2.5% Class 4 (25.5W) 2.0% Schottky Diode FWB IC Standard Diode FWB IC 1.5% Efficiency Gain 1.0% 0.5% 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.0% 0.5 5 FWB Cost Multiplier Vin = 48V Full Power +25°C Figure 7. Efficiency gain vs. FWB relative cost example for providing overall cost-benefit analysis of PD. Bridging the Efficiency Gap in PoE Powered Device Designs 5 Application Report SLUA592 – October 2008 6 Considerations The information provided in this report has been based on operation at +25°C. It’s important to note that at elevated temperatures the efficiency of the standard diode FWB will increase due to decreasing VF, while the efficiency of the FET FWB will decrease due to increasing Rds-on. It’s not uncommon for the Rds-on to double over a 100°C increase in junction temperature. This needs to be considered when selecting the appropriate Rds-on for the desired efficiency gain when using the FET FWB. 7 Summary As the demand for “Green” and energy efficient PoE devices increases, PD suppliers are looking for cost effective ways to increase the efficiency of their products. This application report has explored the use of the FET FWB over the standard diode FWB commonly used at the front-end of a PD. The report shows that practical efficiency gains ranging from 2% to 3.5% can be obtained when using the FET FWB and selecting its Rds-on. An example of the relative cost of the various FWB options has also been presented as an aid in determining the overall cost effectiveness of using the FET FWB in PD designs. 8 References 1) TPS23754: High Power/High Efficiency PoE Interface and DC/DC Controller, Datasheet SLVS885, Texas Instruments, October 2008 2) TPS23750: Integrated 100-V IEEE 802.3af PD and DC/DC Controller, Datasheet SLVS590A, Texas Instruments, August 2005 3) IEEE P802.3at Draft 3.1, July 31, 2008 4) Rectifier Bridge Has No 2Vf Drop, Design Ideas, Theta Engineering Inc. Bridging the Efficiency Gap in PoE Powered Device Designs 6 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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