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TAS5630B
SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
TAS5630B 300-W Stereo and 400-W Mono PurePath™ HD Analog-Input Power Stage
1 Features
3 Description
•
The TAS5630B device is a high-performance analoginput class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
technology) with the ability to drive up to 300 W (1)
stereo into 4-Ω to 8-Ω speakers from a single 50-V
supply.
1
•
•
•
•
•
•
PurePath™ HD Enabled Integrated Feedback
Provides:
– Signal Bandwidth up to 80 kHz for HighFrequency Content From HD Sources
– Ultralow 0.03% THD at 1 W into 4 Ω
– Flat THD at All Frequencies for Natural Sound
– 80-dB PSRR (BTL, No Input Signal)
– > 100-dB (A-weighted) SNR
– Click- and Pop-Free Start-up
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
– Mono Parallel Bridge-Tied Load (PBTL)
– Stereo Bridge-Tied Load (BTL)
– 2.1 Single-Ended Stereo Pair and BTL
Subwoofer
– Quad Single-Ended Outputs
Total Output Power at 10% THD+N
– 400 W in Mono PBTL Configuration
– 300 W per Channel in Stereo BTL
Configuration
– 145 W per Channel in Quad Single-Ended
Configuration
High-Efficiency Power Stage (> 88%) With 60-mΩ
Output MOSFETs
Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short-Circuit
Protection) With Error Reporting
EMI Compliant When Used With Recommended
System Design
PurePath HD technology enables traditional ABamplifier performance (< 0.03% THD) levels while
providing the power efficiency of traditional class-D
amplifiers.
Unlike traditional class-D amplifiers, the distortion
curve does not increase until the output levels move
into clipping.
PurePath HD technology enables lower idle losses,
making the device even more efficient. When coupled
with TI’s class-G power-supply reference design for
TAS563x, industry-leading levels of efficiency can be
achieved.
Device Information(1)
PART NUMBER
TAS5630B
Mini Combo System
AV Receivers
DVD Receivers
Active Speakers
BODY SIZE (NOM)
HSSOP (44)
15.90 mm × 11.00 mm
HTQFP (64)
14.00 mm × 14.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical TAS5630B Application Block Diagram
3 ´ OPA1632
♫♪
TM
ANALOG
AUDIO
INPUT
PurePath HD
TAS5630B
(2.1 Configuration)
♫♪
♫♪
±15 V
12 V
25 V–50 V
TM
PurePath HD
Class-G Power Supply
Ref. Design
2 Applications
•
•
•
•
PACKAGE
110 VAC ® 240 VAC
(1)
Achievable output power levels are dependent on the thermal
configuration of the target application. A high-performance
thermal interface material between the exposed package heat
slug and the heat sink should be used to achieve high output
power levels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5630B
SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Audio Characteristics (BTL) .................................... 10
Audio Specification (Single-Ended Output) ............ 10
Audio Specification (PBTL) .................................... 11
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 30
11.1 Trademarks ........................................................... 30
11.2 Electrostatic Discharge Caution ............................ 30
11.3 Glossary ................................................................ 30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
Changes from Revision C (September 2012) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed Thermal Information table data. .............................................................................................................................. 8
Changes from Revision B (November 2011) to Revision C
Page
•
Changed Analog comparator reference node, VI_CM Vlaues From: MIN = 1.5 TYP = 1.75 MAX = 1.9 To: MIN =
1.75 TYP = 2 MAX = 2.15 ...................................................................................................................................................... 8
•
Changed ANALOG INPUTS - VIN TYP value From 3.5 to 5 VPP............................................................................................ 8
•
Changed the VIH and VIL Test Conditions From: INPUT_X, M1, M2, M3, RESET To: M1, M2, M3, RESET ........................ 9
•
Deleted - RL = 2 Ω, 1% THD+N, unclipped output signal From PO in the Audio Specification (PBTL) table....................... 11
Changes from Revision A (November 2011) to Revision B
Page
•
Changed the RINT_PU parameters from /OTW1 to VREG, /OTW2 to VREG, /SD to VREG to /OTW, /OTW1, /OTW2,
/CLIP, READY, /SD to VRE.................................................................................................................................................... 9
•
Added text to the PHD Package section. ............................................................................................................................. 17
•
Added text to the DKD Package section .............................................................................................................................. 17
Changes from Original (November 2010) to Revision A
Page
•
Changed Title From: 600-W MONO To: 400-W MONO......................................................................................................... 1
•
Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL
Configuration .......................................................................................................................................................................... 1
•
Changed the Pin One Location Package image .................................................................................................................... 5
•
Changed RL(PBTL) Load Impedance Min value From: 1.6 Ω To: 2.4 Ω, and Typ value From 2 To: 3 Ω ............................. 7
•
Added footnotes to the ROC table ......................................................................................................................................... 7
•
Added ROCP information to the ROC Table ............................................................................................................................ 8
2
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
•
Changed the IOC Typical Value From: 19 A To: 15 A............................................................................................................. 9
•
Deleted - RL = 2 Ω, 10%, THD+N, clipped input signal From PO in the Audio Specification (PBTL) table.......................... 11
•
Replaced the TYPICAL CHARACTERISTICS, PBTL CONFIGURATION graphs ............................................................... 12
•
Added section - Click and Pop in SE-Mode ......................................................................................................................... 18
•
Added section - PBTL Overload and Short Circuit ............................................................................................................... 18
•
Replaced the PACKAGE HEAT DISSIPATION RATINGS table with the THERMAL INFORMATION table....................... 18
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
www.ti.com
5 Pin Configuration and Functions
DKD Package
44 Pins HSSOP
Top View
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IOSD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44 pins PACKAGE
(TOP VIEW)
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IOSD
OTW1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
PHD Package
64 Pins HTQFP
Top View
4
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
Electrical Pin 1
Pin 1 Marker
White Dot
Figure 1. Pin One Location PHD Package
Pin Functions
PIN
NAME
FUNCTION (1)
DESCRIPTION
HTQFP
HSSOP
AGND
8
10
P
Analog ground
BST_A
54
43
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_A required.
BST_B
41
34
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_B required.
BST_C
40
33
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_C required.
BST_D
27
24
P
HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_D required.
CLIP
18
—
O
Clipping warning; open drain; active-low
C_STARTUP
3
5
O
Start-up ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode
FREQ_ADJ
12
14
I
PWM frame-rate-programming pin requires resistor to AGND
7, 23, 24, 57,
58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
30
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
—
P
Gate-drive voltage supply requires 0.1-μF capacitor to GND_A
GVDD_B
56
—
P
Gate drive voltage supply requires 0.1-μF capacitor to GND_B
GVDD_C
25
—
P
Gate drive voltage supply requires 0.1-μF capacitor to GND_C
GVDD_D
26
—
P
Gate drive voltage supply requires 0.1-μF capacitor to GND_D
GVDD_AB
—
44
P
Gate drive voltage supply requires 0.22-μF capacitor to GND_A/GND_B
GVDD_CD
—
23
P
Gate drive voltage supply requires 0.22-μF capacitor to GND_C/GND_D
INPUT_A
4
6
I
Input signal for half-bridge A
INPUT_B
5
7
I
Input signal for half-bridge B
INPUT_C
10
12
I
Input signal for half-bridge C
INPUT_D
11
13
I
Input signal for half-bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59–62
–
—
GND
(1)
No connect; pins may be grounded.
I = Input, O = Output, P = Power
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Pin Functions (continued)
PIN
NAME
FUNCTION (1)
DESCRIPTION
HTQFP
HSSOP
OC_ADJ
1
3
O
Analog overcurrent-programming pin requires resistor to AGND. 64-pin
package (PHD) = 22 kΩ. 44-pin PSOP3 (DKD) = 24 kΩ
OSC_IO+
13
15
I/O
Oscillator master/slave output/input
OSC_IO–
14
16
I/O
Oscillator master/slave output/input
OTW
—
18
O
Overtemperature warning signal, open-drain, active-low
OTW1
16
—
O
Overtemperature warning signal, open-drain, active-low
OTW2
17
—
O
Overtemperature warning signal, open-drain, active-low
OUT_A
52, 53
39, 40
O
Output, half-bridge A
OUT_B
44, 45
36
O
Output, half-bridge B
OUT_C
36, 37
31
O
Output, half-bridge C
OUT_D
28, 29
27, 28
O
Output, half-bridge D
63
1
P
PSU reference requires close decoupling of 330 pF to AGND.
PVDD_A
50, 51
41, 42
P
Power-supply input for half-bridge A requires close decoupling of 0.01-μF
capacitor in parallel with 2.2-μF capacitor to GND_A.
PVDD_B
42, 43
35
P
Power-supply input for half-bridge B requires close decoupling of 0.01-μF
capacitor in parallel with 2.2-μF capacitor to GND_B.
PVDD_C
38, 39
32
P
Power-supply input for half-bridge C requires close decoupling of 0.0- μF
capacitor in parallel with 2.2-μF capacitor to GND_C.
PVDD_D
30, 31
25, 26
P
Power-supply input for half-bridge D requires close decoupling of 0.01-μF
capacitor in parallel with 2.2-μF capacitor to GND_D.
READY
19
19
O
Normal operation; open-drain; active-high
RESET
2
4
I
Device reset input; active-low
SD
15
17
O
Shutdown signal, open-drain, active-low
VDD
64
2
P
Power supply for digital voltage regulator requires a 10-μF capacitor in parallel
with a 0.1-μF capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of 1 nF to
AGND.
VREG
9
11
P
Regulator supply filter pin requires 0.1-μF capacitor to AGND.
PSU_REF
6
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted
(1)
MIN
MAX
UNIT
VDD to AGND
–0.3
13.2
V
GVDD to AGND
–0.3
13.2
V
PVDD_X to GND_X (2)
–0.3
69
V
OUT_X to GND_X (2)
–0.3
69
V
BST_X to GND_X (2)
–0.3
82.2
V
BST_X to GVDD_X (2)
–0.3
69
V
VREG to AGND
–0.3
4.2
V
GND_X to GND
–0.3
0.3
V
GND_X to AGND
–0.3
0.3
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF to AGND
–0.3
4.2
V
INPUT_X
–0.3
7
V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND
–0.3
7
V
9
mA
0
150
°C
–40
150
°C
Continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
25
50
52.5
V
GVDD_x
Supply for logic regulators and gate-drive circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
3.5
4
1.8
2
2.4
3
7
10
7
15
7
10
Nominal
385
400
415
AM1
315
333
350
AM2
260
300
335
RL(BTL)
RL(SE)
(2)
RL(PBTL)
Load impedance
Output filter according to schematics in the
application information section
(1)
(2)
LOUTPUT(BTL)
LOUTPUT(SE)
(2)
LOUTPUT(PBTL)
Output filter inductance
(1)
Minimum output inductance at IOC
(2)
PWM frame rate selectable for AM interference
avoidance; 1% resistor tolerance.
fPWM
Nominal; master mode
RFREQ_ADJ
(1)
(2)
PWM frame-rate-programming resistor
Ω
μH
9.9
10
10.1
AM1; master mode
19.8
20
20.2
AM2; master mode
29.7
30
30.3
kHz
kΩ
Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component
rating.
See additional details for SE and PBTL in System Design Considerations.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
Voltage on FREQ_ADJ pin for slave mode
operation
VFREQ_ADJ
Overcurrent-protection-programming resistor,
cycle-by-cycle mode
ROCP
Overcurrent-protection-programming resistor,
latching mode
TJ
NOM
Slave mode
MAX
UNIT
3.3
V
64-pin QFP package (PHD)
22
33
44-Pin PSOP3 package (DKD)
24
33
PHD or DKD
47
68
0
125
Junction temperature
kΩ
°C
6.4 Thermal Information
TAS5630B
THERMAL METRIC
(1)
PHD (HTQFP)
DKD (HSSOP)
64 PINS
44 PINS
RθJA
Junction-to-ambient thermal resistance
8.6
8.8
RθJC(top)
Junction-to-case (top) thermal resistance
0.3
0.4
RθJB
Junction-to-board thermal resistance
2.1
3.0
ψJT
Junction-to-top characterization parameter
0.4
0.4
ψJB
Junction-to-board characterization parameter
2.1
3.0
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
6.5 Electrical Characteristics
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node, VREG
VI_CM
Analog comparator reference node, VI_CM
IVDD
VDD supply current
IGVDD_X
GVDD_x gate-supply current per half-bridge
IPVDD_X
Half-bridge supply current
VDD = 12 V
3
3.3
3.6
V
1.75
2
2.15
V
Operating, 50% duty cycle
22.5
Idle, reset mode
22.5
50% duty cycle
12.5
Reset mode
mA
mA
1.5
50% duty cycle with recommended output
filter
13.3
mA
Reset mode, No switching
870
μA
33
kΩ
5
VPP
ANALOG INPUTS
RIN
Input resistance
VIN
Maximum input voltage with symmetrical
output swing
READY = HIGH
IIN
Maximum input current
342
μA
G
Voltage gain (VOUT/VIN)
23
dB
OSCILLATOR
Nominal, master mode
fOSC_IO+
AM1, master mode
FPWM × 10
AM2, master mode
VIH
High level input voltage
VIL
Low level input voltage
8
3.85
4
3.15
3.33
4.15
3.5
2.6
3
3.35
1.86
V
1.45
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V
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Electrical Characteristics (continued)
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
OUTPUT-STAGE MOSFETs
RDS(on)
Drain-to-source resistance, low side (LS)
Drain-to-source resistance, high side (HS)
TJ = 25°C, excludes metallization
resistance, GVDD = 12 V
60
100
60
100
mΩ
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,G
Vuvp,hyst (1)
9.5
V
0.6
V
(1)
Overtemperature warning 1
95
100
105
°C
OTW2 (1)
Overtemperature warning 2
115
125
135
°C
OTWhyst (1)
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event
OTW1
OTE (1)
25
Overtemperature error
145
155
OTE-OTW differential
30
OTEhyst (1)
A reset must occur for SD to be released
following an OTE event.
25
OLPC
Overload protection counter
°C
165
°C
°C
fPWM = 400 kHz
2.6
Resistor – programmable, nominal peak
current in 1-Ω load,
64-pin QFP package (PHD)
ROCP = 22 kΩ
15
Resistor – programmable, nominal peak
current in 1-Ω load,
44-pin PSOP3 package (DKD),
ROCP = 24 kΩ
15
Overcurrent limit protection, latched
Resistor – programmable, nominal peak
current in 1-Ω load,
ROCP = 47 kΩ
15
IOCT
Overcurrent response time
Time from switching transition to flip-state
induced by overcurrent
150
ns
IPD
Internal pulldown resistor at output of each
half-bridge
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode
3
mA
Overcurrent limit protection
IOC
ms
A
STATIC DIGITAL SPECIFICATIONS
VIH
High-level input voltage
VIL
Low-level input voltage
Ilkg
Input leakage current
M1, M2, M3, RESET
2
V
0.8
V
100
μA
kΩ
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW, OTW1,
OTW2, CLIP, READY, SD to VREG
VOH
High-level output voltage
VOL
Low-level output voltage
IO = 4 mA
FANOUT
Device fanout OTW, OTW1, OTW2, SD,
CLIP, READY
No external pullup
(1)
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
20
26
32
3
3.3
3.6
4.5
V
5
200
30
500
mV
devices
Specified by design.
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6.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 680 nF,
MODE = 010, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
TYP MAX
RL = 4 Ω, 10% THD+N, clipped output signal
300
RL = 6 Ω, 10% THD+N, clipped output signal
210
RL = 8 Ω, 10% THD+N, clipped output signal
160
RL = 4 Ω, 1% THD+N, unclipped output signal
240
RL = 6 Ω, 1% THD+N, unclipped output signal
160
RL = 8 Ω, 1% THD+N, unclipped output signal
UNIT
W
125
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, input capacitor
grounded
|VOS|
Output offset voltage
Inputs ac-coupled to AGND
SNR
Signal-to-noise ratio (1)
A-weighted, AES17 filter
100
dB
DNR
Dynamic range
A-weighted, AES17 filter
100
dB
2.7
W
Pidle
(1)
(2)
Power dissipation due to idle losses (IPVDD_X)
0.03%
20
PO = 0, four channels switching
μV
270
(2)
50
mV
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
6.7 Audio Specification (Single-Ended Output)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 15 μH, CDEM = 470 μF,
MODE = 100, unless otherwise noted.
PARAMETER
PO
Power output per channel
TEST CONDITIONS
MIN
TYP MAX
RL = 2 Ω, 10% THD+N, clipped output signal
145
RL = 3 Ω, 10% THD+N, clipped output signal
100
RL = 4 Ω, 10% THD+N, clipped output signal
75
RL = 2 Ω, 1% THD+N, unclipped output signal
110
RL = 3 Ω, 1% THD+N, unclipped output signal
75
RL = 4 Ω, 1% THD+N, unclipped output signal
UNIT
W
55
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, input capacitor grounded
340
μV
SNR
Signal-to-noise ratio (1)
A-weighted, AES17 filter
93
dB
DNR
Dynamic range
A-weighted, AES17 filter
93
dB
Pidle
Power dissipation due to idle losses
(IPVDD_X)
PO = 0, four channels switching (2)
2
W
(1)
(2)
10
0.07%
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
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6.8 Audio Specification (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 3 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 1.5 μF,
MODE = 101-10, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 3 Ω, 10% THD+N, clipped output signal
400
RL = 4 Ω, 10% THD+N, clipped output signal
300
RL = 3 Ω, 1% THD+N, unclipped output signal
310
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted
260
μV
SNR
Signal to noise ratio (1)
A-weighted
100
dB
DNR
Dynamic range
A-weighted
100
dB
Pidle
Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching (2)
2.7
W
RL = 4 Ω, 1% THD+N, unclipped output signal
(1)
(2)
W
230
0.05%
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
6.9 Typical Characteristics
6.9.1 BTL Configuration
340
10
THD+N − Total Harmonic Distortion + Noise − %
4Ω
6Ω
8Ω
4Ω
6Ω
8Ω
320
300
280
260
PO − Output Power − W
1
0.1
240
220
200
180
160
140
120
100
80
60
40
0.01
0.005
20m
100m
1
10
100
0
400
PO − Output Power − W
4Ω
6Ω
8Ω
200
Efficiency − %
PO − Output Power − W
220
180
160
140
120
100
80
60
40
20
TC = 75°C
25
30
35
40
PVDD − Supply Voltage − V
35
40
PVDD − Supply Voltage − V
45
50
G001
240
0
30
Figure 3. Output Power vs Supply Voltage
300
260
25
G001
Figure 2. Total Harmonic + Noise vs Output Power
280
TC = 75°C
THD+N at 10%
20
TC = 75°C
45
50
G001
Figure 4. Unclipped Output Power vs Supply Voltage
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
4Ω
6Ω
8Ω
0
100
TC = 25°C
THD+N at 10%
200
300
400
500
2 Channel Output Power − W
600
700
G001
Figure 5. System Efficiency vs Output Power
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100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
340
4Ω
6Ω
8Ω
320
300
280
260
PO − Output Power − W
Power Loss − W
BTL Configuration (continued)
240
220
200
180
160
140
120
100
80
60
0
100
200
300
400
500
2 Channel Output Power − W
600
4Ω
6Ω
8Ω
40
TC = 25°C
THD+N at 10%
20
0
−10
700
0
10
THD+N at 10%
20
30
40
50
60
70
80
90 100 110
TC − Case Temperature − °C
G001
Figure 6. System Power Loss vs Output Power
G001
Figure 7. Output Power vs Case Temperature
0
TC = 75°C
VREF = 35.36 V
Sample Rate = 48kHz
FFT Size = 16384
−10
−20
−30
4Ω
Noise Amplitude − dB
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k
f − Frequency − Hz
G001
Figure 8. Noise Amplitude vs Frequency
6.9.2 SE Configuration
1 Channel Driven
170
2Ω
3Ω
4Ω
150
140
130
1
0.1
120
110
100
90
80
70
60
50
40
30
20
0.01
0.005
20m
100m
1
10
PO − Output Power − W
TC = 75°C
THD+N at 10%
10
TC = 75°C
0
100 200
G001
Figure 9. Total Harmonic Distortion + Noise vs Output
Power
12
2Ω
3Ω
4Ω
160
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
25
30
35
40
PVDD − Supply Voltage − V
45
50
G001
Figure 10. Output Power vs Supply Voltage
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SE Configuration (continued)
180
170
160
150
140
PO − Output Power − W
130
120
110
100
90
80
70
60
50
40
30
2Ω
3Ω
4Ω
20
10
0
−10
0
10
THD+N at 10%
20
30
40
50
60
70
80
90 100 110
TC − Case Temperature − °C
G001
Figure 11. Output Power vs Case Temperature
6.9.3 PBTL Configuration
500
3Ω
4Ω
6Ω
8Ω
3Ω
4Ω
6Ω
8Ω
450
400
1
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
0.1
350
300
250
200
150
100
50
0.01
TC = 75°C
THD+N at 10%
TC = 75°C
0.005
20m
100m
1
10
100
0
700
PO − Output Power − W
25
30
G001
35
40
PVDD − Supply Voltage − V
45
50
G001
Figure 12. Total Harmonic Distortion + Noise vs Output
Power
Figure 13. Output Power vs Supply Voltage
500
450
PO − Output Power − W
400
350
300
250
200
150
100
3Ω
4Ω
6Ω
8Ω
50
0
−10
0
10
THD+N at 10%
20
30
40
50
60
70
80
90 100 110
TC − Case Temperature − °C
G001
Figure 14. Output Power vs Case Temperature
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7 Detailed Description
7.1 Overview
TAS5630B is an analog input, audio PWM (class-D) amplifier. The output of the TAS5630B can be configured for
single-ended, bridge-tied load (BTL) or parallel BTL (PBTL) output. It requires two rails for power supply, PVDD
and 12 V (GVDD and VDD). The following functional block diagram shows interconnections of internal supplies,
control logic, gate drives and power amplifiers. Detailed schematic can be viewed in TAS5630B EVM User's
Guide (SLAU287).
7.2 Functional Block Diagram
/CLIP
READY
/OTW1
/OTW2
/SD
PROTECTION & I/O LOGIC
M1
M2
M3
/RESET
C_STARTUP
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
TEMP
SENSE
STARTUP
CONTROL
GVDD_A
GVDD _C
GVDD_B
OVER-LOAD
PROTECTION
GND
GVDD_D
CURRENT
SENSE
CB3C
OC_ADJ
OSC_SYNC_IO+
OSC_SYNC_IO-
4
OSCILLATOR
PPSC
FREQ_ADJ
4
4
PVDD_X
OUT_X
GND_X
GVDD_A
PWM
ACTIVITY
DETECTOR
4
PSU_REF
BST_A
PVDD_A
PVDD_X
PSU_FF
VI_CM
GND
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND_A
GVDD_B
INPUT_A
ANALOG
LOOP FILTER
BST_B
+
PVDD_B
+
INPUT_D
ANALOG
LOOP FILTER
-
+
ANALOG COMPARATOR MUX
INPUT_C
ANALOG
LOOP FILTER
ANALOG INPUT MUX
INPUT_B
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
GND_B
GVDD_C
BST_C
PVDD_C
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
+
ANALOG
LOOP FILTER
OUT_B
OUT_C
GND_C
-
GVDD_D
BST_D
PVDD_D
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND_D
14
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7.3 Feature Description
7.3.1 Power Supplies
To facilitate system design, the TAS5630B needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see Typical Application for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See SLAU287 for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5630B reference design. For additional information on recommended power
supply and required components, see Typical Application.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V powerstage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5630B is fully protected against erroneous
power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within
the specified range (see Recommended Operating Conditions).
7.3.2 System Power-Up and Power-Down Sequence
7.3.2.1 Powering Up
The TAS5630B does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see Electrical Characteristics). Although not specifically required, it is
recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to
charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
7.3.2.2 Powering Down
The TAS5630B does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see Electrical Characteristics). Although not specifically required, it is a good practice to hold RESET
low during power down, thus preventing audible artifacts including pops or clicks.
7.3.3 Error Reporting
The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
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Feature Description (continued)
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see Table 1).
Table 1. Error Reporting
SD
OTW1
OTW2,
OTW
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
Overload (OLP) or undervoltage (UVP)
1
0
0
Junction temperature higher than 125°C (overtemperature warning)
1
0
1
Junction temperature higher than 100°C (overtemperature warning)
1
1
1
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
DESCRIPTION
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, for example, turning down the volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see Electrical
Characteristics for further specifications).
7.3.4 Device Protection System
The TAS5630B contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5630B responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, that is, the supply voltage has increased.
The device functions on errors, as shown in the following table.
Table 2. Device Protection System
BTL Mode
Local error in
A
B
C
D
PBTL Mode
Turns Off or in
A+B
C+D
Local error in
Turns Off or in
A
B
C
SE Mode
Local error in
Turns Off or in
A
A+B+C+D
D
B
C
D
A+B
C+D
Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.
16
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7.3.5 Pin-to-Pin Short-Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, that is, when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device
does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and
SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and
PBTL output configurations; the detection is not performed in SE mode. To make sure the PPSC detection
system is not tripped, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X.
7.3.6 Overtemperature Protection
The two different package options have individual overtemperature protection schemes.
PHD Package:
The TAS5630B PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation. For highest reliability, the RESET should not be asserted until
OTW1 has cleared.
DKD Package:
The TAS5630B DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. It is recommended to wait until OTW has cleared before asserting RESET.
Thereafter, the device resumes normal operation.
7.3.7 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5630B fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach the levels stated in Electrical
Characteristics. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the highimpedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply
voltages have increased above the UVP threshold.
7.3.8 Device Reset
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output; that is, SD is forced high. A rising-edge transition on reset input allows the device to resume operation
after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms
after the falling edge of SD.
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7.3.9 Click and Pop in SE-Mode
The BTL startup has low click and pop due to the trimmed output dc offset, see Audio Characteristics (BTL).
The startup of the BTL+2 x SE system (Figure 21) or 4xSE (Figure 20) is more difficult to get click and pop free,
than the pure BTL solution; therefore, evaluating the resulting click and pop before designing in the device is
recommended.
7.3.10 PBTL Overload and Short Circuit
The TAS5630B has extensive overload and short circuit protection. In BTL and SE mode, it is fully protected
against speaker terminal overloads, terminal-to-terminal short circuit, and short circuit to GND or PVDD. The
protection works by limiting the current, by flipping the state of the output MOSFETs; thereby, ramping currents
down in the inductor. This only works when the inductor is NOT saturated, the recommended minimum inductor
values are listed in Recommended Operating Conditions. In BTL mode, the short circuit currents can reach more
than 15 A, so when connecting the device in PBTL mode (Mono), the currents double – that is more than 30 A,
and with these high currents, the protection system will limit PBTL speaker overloads, terminal-to-terminal shorts,
and terminal-to-GND shorts. PBTL mode short circuit to PVDD is not recommended.
7.3.11 Oscillator
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower-value switching frequencies together result in the fewest cases of interference throughout the AM band,
and can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
For slave-mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the
OSC_I/O pins as inputs, which must be slaved from an external clock.
7.4 Device Functional Modes
Table 3. Mode Selection Pins
MODE PINS
ANALOG INPUT
OUTPUT
CONFIGURATION
0
Differential
2 × BTL
AD mode
1
—
—
Reserved
1
0
Differential
2 × BTL
BD mode
0
1
1
Differential singleended
1 × BTL +2 ×SE
1
0
0
Single-ended
4 × SE
M3
M2
M1
0
0
0
0
0
DESCRIPTION
BD mode, BTL differential
AD mode
INPUT_C
1
(1)
18
0
1
1
1
0
1
1
1
Differential
1 × PBTL
(1)
INPUT_D
(1)
0
0
AD mode
1
0
BD mode
Reserved
INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 PCB Material Recommendation
TI recommends FR-4 2-oz. (70-μm) glass epoxy material for use with the TAS5630B. The use of this material
can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB
trace resistance).
8.1.2 PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000 μF, 63-V supports more applications.
The PVDD capacitors should be the low-ESR type, because they are used in a circuit associated with high-speed
switching.
8.1.3 Decoupling Capacitor Recommendations
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, quality decoupling capacitors should be used. In practice, X7R should be used in this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2.2-μF capacitor that is placed on the power supply to each half-bridge. The decoupling capacitor
must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high
power output, and the ripple current created by high power output. A minimum voltage rating of 63 V is required
for use with a 50-V power supply.
8.1.4 System Design Considerations
A rising-edge transition on the reset input allows the device to execute the startup sequence and starts switching.
Apply audio only when the state of READY is high; that starts and stops the amplifier without having audible
artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY
signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller
systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used either to activate a
volume decrease or to signal an intelligent power supply to increase the rail voltage from low to high for optimum
efficiency.
The device inverts the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
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8.2 Typical Application
The following schematics and PCB layouts illustrate best practices used for the TAS5630B.
8.2.1 Typical Application Schematic
Input DC
Blocking
Caps
ANALOG_IN_A
ANALOG_IN_B
OSC_IO-
VI_CM
/CLIP
C_STARTUP
OSC_IO+
READY
/RESET
/SD
Oscillator
Synchronization
/OTW1, /OTW2, /OTW
(2)
PSU_REF
Caps for
External
Filtering
&
Startup/Stop
System
microcontroller
or
Analog circuitry
BST_A
BST_B
OUT_A
INPUT_A
Input
H-Bridge 1
INPUT_B
Output
H-Bridge 1
2
OUT_B
2
Hardwire
PWM Frame
Rate Adjust
&
Master/Slave
Mode
Input DC
Blocking
Caps
ANALOG_IN_C
ANALOG_IN_D
FREQ_ADJ
nd
OUT_C
Output
H-Bridge 2
Input
H-Bridge 2
INPUT_D
2
OUT_D
8
PVDD
12V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
8
2 Order
L-C Output
Filter for
each
H-Bridge
BST_D
OC_ADJ
VREG
VDD
BST_C
AGND
M3
GND
M2
GND_A, B, C, D
PVDD_A, B, C, D
M1
GVDD_A, B, C, D
2
50V
nd
2 Order
L-C Output
Filter for
each
H-Bridge
2-CHANNEL
H -BRIDGE
BTL MODE
INPUT_C
Hardwire
Mode
Control
Bootstrap
Caps
Bootstrap
Caps
4
GVDD, VDD,
& VREG
Power Supply
Decoupling
Hardwire
OverCurrent
Limit
GND
GVDD (12V)/VDD (12V)
VAC
Figure 15. Typical Application Schematic
8.2.1.1 Design Requirements
This device can be configured for BTL, PBTL, or SE mode. Each mode will require a different output
configuration.
8.2.1.2 Detailed Design Procedure
• Pin 1 – Overcurrent adjust resistor can be between 24 kΩ to 68 kΩ depending on the application. The lower
resistance corresponds to the higher over-current protection level.
• Pin 2 – RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled
by a microprocessor.
• Pin 3 – Start-up ramp capacitor should be 4.7 nF for BTL and PBTL configurations, and 10 nF for SE
configuration.
• Pins 4, 5, 10, 11 – Differential pair inputs AB and CD. A DC blocking capacitor of 10 µF and an RC of 100 Ω
and 100 pF should be placed on each analog input.
• Pin 6 – Analog comparator reference node requires close decoupling capacitor of 1 nF to ground.
• Pin 7, 8, 23, 24, 57, 58 – Ground pins are connected to board ground.
• Pin 9 – Regulator supply filter pin requires 0.1 uF to AGND.
• Pin 12 – Frequency adjust resistor is discussed in Oscillator.
20
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Typical Application (continued)
•
•
•
•
•
•
•
•
•
•
•
•
Pin 13, 14 – Oscillator input/output. When frequency adjust pin is pulled up to VREG, the oscillator pins are
configured as inputs.
Pin 15 – Shutdown pin can be monitored by a microcontroller through GPIO pin. System can decide to assert
reset or power down. See Error Reporting.
Pin 16, 17 – There are two overtemperature warning pins for PHD package. They have two different levels of
warning. OTW1 is lower temperature level warning than OTW2. They can be monitored by a microcontroller
through GPIO pins. System can decide to turn on fan, lower output power or shutdown. See Error Reporting.
Pin 18 – Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide
to lower the volume.
Pin 19 – Ready pin can be used to signal the system that the device is up and running.
Pin 20-22 – Mode pins set the input and output configurations. See Table 2 for configuration setting of these
pins.
Pin 25, 26, 55, 56 – Gate drive power pins provide gate voltage for half-bridges. Each needs a 3.3-Ω isolation
resistor and a 0.1-uF decoupling capacitor.
Pins 27, 40, 41, 54 – Bootstrap pins for half-bridges A, B, C, D. Connect 33 nF from this pin to corresponding
output pins.
Pins 28, 29, 36, 37, 44, 45, 53, 54 – Output pins from half-bridges A, B, C, D. Connect appropriate bootstrap
capacitors to the output pins. For PWM filtering, each output mode is used with different LC configuration.
Pins 30, 31, 38, 39, 42, 43, 50, 51 – Power supply pins to half-bridges A, B, C, D. Each PVDD_X has
decoupling capacitor connecting to the appropriate GND_X pin.
Pins 32, 33, 34, 35, 46, 47, 48, 49 – Connect decoupling capacitors of each power input pin to power supply
ground pins. Connect these pins to board ground.
Pins 59-62 – Connect “No connect” pins to board ground. There is no internal connection to these pins.
8.2.1.3 Application Curves
340
4Ω
6Ω
8Ω
4Ω
6Ω
8Ω
320
300
280
260
1
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
0.1
240
220
200
180
160
140
120
100
80
60
40
0.01
100m
1
10
PO − Output Power − W
100
TC = 75°C
THD+N at 10%
20
TC = 75°C
0.005
20m
0
400
G001
Figure 16. Total Harmonic + Noise vs Output Power
25
30
35
40
PVDD − Supply Voltage − V
45
50
G001
Figure 17. Output Power vs Supply Voltage
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8.2.2 Typical Differential-Input BTL Application With BD Modulation Filters
BTL output and differential input configuration is a typical audio class-D (PWM) amplifier. With differential input, the output can be configured for BTL
application with BD modulation. The configuration below can also be used with AD modulation. BD modulation gives better channel separation and PSSR
performance.
GVDD/VDD (+12V)
PVDD
R30
C64
1000uF
3.3R
R31
3.3R
C26
100nF
C25
10uF
C40
33nF
L10
7uH
GND
C23
/SD
50
51
49
GND_A
PVDD_A
53
52
OUT_A
PVDD_A
55
56
57
58
54
BST_A
OUT_A
GVDD_A
GVDD_B
GND
60
62
59
NC
GND
NC
NC
63
GND_C
/SD
GND_C
/OTW1
GND_D
C71
1nF
C51
680nF
47
46
GND
L11
7uH
R71
3.3R
45
44
43
OUT_LEFT_P
C61
2.2uF
C41
33nF
42
PVDD
41
C68
47uF
63V
1000uF
C66
1000uF
C65
40
C69
2.2uF
GND
38
37
R74
3.3R
GND
C78
10nF
39
C62
2.2uF
GND
GND
GND
GND
C42
33nF
GND
OUT_RIGHT_M
36
7uH
L12
35
R72
3.3R
34
GND
C52
680nF
33
C72
1nF
C76
10nF
-
GND_D
OSC_IO-
PVDD_D
OSC_IO-
GND
C75
10nF
48
GND
C77
10nF
32
OSC_IO+
OUT_C
31
16
OUT_C
OSC_IO+
PVDD_D
15
FREQ_ADJ
OUT_D
14
PVDD_C
30
13
PVDD_C
INPUT_D
29
10uF
12
BST_C
INPUT_C
OUT_D
R21
10k
GND
TAS5630BPHD
VREG
BST_D
11
R_RIGHT_N
C17
100R
100pF
10
28
100nF
27
R13
9
GND
BST_B
GVDD_D
C16
GND
C15
100pF
GVDD_C
100R
PVDD_B
U10
AGND
26
R12
IN_RIGHT_P
GND
GND
C14
10uF
GND
25
7
8
VREG
24
1nF
C22
GND
C13
100pF
M3
100R
PVDD_B
VI_CM
23
10uF
OUT_B
INPUT_B
22
6
GND
M2
C21
R11
OUT_B
INPUT_A
M1
5
C12
IN_LEFT_N
GND_B
21
4
GND_B
C_STARTUP
READY
4.7nF
/RESET
20
3
19
10uF
NC
64
VDD
2
GND
C11
100R
100pF
GND_A
/CLIP
22.0k
C20
R10
C74
10nF
+
OC_ADJ
/OTW2
1
18
C10
IN_LEFT_P
C70
1nF
C50
680nF
GND
GND
R20
GND
17
C18
100pF
PSU_REF
R19
47k
61
GND
330pF
/RESET
100R
OUT_LEFT_M
R70
3.3R
C60
2.2uF
GND
GND
VREG
R18
GND
C31
100nF
C30
100nF
+
GND
/OTW1
C53
680nF
C63
2.2uF
/OTW2
/CLIP
C73
1nF
R73
3.3R
L13
7uH
GND
OUT_RIGHT_P
READY
VREG
PVDD
C67
1000uF
C43
33nF
R32
GND
3.3R
R33
GND
GVDD/VDD (+12V)
3.3R
C33
100nF
C32
100nF
GND GND
Figure 18. Typical Differential-Input BTL Application With BD Modulation Filters
22
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8.2.3 Typical Differential (2N) PBTL Application With BD Modulation Filters
When there is a need for more power in an audio system, PBTL is a good choice for this application. Paralleling the output after the inductors is
recommended. In this configuration, the device can be driven with higher current (lower load impedance). Figure 19 shows the component and pin
connections.
3.3R
GVDD (+12V)
VDD (+12V)
3.3R
PVDD
100nF
100nF
100nF
10uF
10nF
100V
2.2uF
100V
1
2
3
4
50
51
52
53
54
55
56
49
GND_A
PVDD_A
PVDD_A
OUT_A
OUT_A
BST_A
GVDD_A
57
58
GND
GVDD_B
60
61
62
59
NC
GND
NC
44
43
PVDD_B
VREG
AGND
BST_B
TAS5630BPHD
VREG
BST_C
10
INPUT_C
PVDD_C
11
INPUT_D
PVDD_C
12
1uF
250V
33nF
1nF
100V
10nF
100V
1nF
100V
10nF
100V
-
41
40
+
GND
39
38
37
2.2uF
100V
GND
1uF
250V
33nF
7uH
3.3R
36
35
OUT_LEFT_P
34
GND
33
1000uF
63V
32
31
30
29
28
26
27
25
24
/OTW2
17
2.2uF
100V
42
GND_D
GND_D
PVDD_D
GND_C
/OTW1
PVDD_D
/SD
16
OUT_D
15
OUT_D
GND_C
BST_D
OSC_IO-
14
GVDD_D
OUT_C
GVDD_C
OUT_C
OSC_IO+
13
GND
GND
FREQ_ADJ
GND
GND
10k
NC
OUT_B
PVDD_B
9
GND
3.3R
GND
8
7uH
GND
45
VI_CM
GND
OUT_LEFT_M
46
INPUT_B
M3
VREG
47
6
7
GND
48
5
23
100nF
OUT_B
22
GND
GND
GND_B
INPUT_A
M2
1nF
C_STARTUP
M1
100pF
GND_B
21
GND
10uF
GND
GND
GND_A
20
100R
IN_N
GND
1000uF
63V
/RESET
READY
GND
GND
OC_ADJ
/CLIP
4.7nF
100pF
19
GND
10uF
18
100R
IN_P
63
64
22.0k
NC
VDD
100pF
PSU_REF
330pF
GND
GND
GND
GND
47k
2.2uF
100V
GND GND
GND GND
/RESET
47uF
63V
1000uF
63V
VREG
100R
3.3R
7uH
33nF
OSC_IO+
OSC_IO-
GND
2.2uF
100V
PVDD
/SD
GND
/OTW1
GND
7uH
VREG
1000uF
63V
/OTW2
/CLIP
33nF
3.3R
READY
3.3R
GND
GVDD (+12V)
100nF
100nF
GND GND
Figure 19. Typical Differential (2N) PBTL Application With BD Modulation Filters
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8.2.4 Typical SE Application
Single-ended output configuration is often used for cost effective systems. This device can be configured to drive four independent channels with four
different inputs. The delivered power is not as much as BTL configuration. The advantage is that the component count for four channels is the same as
two BTL channels. The schematic in this section shows the component and pin connections.
3.3R
VDD (+12V)
3.3R
10uF
GVDD (+12V)
100nF
100nF
100nF
33nF
15uH
A
GND GND
GND GND
VREG
PVDD
2.2uF
1
10nF
2
3
GND
100R
4
GND
5
IN_B
6
10uF
100pF
1nF
7
GND
100nF
100R
VREG
8
GND
GND
9
IN_C
GND
10uF
10
100pF
11
10k
12
100R
GND
13
GND
IN_D
14
10uF
100pF
15
16
49
GND
GND_A
52
51
55
54
50
PVDD_A
OUT_A
OUT_A
PVDD_A
GND
GND
NC
NC
NC
NC
GVDD_A
22.0k
GND
100pF
GVDD_B
GND
100R
IN_A
10uF
PSU_REF
VDD
100pF
BST_A
58
57
56
61
60
59
64
63
330pF
62
/RESET
53
GND
GND
47k
100R
OC_ADJ
GND_A
/RESET
GND_B
C_STARTUP
GND_B
INPUT_A
OUT_B
INPUT_B
OUT_B
VI_CM
PVDD_B
GND
PVDD_B
TAS5630BPHD
AGND
BST_B
VREG
BST_C
INPUT_C
PVDD_C
INPUT_D
PVDD_C
FREQ_ADJ
OUT_C
OSC_IO+
OUT_C
OSC_IO-
GND_C
/SD
GND_C
/OTW1
GND_D
48
47
46
GND
15uH
45
B
44
2.2uF
43
33nF
42
PVDD
41
3.3R
47uF
63V
40
2.2uF
39
10nF
38
2.2uF
37
33nF
15uH
GND
GND
36
GND
C
35
34
GND
33
GND_D
32
PVDD_D
PVDD_D
OUT_D
29
30
31
BST_D
OUT_D
GVDD_D
26
28
27
GND
GVDD_C
GND
23
24
25
M1
M3
M2
20
21
22
/CLIP
/OTW2
17
18
19
OSC_IO+
READY
GND
OSC_IO2.2uF
/SD
PVDD
GND
/OTW1
VREG
15uH
/OTW2
D
33nF
/CLIP
GND
3.3R
READY
GVDD (+12V)
3.3R
100nF
100nF
10nF
100V
3.3R
100nF
100V
R_COMP
10k
PVDD
R_COMP
50V
49V
48V
<48V
147kW
165kW
187kW
191kW
+
100nF
100V
1%
10k
470uF
50V
10k
470uF
50V
10k
-
470nF
250V
+
100nF
100V
1%
GND
OUT_A_P
10k
470uF
50V
100nF
100V
R_COMP
PVDD
GND
1%
3.3R
GND
100V
10nF
OUT_B_P
1%
3.3R
GND
100V
10nF
GND
10nF
100V
3.3R
100nF
100V
R_COMP
10k
PVDD
470uF
50V
10k
GND
3.3R
470uF
50V
10k
1%
1%
+
GND
100nF
100V
R_COMP
10k
PVDD
470uF
50V
10k
470uF
50V
10k
1%
-
470nF
250V
+
100nF
100V
GND
OUT_C_P
3.3R
GND
100V
10nF
GND
OUT_D_M
D
-
470nF
250V
100nF
100V
GND
10nF
100V
OUT_C_M
C
GND
OUT_B_M
B
-
470nF
250V
10k
470uF
50V
PVDD
3.3R
OUT_A_M
A
10nF
100V
GND GND
GND
1%
OUT_D_P
3.3R
GND
GND
100V
10nF
GND
Figure 20. Typical SE Application
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8.2.5 Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application
One of the attractive features of this device is that it can be configured for mixed BTL and SE outputs. One BTL plus two SE channels make up a 2.1
audio system. While the SE channels are used to drive the front end and right speakers, the BTL channel can deliver higher power and is used to drive a
subwoofer. Figure 21 shows the component and pin connections.
GVDD (+12V)
PVDD
3.3R
1000uF
63V
VDD (+12V)
3.3R
10uF
GND
100nF
100nF
100nF
33nF
7uH
OUT_CENTER_M
GND GND
GND GND
VREG
3.3R
2.2uF
100V
49
52
51
50
55
54
53
58
57
56
61
60
59
64
63
330pF
62
/RESET
1
GND
10uF
2
100pF
3
GND
100R
4
GND
5
IN_CENTER_N
6
10uF
100pF
1nF
GND
7
100nF VREG
8
GND
100R
GND
9
IN_LEFT
GND
10uF
10
100pF
11
10k
100R
GND
12
13
GND
IN_RIGHT
14
10uF
100pF
15
16
OC_ADJ
GND_A
GND_B
C_STARTUP
GND_B
OUT_B
45
GND
VREG
44
43
41
BST_C
40
PVDD_C
PVDD_C
FREQ_ADJ
OUT_C
OSC_IO+
OUT_C
OSC_IO-
GND_C
/SD
GND_C
/OTW1
GND_D
2.2uF
100V
33nF
42
BST_B
INPUT_C
7uH
OUT_CENTER_P
OUT_B
INPUT_D
PVDD
3.3R
37
2.2uF
100V
33nF
GND
GND
GND
GND
OUT_LEFT_M
35
GND
33
100nF
100V
R_COMP
34
10k
PVDD
470uF
50V
10k
1%
470uF
50V
10k
1%
-
470nF
250V
+
100nF
100V
GND
OUT_LEFT_P
3.3R
GND
GND
3.3R
GND
15uH
36
GND
2.2uF
100V
VREG
/SD
10nF
100V
10nF
100V
39
38
GND_D
PVDD_D
2.2uF
100V
32
31
OUT_D
PVDD_D
OUT_D
29
30
28
GVDD_C
BST_D
GVDD_D
26
27
25
M3
GND
GND
23
24
22
READY
M2
M1
20
21
/CLIP
/OTW2
17
18
19
OSC_IO+
47uF
63V
1000uF
63V
GND
OSC_IO-
GND
3.3R
GND
PVDD_B
PVDD_B
TAS5630BPHD
10nF
100V
680nF
250V
48
INPUT_A
AGND
1nF
100V
47
46
INPUT_B
10nF
100V
+
GND
/RESET
VI_CM
1nF
100V
GND
GND_A
PVDD_A
OUT_A
OUT_A
PVDD_A
BST_A
GVDD_B
NC
GND
GND
NC
NC
GVDD_A
22.0k
10nF
NC
VDD
GND
100R
PSU_REF
100pF
IN_CENTER_P
680nF
250V
GND
GND
47k
100R
100V
10nF
10nF
100V
GND
/OTW1
15uH
/OTW2
3.3R
GND
OUT_RIGHT_M
33nF
/CLIP
3.3R
READY
100nF
100V
R_COMP
3.3R
10k
PVDD
100nF
100nF
GND GND
470uF
50V
10k
1%
470uF
50V
10k
1%
GND
-
470nF
250V
+
100nF
100V
GND
OUT_RIGHT_P
3.3R
GND
100V
10nF
PVDD
GVDD (+12V)
Figure 21. Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application
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8.2.6 Typical Differential-Input BTL Application With BD Modulation Filters, DKD Package
This is the same application as described in Typical Differential-Input BTL Application With BD Modulation Filters with PHD package. For DKD package
an external heatsink is required to dissipate excess heat. In this package, the PCB space is not a limiting factor for dissipating excess heat.
R34
GVDD (+12V)
1.5R
C87
100nF
C38
100nF
PVDD
1000uF
63V
VDD (+12V)
GND
C35
100nF
C44
10uF
GND
7uH
OUT_LEFT_M
GND
GND
3.3R
C86
VREG
680nF
250V
GND
330pF
R44
47k
R13
U12
1
/RESET
C78
100pF
100R
2
R14
3
GND
24k
C45
R45
4
GND
IN_LEFT_P
10uF
100R
4.7nF
C82
100pF
100R
1nF
C79
100pF
C42
VREG
GND
R53
10uF
100R
R60
GND_A
VI_CM
GND_B
GND
OUT_B
10
AGND
11
VREG
14
10k
IN_RIGHT_N
100R
C81
100pF
BST_B
INPUT_C
BST_C
INPUT_D
PVDD_C
FREQ_ADJ
OUT_C
OSC_IO+
GND_C
16
OSC_IO-
GND_D
/SD
OUT_D
17
18
19
/OTW
READY
OUT_D
PVDD_D
20
M1
PVDD_D
21
M2
BST_D
M3
GVDD_CD
VREG
OSC_IO+
PVDD_B
TAS5630BDKD
15
GND
10uF
PVDD_A
INPUT_B
13
R20
PVDD_A
/RESET
OUT_A
12
C80
100pF
OC_ADJ
OUT_A
100nF
IN_RIGHT_P
43
INPUT_A
9
GND
GND
BST_A
VDD
C_STARTUP
8
GND
10uF
44
6
7
IN_LEFT_N
GVDD_AB
5
C85
R54
PSU_REF
22
42
1nF
100V
10nF
100V
1nF
100V
10nF
100V
-
C33
+
33nF
GND
41
680nF
250V
C83
2.2uF
40
GND
3.3R
39
7uH
38
OUT_LEFT_P
37
GND
36
PVDD
35
34
C41
33nF
C90
2.2uF
C37
33nF
C91
2.2uF
63V
33
32
1000uF
1000uF
63V
2.2uF
100V
10nF
100V
GND
GND
GND
GND
31
3.3R
47uF
63V
GND
GND
7uH
30
OUT_RIGHT_M
29
28
GND
C34
2.2uF
27
26
3.3R
680nF
250V
25
1nF
100V
10nF
100V
1nF
100V
10nF
100V
-
24
23
OSC_IO-
33nF
C88
+
GND
GND
GND
/SD
680nF
250V
/OTW
3.3R
READY
7uH
OUT_RIGHT_P
PVDD
1.5R
1000uF
63V
R31
100nF
C89
100nF
C84
GND
GVDD (+12V)
GND
Figure 22. Typical Differential-Input BTL Application With BD Modulation Filters, DKD Package
26
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TAS5630B
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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015
9 Power Supply Recommendations
Absolute Maximum Ratings discusses most of the requirements on TAS5630B power supply. There are a few
more important guidelines that should be considered. The most important parameters are the absolute maximum
rating on PVDD pins, bootstrap pins and output pins. Over stress the device with higher that maximum voltage
rating may shorten device lifetime operation and even cause device damage. Be sure that the specifications in
section 6 are observed. For best audio performance, low ESR bulk capacitors are recommended. Depending on
the application 470-µF capacitor or higher should be used. As always, decoupling capacitors must be placed no
more than 1 mm from the power supply pins. If PCB space is not allowed for close decoupling capacitor
placement, the decoupling capacitors can be placed on the back side of the device with vias. However, it still
needs to be right below the pins.
10 Layout
10.1 Layout Guidelines
Use an unbroken ground plane to have a good low-impedance and -inductance return path to the power supply
for power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
of the audio input should be kept short and together with the accompanying audio-source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce. It is always good practice to
follow the EVM layout as a guideline.
Netlist for this printed circuit board is generated from the schematic in Figure 18.
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10.2 Layout Example
Note T1: PVDD bulk decoupling capacitors C60–C64 should be as close as possible to the PVDD_X and GND_X
pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins
and without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins. This is valid for C60, C61, C62, and C63.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, preferably metal film types.
Figure 23. Printed Circuit Board – Top Layer
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Layout Example (continued)
Note B1: It is important to have a direct-low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short, low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors
Figure 24. Printed Circuit Board – Bottom Layer
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11 Device and Documentation Support
11.1 Trademarks
PurePath is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TAS5630BDKDR
HSSOP
DKD
44
500
330.0
24.4
TAS5630BPHDR
HTQFP
PHD
64
1000
330.0
24.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
14.7
16.4
4.0
20.0
24.0
Q1
17.0
17.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5630BDKDR
HSSOP
DKD
TAS5630BPHDR
HTQFP
PHD
44
500
367.0
367.0
45.0
64
1000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DKD0044A
PowerPAD TM SSOP - 3.6 mm max height
SCALE 1.000
PLASTIC SMALL OUTLINE
C
SEATING PLANE
14.5
TYP
13.9
A
0.1 C
PIN 1 ID AREA
42X 0.65
44
1
EXPOSED
THERMAL PAD
12.7
12.6
16.0
15.8
NOTE 3
2X
13.65
22
23
44X
(2.95)
0.38
0.25
0.12
C A B
5.9
5.8
B
11.1
10.9
NOTE 4
(0.15)
EXPOSED THERMAL PAD
3.6
3.1
(0.28) TYP
SEE DETAIL A
0.35
GAGE PLANE
0 -8
0.3
0.1
1.1
0.8
DETAIL A
TYPICAL
4218846/A 07/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. The exposed thermal pad is designed to be attached to an external heatsink.
www.ti.com
EXAMPLE BOARD LAYOUT
DKD0044A
PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE
44X (2)
SEE DETAILS
SYMM
1
44
44X (0.45)
42X (0.65)
SYMM
(R0.05) TYP
22
23
(13.2)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MAX
AROUND
0.05 MIN
AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4218846/A 07/2016
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DKD0044A
PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE
44X (2)
1
SYMM
44
44X (0.45)
42X (0.65)
SYMM
(R0.05) TYP
23
22
(13.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE:6X
4218846/A 07/2016
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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