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AN033
High Efficiency, Fast Transient
Synchronous Step-Down Converter
The Future of Analog IC Technology
High Efficiency, Fast Transient
Synchronous Step-Down Converter
Application Note
Prepared by Scott Yi
Jan. 25, 2010
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AN033
High Efficiency, Fast Transient
Synchronous Step-Down Converter
The Future of Analog IC Technology
ABSTRACT
This paper introduces the monolithic synchronous rectified step-down converter of NB638, which
utilizes constant-on-time (COT) control scheme. Details of COT operation are provided. It also provides
design guidelines for ramp compensation, frequency setting, output setting and output LC filter
selection. A detailed example design is demonstrated.
NB638 INTRODUCTION
The NB638 is a fully integrated high frequency synchronous rectified step-down switch mode converter.
It offers a very compact solution to achieve 6A continuous output current over a wide input supply
range with excellent load and line regulation. The NB638 operates at high efficiency over a wide output
current load range. COT control method is utilized in NB638.
The COT control method uses the output ripple as feedback ramp signal (FB) to compare with a
reference voltage signal (REF) to regulate the output voltage. A fast comparator is used in the control
loop. Unlike current mode control and voltage mode control, COT control doesn’t employ an error
amplifier. So comparing with current mode control and voltage mode control, COT control method
provides easy loop stabilization and fast transient response. In addition, COT also provides seamless
transition between skip mode and PWM mode. However, there is no perfect control scheme in power
management field. COT control also has its own disadvantages. In COT control, the switching
frequency at PWM mode changes with input voltage. Fortunately, in NB638, adaptive COT control is
achieved by feed-forwarding the input voltage. Hence, the switching frequency in NB638 is fairly
constant over the input voltage range. The COT control uses output ESR ripple to regulate the output
voltage. When low ESR capacitors (e.g. Ceramic CAP) are used, the CAP ripple dominates the output
ripple, which causes instability in the system. In this case, a voltage ramp derived from inductor current
ripple is introduced to FB to stabilize the system.
HEAVY LOAD OPERATION (PWM)
In Fig 1, it shows the function block diagram of NB638. The operation of NB638 is demonstrated in Fig
2. At the beginning of each cycle, the high-side MOSFET (HS-FET) is turned ON whenever the FB is
below the REF which indicates insufficient output voltage. The ON period is determined by the input
voltage and the frequency-set resistor as follows:
6 × RFREQ (kΩ)
(1)
TON (ns) =
VIN (V) − 0.4
After the ON period elapses, the HS-FET is turned off, or becomes OFF state. It is turned ON again
when FB drops below REF. By repeating operation in this way, the converter regulates the output
voltage. The integrated low-side MOSFET (LS-FET) is turned on when the HS-FET is in its OFF state to
minimize the conduction loss. There will be a dead short between input and GND if both HS-FET and
LS-FET are turned on at the same time. That’s so-called shoot-through. In order to avoid shoot-through,
a dead-time (DT) is internally generated between HS-FET off and LS-FET on, LS-FET off and HS-FET
on.
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
IN
Current Sense
Amplifer
FREQ
+
RSEN
5V LDO
VCC
Over-Current
Timer
OC
BST
Refresh
Timer
ILIM
+
REFERENCE
EN
BSTREG
OFF
Timer
-
HS_MOS
HS Ilimit
Comparator
0.4V
1MEG
HS
Driver
PWM
xS
Q
1.0V
0
0.8V
SW
xR
LOGIC
SS
SOFT
START/STOP
VCC
+
+
-
FB
ON
Timer
START
LS_MOS
LS
Driver
Loop
Comparator
Current
Modulator
PGOOD
+
PGOOD
Comparator
+
UV
GND
UV Detect
Comparator
0
AGND
+
OV
0
OV Detect
Comparator
Fig 1—NB638 Function Block Diagram
Fig 2—NB638 COT Heavy Load Operation
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
LIGHT LOAD OPERATION (SKIP MODE)
At light load or no load condition, the output drops very slowly as shown in Fig 3. The FB does not
reach REF when the inductor current is approaching zero. The LS-FET driver turns into tri-state (high Z)
whenever the inductor current reaches zero. A current modulator takes over the control of LS-FET and
limits the inductor current to less than -1mA. Hence, the output capacitors discharge slowly to GND
through LS-FET. The efficiency at light load condition is greatly improved. At light load condition, the
HS-FET is not turned ON as frequently as at heavy load condition, so it’s called skip mode.
Fig 3—NB638 COT Light Load Operation
TRANSITION BETWEEN PWM MODE AND SKIP MODE
As the output current increases from the light load condition, the time period within which the current
modulator regulates becomes shorter. The HS-FET is turned ON more frequently. Hence the switching
frequency increases correspondingly. The output current reaches the critical level when the current
modulator time is zero. This critical level of the output current is determined as follows:
(VIN − VOUT ) × VOUT
(2)
IOUT =
2 × L × FS × VIN
It turns into PWM mode once the output current exceeds the critical level. After that, the switching
frequency stays fairly constant over the output current range.
FREQUENCY SETTING
There is no dedicated oscillator in the NB638. The input voltage is feed-forwarded to the on-time oneshot timer through the resistor RFREQ. The duty ratio is kept as VOUT/VIN. Hence the switching frequency
is fairly constant over the input voltage range. The switching frequency can be set as follows:
FS (kHz) =
106
6 × RFREQ (kΩ) VIN (V)
×
+ TDELAY (ns)
VIN (V) − 0.4 VOUT (V)
(3)
Where TDELAY is the comparator delay, it’s about 40ns.
NB638 is optimized to operate at high switching frequency but also with high efficiency. High switching
frequency makes it possible to utilize small sized LC filter components to save system PCB space.
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
RAMP COMPENSATION
In Fig 4 and Fig 5, it shows jittering happens both in PWM mode and skip mode. To stabilize the
system, it should be understood that it’s the downward slope of the FB ripple dominates the noise
immunity ability. The magnitude of the FB ripple doesn’t affect the noise immunity directly. In the follow
sections, we’ll discuss how to determine the downward slope of the FB ripple. When the output
capacitors are ceramic ones, the ESR ripple is not high enough to stabilize the system, and then an
external ramp signal is added. In the case of POSCAP or other types of capacitor with higher ESR, the
external ramp is not necessary. In PWM mode, the downward slope differs whether there is external
ramp used or not. While in skip mode, the downward slope is not related to the external ramp. We’ll
discuss the details of the downward slope in these three cases below.
Fig 4—Jittering in PWM Mode
Fig 5—Jittering in skip Mode
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
CERAMIC CAPACITORS (EXTERNAL RAMP USED)
In PWM mode, the equivalent circuit during HS-FET off is simplified as in Fig 6 when an external ramp
circuit is used. The external ramp is derived from the inductor ripple current. If we choose C4, R1 and
R2 to meet the following condition:
1
1 R × R2
〈 ×( 1
)
2π × FS × C4 5 R1 + R2
(4)
then we can have:
IR4 = IC5 + IFB ≈ IC5
The downward slope of the FB ripple can be estimated as follows:
− VREF
(5)
VSLOPE1 =
R 4 × C4
As we can see from equation 4, if there is instability in PWM mode, we can reduce either R4 or C4. If
C4 can not be reduced further due to limitation from equation 5, then we can only reduce R4. From our
bench experiments, VSLOPE1 is expected around 20~40V/ms.
Fig 6—Simplified Circuit in PWM Mode (External Ramp Used)
POSCAP CAPACITORS (NO EXTERNAL RAMP USED)
In Fig 7, it shows the equivalent circuit in PWM mode when HS-FET is off, where there is no external
ramp used. The ESR ripple dominates the output ripple. The downward slope of the FB ripple is as
follows:
−ESR × VREF
(6)
VSLOPE1 =
L
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
From equation 6, we can see that downward slope of FB ripple is proportional to ESR/L. That’s the
reason why we ask for minimum ESR value of the output capacitors when no external ramp is used.
There is also a limitation of the inductance in this case. The smaller of the inductance, the better
stability it will be. From our bench experiments, it is recommended to keep VSLOPE1 around 15~30V/ms.
The ESR value of the output capacitors should also fulfill the equation 6A to ensure the stability of the
system:
1
1 1
(7)
< ( ~ )fs (6A)
2π × ESR × COUT
3 4
Fig 7—Simplified Circuit in PWM Mode (No External Ramp Used)
SKIP MODE
In skip mode, the downward slope of the FB ripple is the same no matter the external ramp is used or
not. Fig 8 shows the equivalent circuit when HS-FET is off and the current modulator regulates the LSFET. The downward slope of the FB ripple can be determined as follows (IMOD is ignored here):
− VREF
(8)
VSLOPE2 =
(R1 + R2 ) × COUT
To keep the system stable during light load condition, the values of the FB resistors should not be too
big. It is recommended to keep VSLOPE2 to be around 0.4~0.8mV/ms. This is the worst case condition
since IMOD is ignored here. With IMOD considered, there should be no stability issue at light load condition.
Fig 8—Simplified Circuit in skip Mode
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
OUTPUT VOLTAGE SETTING
The output voltage is set by using a resistive voltage divider from the output voltage to FB pin. The type
of output capacitor affects the FB resistors selection.
POSCAP CAPACITORS (NO EXTERNAL RAMP USED)
When there is no external ramp employed, the output voltage is set by feedback resistors R1 and R2.
First, choose a value for R2. A value within 5kΩ-40kΩ is recommended to ensure stable operation.
Then R1 is determined as follows:
R1 =
VOUT − VREF
× R2
VREF
(9)
CERAMIC CAPACITORS (EXTERNAL RAMP USED)
When low ESR ceramic capacitor is used in the output, an external voltage ramp should be added to
FB through resistor R4 and capacitor C4. Choose a value within 5kΩ-40kΩ for R2. The value of R1 then
is determined as follows:
1
(10)
R1 =
1
VREF + VRAMP
1
2
−
1
R2 × (VOUT − VREF − VRAMP ) R 4
2
OUTPUT RIPPLE
The output capacitor is required to maintain the DC output voltage. Ceramic or POSCON capacitors are
recommended. The output voltage ripple can be estimated by:
ΔVOUT =
VOUT
V
1
× (1 − OUT ) × (RESR +
)
FS × L
VIN
8 × FS × COUT
(11)
Where RESR is the equivalent series resistance (ESR) value of the output capacitor.
In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the
output voltage ripple can be estimated by:
ΔVOUT =
VOUT
V
× (1 − OUT )
8 × FS2 × L × COUT
VIN
(12)
The output voltage ripple caused by ESR is very small. So it needs an external ramp to stabilize the
system. The external ramp can be generated through resistor R4 and capacitor C4 follows:
VRAMP =
(VIN − VFB ) × TON
R 4 × C4
(13)
In the case of POSCON capacitors, the ESR dominates the impedance at the switching frequency. The
ramp voltage generated from the ESR is high enough to stabilize the system. So the external ramp is
not recommended. For simplification, the output ripple can be approximated as:
ΔVOUT =
AN033 Rev. 0.2
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VOUT
V
× (1 − OUT ) × RESR
FS × L
VIN
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
INDUCTOR SELECTION
The inductor is required to supply constant current to the output load while being driven by the switched
input voltage. A larger value inductor will result in less ripple current that will result in lower output ripple
voltage. However, the larger value inductor will have a larger physical size, higher series resistance,
and/or lower saturation current. A good rule for determining the inductance to use is to allow the peakto-peak ripple current in the inductor to be approximately 30~40% of the maximum switch current limit.
Also, make sure that the peak inductor current is below the maximum switch current limit. The
inductance value can be calculated by:
L=
VOUT
V
× (1 − OUT )
FS × ΔL
VIN
(15)
Where ΔL is the peak-to-peak inductor ripple current.
Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor
current can be calculated by:
ILP = IOUT +
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VOUT
V
× (1 − OUT )
2FS × L
VIN
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
DESIGN PROCEDURE (POSCAP OUTPUT CAPACITOR USED)
Unknown: VIN, VOUT, IOUT, ∆VOUT, FS,
To be known: R1, R2, RFREQ, L, COUT, ESR
1. Determine RFREQ,
RFREQ can be determined by equation 3. After derivation, it’s as follows:
V (V) − 0.4 VOUT (V)
106
RFREQ (kΩ) = (
)
− TDELAY (ns)) × ( IN
×
FS (kHz)
6
VIN (V)
2. Determine L
The inductance of L can be found by equation 15. The thumb of rule to choose ΔL is to keep it
30%~40% of IOUT. Here we choose 30%.
VOUT
V
L≤
× (1 − OUT )
FS × 0.3 × IOUT
VIN
3. Determine ESR
With L known, we can get the maximum ESR based on equation 14.
ΔVOUT
ESR ≤
VOUT
V
× (1 − OUT )
FS × L
VIN
Choose an ESR value that is less than what is determined by above equation. Based on our
bench experience, for application of VIN=19V, VOUT=1.05V and IOUT=6A, the minimum ESR value
would be 12mΩ for COUT=270μF and fs=300kHz.
4. Determine COUT
The larger of the output capacitance, the better the transient response will be, however the
higher cost. As we know ESR, we can easily choose the output capacitors which provide proper
capacitance value, voltage rating and footprint size. The output capacitance value should also
fulfill equation 6A as follows:
2
COUT >
π × ESR × fs
5. Determine R1, R2
As we can find out from equation 6, the values of R1 and R2 shouldn’t be too big, otherwise, it
may be unstable at light load condition. Choose a value between 5kΩ-40kΩ for R2, then R1
could be determined as follows:
V − VREF
R1 = OUT
× R2
VREF
If it’s unstable at light load condition, we can reduce the value of R2 and then get a new value
for R1, until it’s stable.
DESIGN PROCEDURE (CERAMIC CAPACITOR USED)
Unknown: VIN, VOUT, IOUT, ∆VOUT, FS,
To be known: R1, R2, RFREQ, R4, C4, L, COUT
1. Determine RFREQ,
RFREQ can be determined by equation 3. After derivation, it’s as follows:
V (V) − 0.4 VOUT (V)
106
RFREQ (kΩ) = (
− TDELAY (ns)) × ( IN
×
)
FS (KHz)
6
VIN (V)
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
2. Determine L
The inductance of L can be found by equation 14. The thumb of rule to choose ΔL is to keep it
30%~40% of IOUT. Here we choose 30%.
VOUT
V
L≤
× (1 − OUT )
FS × 0.3 × IOUT
VIN
3. Determine COUT
The larger of the output capacitance, the better the transient response will be, however the
higher cost. The minimum output capacitance can be determined as follows:
VOUT
V
COUT =
× (1 − OUT ) .
8 × FS2 × L × ΔVOUT
VIN
4. Determine R1, R2
As we can find out from equation 6, the values of R1 and R2 shouldn’t be too big, otherwise, it
may be unstable at light load condition. Choose a value between 10kΩ-30kΩ for R2, then R1
could be determined as follows:
R1 =
1
1
VREF + VRAMP
1
2
−
1
R
4
R 2 × (VOUT − VREF − VRAMP )
2
If it’s unstable at light load condition, we can reduce the value of R2 and then get a new value
for R1, until it’s stable.
5. Determine TON
The On period of HS-FET can be determined based equation 1 as follows:
6 × RFREQ (kΩ)
TON (ns) =
VIN (V) − 0.4
6. Determine C4
The minimum value of C4 can be determined from equation 5 as follows:
C4 =
5 × (R1 + R2 )
2π × FS × R1 × R2
From equation 4, the smaller of the value of C4, the better the system stability will be. So we’ll
choose the value for C4 based on the above equation.
7. Determine R4
From previous analysis, the magnitude of the external ramp doesn’t directly affect the stability of
the system. However, as long as the ON and OFF period of the HS-FET are determined, the
larger the ramp is, the more stable the system will be. But as the point of view of transient
response, it’s better to have the smallest external ramp voltage. For the typical application of
“VIN=19V, VOUT=1.05V and IOUT=6A”, 30mV is a good choice for the external ramp. Then R4 can
be determined as follows:
R 4 (kΩ) =
(VIN − VFB ) × TON (ns) × 106
30(mV) × C4
If the system is unstable at PWM mode, we can choose a higher value for VRAMP to determine
the new value of R4 until it’s stable.
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AN033 –HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
CONCLUSION
The NB638 using adaptive COT control is introduced here. Detailed design guidelines of system
stabilization are provided. The NB638 provides fast transient response and easy loop stabilization, with
optimized high efficiency at light load as well.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
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