Download Realization of Square-Root Domain integrators with large time

Indian Journal of Pure & Applied Physics
Vol. 54, May 2016, pp. 321-326
Realization of Square-Root Domain integrators with large time-constant
Farooq A Khanday1* & Costas Psychalinos2
1
University of Kashmir, Department of Electronics and Instrumentation Technology, Srinagar, 190 006, India
2
University of Patras, Physics Department, Electronics Laboratory, GR-26504, Rio Patras, Greece
Received15 January 2015; revised 20 October 2015; accepted 8 December 2015
A technique for performing capacitor scaling in Square-Root Domain (SRD) filters is introduced in this paper. This has
been achieved through an appropriate modification of the bias in the corresponding SRD integrator blocks. The validity of
the proposed scheme has been verified through simulation results, where the most important performance factors have been
compared with those obtained through the conventional SRD integrator scheme.
Keywords: Analog integrated circuits, Low-voltage analog circuits, Companding filters, Capacitor multipliers
1 Introduction
Square-Root Domain (SRD) filters are a category
of compression-expansion filters, which are based on
the translinear principle1. This category of filters
utilizes the square law I–V characteristics of MOS
transistor when operated in saturation region2.
Consequently, the SRD filters, because of their
nature, offer a large dynamic range (DR) with
potential for operation in modern low-voltage
environment. These stem from the fact that the
voltages at integration nodes are compressed versions
of the voltages of their conventional linear
counterparts and, therefore, reduced voltage swings
are observed. The compression is performed by the
input non-linear current-to-voltage conversion stage
which employs the large-signal current-voltage
characteristics of MOS transistors. Also, the realized
time constants are controlled through appropriate dc
currents. An additional benefit is the possibility for
electronic adjustment of the frequency characteristics
of SRD filters, due to the electronically controlled
time constants. On the other hand, these specific filter
structures are more complex in comparison with
filter structures of classical linear techniques and
therefore they produce more parasitic poles while also
consuming more power. Besides, this technique of
filter design is limited vis-à-vis the minimum channel
length of MOS transistors3-7.
Systematic design procedures for deriving
SRD filters have been introduced in Refs8,9.
Following the design procedures, the wave
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*Corresponding author (E-mail: [email protected])
active filter10, component substitution11, linear
transformation12, and multifeedback13-15 techniques
have been applied in the case of SRD filters.
Also, SRD first and second-order filters have been
introduced in Refs16-19.
To be compatible with digital design, the analog
structures must be designed in MOS and the area
consumed should be small. The major contributor
of the area for analog circuits is capacitors.
The problem becomes severe as the circuits are
designed for low-frequency applications. The solution
to this problem lies in the electronic scaling of
capacitor. The Log-Domain and Sinh-Domain
designs of large time-constants using capacitor
scaling have been recently introduced20. The circuits
employ MOS transistors in weak inversion
which have inherent limitations of sensitiveness
to threshold voltage matching and the restricted
bandwidth.
Therefore, a novel concept for realizing SRD filters
with large time-constants using capacitor scaling
is introduced in this paper. To start with, the lossy
and lossless SRD integrators, being the building
blocks of the SRD filter design, have been redesigned
in order to incorporate the capacitor scaling.
2 SRD Integrator Blocks with Capacitor Scaling
The basic idea of companding technique realized
using the concept of SRD filtering is presented in
Fig. 1, where the conversion of the current into a
compressed voltage is performed by the leftmost
transistor denoted as COMP by employing the
following equation9
INDIAN J PURE & APPL PHYS, VOL 53, MAY 2016
322
υ̂ IN = COMP(iin ) ≡
where
υ̂ IN
is
2(iin + I o )
+ VTH
K
the
gate-source
the performed operation is
corresponding operator as:
… (1)
voltage,
W 
K = µ o Cox   the transconductance parameter,
L
VTH the threshold voltage of a MOS transistor.
It must be noted that the addition of the circumflex (^)
at signals denotes compressed signals and will be
followed in the entire paper.
The output voltage is converted into a current
by the rightmost transistor denoted as EXP and
iout = EXP(υˆ OUT ) ≡
described by the
K
(υˆOUT − VTH )2 − I o
2
… (2)
The realization of the integrators which will be
described below is performed by employing the
square-root divider block given in Fig. 214. The output
current of this topology is given as:
iZ =
I0
iX
iY
… (3)
where Io is a dc current.
A current-mode lossless integrator with one output
realized using the concept of SRD filtering is
presented in Fig. 3a14. Inspecting the topology in
Fig. 3a, it is readily obtained that due to the
current-mirror (Mn3-Mn4) action, the topology
could be simplified as it is shown in Fig. 3b. The
transfer function of the SRD integrator is given as:
H (s ) =
Fig. 1 – The basic idea of SRD filtering
iout EXP(υˆOUT ) 1
=
=
iin
EXP(υˆ IN ) τˆs
Fig. 2 – Square-root divider cell (a) circuitry and (b) its associated symbol
… (4)
KHANDAY & PSYCHALINOS: REALIZATION OF SQUARE-ROOT DOMAIN INTEGRATORS
323
Fig. 3 – Current-mode lossless integrator using the concept of SRD filtering (a) full and (b) simplified circuitry
with the time-constant of SRD integrator given as:
τˆ =
Cˆ
2 KI o
… (5)
The value of the equivalent resistor is determined
through the expansion stage and, according to Eq. (5)
it will be
R eq =
1
2 KI o
… (6)
From Eqs (5) and (6) it can be derived that way
for increasing the value of the time-constant is
through the reduction of the dc bias current Io. Due
to the fact that the output current should be always
less than or equal to this bias current Io, it is obvious
that the amplitude of the maximum signal that could
be successfully handled by the integrator is reduced.
In order to overcome this limitation, the realization
depicted in Fig. 4 is introduced. The current that flows
through the integration capacitor is given as:
dυ̂
iC = Cˆ OUT =
dt
I SRD
iin
iOUT
… (7)
Fig. 4 – Proposed topology of a current-mode lossless integrator
using the concept of SRD filtering with capacitor multiplication
In addition, the output current could be expressed
as:
iout =
K
(υˆOUT − VTH )2 − I o
2
… (8)
According to Eq. (8) the instantaneous value of the
output current is the sum of an dc component (Io) and
ac component (iout) and is given by the formula:
K
2
iOUT = (υˆOUT − VTH )
2
, then from Eqs (7) and (8) is
derived the transfer function of the integrator
INDIAN J PURE & APPL PHYS, VOL 53, MAY 2016
324
H (s ) =
iout
iin
=
1
ˆ
τ's
… (9)
where in Eq. (9) the time constant is given as:
τˆ' =
Cˆ
2 KI SRD
… (10)
Taking into account that the expansion of the
output voltage is performed by a transistor biased at
dc current Io and, therefore, the value of the
equivalent resistance remains unchanged, it is derived
from (7) and (10) that
Cˆ eq = Cˆ ⋅
Io
I SRD
… (11)
According to Eq. (11), the core of the topology in
Fig. 4 could be viewed as a capacitor multiplier, with
Io
I
a multiplication factor equal to SRD .
That is, the contribution made by the proposed
concept is that a scaling of the capacitor value is
achieved without limiting the range of the signal that
could be successfully handled by the system. This is
achieved through the utilization of an additional
degree of freedom originated from the bias of the
square-root divider block.
At this point, it is to be mentioned that SRD
circuits are not suitable for biomedical applications,
where extremely large time-constants should
be realized due to the low-frequency nature of
biological signals, and this could be easily confirmed
through a literature survey. This is originated
from the fact SRD filters are realized through the
employment of the quadratic law of MOS transistor
which is only valid in the strong-inversion regime
and, therefore, the bias current could not be in the
order of pAs required for realizing large timeconstants. As a result, only Log-Domain and SinhDomain realizations constructed from MOS
transistors biased in the subthreshold region have
been reported, and this originated from the fact that
exponential characteristic of bipolar transistors
biased in the forward active region is also valid for
MOS transistors biased in the subthreshold region.
Therefore, the proposed concept is intended to used
in typical base-band applications where, as it will be
confirmed through the comparison, a significant
capacitor area saving is achieved.
Following the same concept, the corresponding
topology of a lossy SRD integrator is depicted in
Fig. 5. The realized transfer function is given as:
H (s ) =
iout
1
=
iin τˆ' s + 1
… (12)
while the expressions for the time-constant is still
given by Eq. (11).
An important characteristic of the presented
integrator topologies, originated from the employment
of the cell in Fig. 2, is that the minimum supply voltage
V
+ 2V
V
DS , sat
requirement is equal to TH
, where DS , sat
is the saturation voltage of MOS transistors. As a
result, the proposed circuits will be fully compatible
with nowadays’ industry demands for systems with
low-voltage operation capability. Another benefit
is that the realization of SRD integrators using the
square-root divider block offers a significant reduction
of the circuit complexity in comparison with the
Fig. 5 – Proposed topology of a current-mode lossy integrator using the concept of SRD filtering with capacitor multiplication
KHANDAY & PSYCHALINOS: REALIZATION OF SQUARE-ROOT DOMAIN INTEGRATORS
corresponding topologies where geometric mean and
squarer/divider cells have been utilized9-13.
3 Simulation and Comparison Results
The validity of the proposed concept has been
evaluated using the Analog Design Environment of
the Cadence software. For this purpose, the models
provided by the AMS 0.35 µm CMOS process were
utilized for the MOS transistors. The dc power supply
voltages were VDD=1.5 V and VDC=900 mV, while the
dc current Io was equal to 50 µA. Taking into account
this bias scheme, the aspect ratios of the transistors of
the cell in Fig. 2 are summarized in Table 1.
It must be also mentioned that the aspect ratio of
nMOS and pMOS transistors that distribute the bias
current through the current mirrors was 4 µm / 1 µm and
100 µm/1 µm, respectively. Furthermore, the aspect
ratio of nMOS transistors employed in integration and
compression/expansion blocks was equal to 10 µm/2 µm.
The performance of the lossy integrator in
Fig. 5 will be evaluated in the next. Considering
that ISRD= 10 µA, then the value of the resistor
will be equal to 23.56 kΩ. In order to realize a cutoff
frequency fo=100 kHz then, according to Eq. (5),
the capacitor value should be C = 135.1 pF .
The dc power dissipation for the integrator in Fig. 4
was 708 µW. Its tunability is demonstrated in Fig. 6,
where the frequency responses at ISRD= 10 µA, 25 µA,
and 50 µA are simultaneously given. The simulated
values of the cutoff frequency were fo= 96.8 kHz, 182.3
kHz, and 266 kHz; the corresponding theoretical values
were 100 kHz, 158.1 kHz, and 224 kHz, respectively.
325
The linear performance of this topology has been
evaluated through the periodic steady state (PSS)
analysis offered by the Analog Design Environment.
For this purpose, a sinusoidal input signal with 1 kHz
frequency has been applied at the input. The derived
total harmonic distortion (THD) plot is given in
Fig. 7, where the THD level at full input scale
(i.e. amplitude 50 µA) was 0.83%.
The noise has been integrated within the pass
band frequency of the integrator and the calculated
rms value of the input referred noise was 13.7 nA.
Therefore, the dynamic range (DR) will be 68.2dB.
The effects of MOS transistor parameters
mismatch as well as process parameters variations
have been analyzed using the Monte Carlo analysis.
The obtained statistical plots are given in Fig. 8.
The values of standard deviation about the cutoff
frequency and low-frequency gain were 6.8 kHz and
ˆ
Fig. 7 – Evaluation of the linear performance of the lossy
integrator in Fig. 5
Table 1 – MOS transistor aspect ratios for the square-root
divider cell in Fig. 2
Transistor
W/L
Mp1-Mp7
Mp8-Mp10
Mn1-Mn4
Mn5-Mn8
Mn9-Mn12
200µm/2µm
20µm/2µm
24µm/2µm
48µm/2µm
24µm/2µm
Fig. 6 – Frequency responses of the lossy integrator in Fig. 5
Fig. 8 – Statistical analysis results for the (a) cutoff
frequency and (b) low-frequency gain of the lossy integrator
in Fig. 5
326
INDIAN J PURE & APPL PHYS, VOL 53, MAY 2016
Table 2 – Comparison results for the proposed lossy integrator with capacitor scaling scheme
Performance factor
Lossy integrator without
capacitor scaling
Lossy integrator with
capacitor scaling
1.5 V / 900 mV
50 µA
50 µA
972 µW
302 pF
0.70%
10.1 nA
70.1 dB
8.1 kHz
14.5m
1.5 V / 900 mV
50 µA
10 µA
708 µW
135.1 pF
0.83%
13.7 nA
68.2 dB
6.8 kHz
14.5m
Bias voltages (VDD/VDC)
Bias current for compression/expansion (Io)
Bias current for SRD filtering (ISRD)
Power dissipation
Total capacitance
THD for input signal full scale (50 µA)
rms value of the input referred noise
Dynamic range
Standard deviation of the cutoff frequency
Standard deviation of the low-frequency gain
14.5 m, respectively. Therefore, the topology in
Fig. 5 offers reasonable sensitivity characteristics.
The performance results are summarized given in
Table 2, where the corresponding results for the lossy
SRD integrator derived through the conventional
design approach (i.e. Io= ISRD= 50 µA) are also
provided. According to Table 2, it is easily obtained
that the proposed scheme offers a significant reduction
of the total silicon area and power dissipation at the
expense of linearity and dynamic range.
As per the author’s best knowledge, there is
no square-root domain circuit where an endeavor
has been made to scale the value of capacitors.
However, few techniques have been given in
the open literature using the Log-Domain and
Sinh-Domain techniques. These schemes have
utilized MOSFET operated in weak inversion
region. Therefore, it will not be fair to compare the
proposed circuit with these schemes.
It should be also mentioned at this point that
the proposed scheme is not suitable for biomedical
application where very large time constants are
required. The large time constants are generally
achieved using the small currents (in the order of
pAs), but is not possible to bias the transistors in
strong inversion region with such low current.
Therefore the proposed scheme will be suited for
base-band applications where it will save a significant
capacitor area.
4 Conclusions
A novel integrator capacitor scaling scheme
suitable for realizing SRD filters with large timeconstants is introduced in this paper. The performance
comparison results show that the proposed scheme
offers the benefit of reducing the total silicon area
without significantly affecting the other performance
factors of a filter. The proposed topologies are
amenable for monolithic integration, and could be
used for realizing modern low-voltage, low-frequency
analog processing systems.
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