Download Noise Analysis of Multi input Quasi Floating Gate Using

Noise Analysis of Multi input Quasi Floating Gate Using CMOS Inveter
K.Ramesh
Asst. Professor in ETC,ABIT,Cuttack,Orissa
[email protected]
G. Devi
Professor in CSE,ABIT,Cuttack,Orissa
[email protected]
ABSRACT
In this paper the multiinput Quasi Floating gate is
used for low voltage application.The Noise effect
in the multi-input combined signal is somehow
reuced by using Quasi Floating FET gates and by
CMOS inverter. The Noise effect is almost reduced
and hence the signal to noise (S/N) ratio is
enhanced.
KEY WORDS : Quasi floating Gate FETs,CMOS
inverter,Multi input Signals
I. INTRODUCTION
The Floating Gate MOS Transister is generated by
forming an additional conductive layer between
control terminal and channel DS isolated from
envirnment called floating gate. The concept I.of
floating gate was first develoved by Kahng and Sze
in 1967. The initial charge on floating gates may
vary significantly. In order to control a desired
voltage level, different techniques are available.A
floating gate MOSFET offers tunability of
threshold voltage with a bias voltage without the
need of actually lowering the threshold voltage.
The design of analog circuits operting with low
voltage and dissipating low power is significant for
mixed mode implementation of systems on chip
which comprises both digital and analog
III.
Circuit digram of Multi-Input Quasi
Floating Gate & It’s Analysis :-
components[6,10]. Floatin gate has limitations
such as isolated floating gate which may
accumulate static charge, give low frequency
response and require large chip area[3]. A number
of anlog applications based on floating gate
techniques have been developed for analog
amplifiers,D/A Converter and adaptation circuits
,etc.These analog floating gate approaches for low
voltage, low power and high precision analog
circuit design. But there is one practical problem
how to control initial charge of floating gate
nodes.It require high supply voltage. These
problems can be overcome by Quasi floating gate
MOSFET (QFGMOS).
II.QUASI FLOATING GATE AND MULTI
INPUT QUASI FLOATING GATE
In Quasi Floating Gate, the gate is weakly
connected to one of the supply range to a high
value resister[1,4,5,6,8].In Multi input Quasi
floating gate MOSFET, one important factor is the
input terminals are capacitively coupled to the
Quasi floating Gate and it’s gate voltage is set to
VDD through a pull-up resister which can be
implemented by using the large leakage resistance
of a P-MOS Transister operating in cut-off
region[7,9,10].It offers better performance interms
of frequency response,offsets and chip area.
T
5.00
OUTPUT WAVEFORMS AT DIFFERENT STAGES AND RESULTANT OUTPUT VF3
OSC1_Ch1
OSC1_Ch2
VF1
VF2
VF3
VF1
VF2
2.50
Axis label
VF3
0.00
-2.50
Figure No.-1
The above electronics circuit gives us an idea about the
multiplexed inputs with double ended inverter gate which
is successfully demonstrated by Tina Software and the
pseudo floating gates are involved in the demonstration
with p-channel and n-channel JFET gates along with
leakage resisters and bypass capacitors. Here the three
different kinds of signals are combined at node point (1)
as combined input 1 and another three kinds of different
signals are combined at node point (2) as combined input
2. Both the combined input signals are passed through
the p-channel pseudo floating and n-channel pseudo
floating gates for the shifting purpose so the biasing
voltage can be stored at the capacitors and the combined
ac signal can easily pass throughout the capacitors to the
inverter gate as double input combined signals.
-5.00
0.00
1.00u
2.00u
3.00u
4.00u
5.00u
Figure No.-2
The output of combined signals at the node point (1) is
the combination of three sine wave signals with 5v and
1MHz and the output of node point (1) is passed through
the n-channel pseudo floating gate and the end gate
output VF1 as shown in fig (1) and similar procedure is for
2nd combined signal where we given three square wave
signals of 5v and 1MHz, whose output VF2 is as shown in
fig (2).
The net output VF1 of multi-input inverter gate is as
shown in fig. (2) Where two p-channel and n-channel
EMOS are involved and shows the result as the
T
output of inverter gate and due to different waveform
,many spectrums are generated.
0.0
VF1
VF2
Gain [dB]
-50.0
VF3
FREQUENCY RESPONSE AT DIFFERENT OUTPUTS
Vs DIFFENERENT INPUT FREQUENCIES
-100.0
VF1
VF2
VF3
-150.0
-200.0
10.00
100.00
1.00k
10.00k
100.00k
Frequency [Hz]
1.00M
10.00M
100.00M
1.00G
Figure No.-3
The frequency response of three outputs are shown in fig.
where the response of VF1 and VF2 are more linear above
the cut off frequency where as the frequency response of
VF3 is more non –linear above the cut off frequency. From
the characteristics, the maximum gain of VF3 is constant
in very small bandwidth. Hence in less BW we can
transmit large no. of summed signals through the channel
and by using the band pass filters we can separate the
signals
T
Nodes
Values
I_R1[9,8]
271.3uA
I_R2[7,13]
247.1uA
I_R3[0,9]
235uA
I_R4[0,7]
1.1mA
I_R5[13,15]
-8.4uA
I_R6[8,16]
-9.9pA
V_C1[1,9]
235mV
V_C10[9,14]
-235mV
V_C11[7,10]
-1.1V
V_C2[2,9]
235mV
V_C3[3,9]
235mV
V_C4[7,13]
8.9V
V_C5[9,8]
9.8V
V_C6[4,7]
1.1V
V_C7[5,7]
1.1V
V_C8[6,7]
1.1V
V_C9[17,12]
3.1mV
V_Light1[1,0]
0V
V_Light10[14,0]
333.5pV
V_Light11[10,0]
5.02E-19V
V_Light7[7,0]
-1.1V
V_Light8[9,0]
-235mV
V_Light9[12,0]
0V
V_R1[9,8]
9.8V
V_R2[7,13]
8.9V
V_R3[0,9]
235mV
V_R4[0,7]
1.1V
V_R5[13,15]
-8.4V
V_R6[8,16]
-9.9uV
V_V1[0,8]
10V
V_V2[11,0]
10V
V_V3[0,13]
10V
VF1
-235mV
VF2
-1.1V
VF3
0V
VP_1
0V
VP_10
5.02E-19V
VP_11
10V
VP_12
0V
DC values at nodal points and output terminals of the
circuit
5.0
VF2
4.0
T
0.0
VF2
3.0
Ampl. [V]
AMPLITUDE SPECTRUM OF VF1,VF2 & VF3
VF3
VF1
-50.0
VF2
Power [dBm]
VF1
VF2
VF3
2.0
VF3
1.0
VF1
VF2
VF3
-100.0
POWER SPECTRUMS OF OUTPUTS AT 1MHz
-150.0
0.0
1.00p
166.81p
27.83n
4.64u
774.26u
129.15m
Frequency [Hz]
21.54
3.59k
599.48k
100.00M
Figure No.-4
Amplitude spectrums of three outputs are shown in fig.,
all the spectrums have the BW of 1 MHz and the resultant
spectrum have some band with more or less than 1MHz
due to inversion of two other outputs bandwidths at the
-200.0
1.0p
129.2p
16.7n
2.2u
278.3u
35.9m
Frequency [Hz]
4.6
599.5
77.4k
Figure No.-5
It seems that the power content of three output
waveforms are concentrated at nearly 3MHz frequency
10.0M
and it is also seems that the power spectrums are
contented at the center frequency 1MHz due to the
combination of different singe tone signals.
T
600.00n
TOTAL NOISE IN THE OUTPUTS
T
2.00
FOURIER SPECTRUM OF VF1 ,VF2 & VF3
1.50
Amplitude [V]
Total noise (V)
400.00n
OSC1_Ch1
OSC1_Ch2
VF1
VF2
VF3
1.00
200.00n
VF1
OSC1_Ch1
OSC1_Ch2
VF1
VF2
VF3
VF3
VF1=VF2
VF2
VF2
500.00m
0.00
1
10
100
VF3
0.00
0
1M
2M
3M
Frequency (Hz)
Figure No.-6
Amplitude spectrum of different stage waveforms are
shown in fig. Here the spectrums are concentrated at
1MHz center frequency .Since the signals are combined
signals they produced the more number of spectrums
centered at 1MHz. frequency
T
1k
Frequency (Hz)
10k
100k
1M
Figure No.-8
From the characteristics of noise effect, it seems that the
noise effect in the input of Quasi floating gate is more in
low frequency range and is reduce by the Quasi floating
gates and gives the less effect noise at the output and
also it seems that there is no noise effect in the Quasi
floating gate during the multi input signal flow.
T
300.00
20.00
VF3
Signal to Noise [dB]
250.00
15.00
Power [W]
POWER SPECTRUM OF VF1,VF2 & VF3
OSC1_Ch1
OSC1_Ch2
VF1
VF2
VF3
200.00
VF2
150.00
VF1
10.00
VF2
OSC1_Ch1
OSC1_Ch2
VF1
VF2
VF3
100.00
1
5.00
VF3
0.00
0
1M
2M
3M
Frequency (Hz)
Figure No.-7
Power spectrums of different waveforms are shown in fig.
and it is seems that all the power spectrums are
concentrated at the center frequency at 1MHz because of
same frequency signals are provided.
10
100
1k
Frequency (Hz)
10k
100k
1M
Figure No.-9
Since the noise effect is more at inputs of quasi floating
gate, hence the signal to noise ratio is less as shown in
figure where as the S/N ratio is almost constant after 1
kHz frequency. At the output of Quasi floating gate the
noise effect is very less than that of inputs of Quasi
floating gate and hence, S/N ratio is more than that of
inputs and is almost constant after 1khz.The overall noise
effect in quasi floating gate is almost zero up to 1MHz but
due to the signal variation at the combined signal the
signal to noise ratio is reducing with increasing frequency.
IV
CONCLUSION
In this paper, we have analyzed high frequency with low
noise effect. The signal to noise ratio performance is
enhanced so that noise is reduced in comparison to
floating gate. By using high pass filter in output, the
results of corresponding multi input signal is obtained as
in multi output forms where noise will be reduced.
REFERENCE
[1] A. Torralba, J. Galan, C. Lujan Martinez, R.G.
Carvajal, “Comparision of Programmable linear
resistors based on quasi floating gate MOSFETs”
Proceedings of IEEE. International symposium on
circuits and systems, 2008, Washington, USA,
pp. 1712-1716.
[2] D. Kahng, S.M. Sze, “A floating-gate and its
application to memory devices”, The Bell System
Technical Journal, 46(4): 1288-1295, 1967, IEEE
standard definitions and characterization of using
floating – gate semiconductor arrays, Feb. 1999.
[3] H. Gundersen, Y. Berg, “Max and Min
functions using multi-valued recharged semifloating gate circuits.: IEEE, ISCAS 2004, Vol. II,
857-860.
[4] I. Seo and R.M. Fox, “Comparison of
quasi/pseudo floating gate techniques and low
voltage application” Aanlog Integer circuits signal
process, 2006, 47, 183-192.
[5] J. Ramirez–Angulo, C.A. Urquidi, R.G.
Carvajal and F.M. Chavero, “Very low-voltage
analog signal processing based on quais-floating
gate transistor”, IEEE, J. Solid State
Circuits, 2004, 39, 434-442
[6] K. Ramesh, S.K. Dash, G. Devi, “Comparison
of floating gate and pseudo floating gate
techniques” IJAIEM, Vol.2, Issue 11, Nov. 2013.
[7] L. Topor – Kaminski, P. Holajn, “Multiple input
floating gate MOS transistor in Analogue
electronic circuit.” Bulletin of polish Academy of
Science, Vol. 52, No. 3, 2004.
[8] R. Gupta, S. Sharma, “Voltage controlled
resister using quasi-floating gate MOSFET” 2013,
7(10), 16-25.
[9] S.K. Bisoi, G. Devi, “Multi-input Multi Pseudo
Floating Gates used in circuits”, IJEAT, Vol.3,
Issue-1, Oct-2013.
[10] S.K. Bisoi, G. Devi, “Multi-input Quasi
Floating Gate MOSFETs with analog inverter
used in circuits ”, IJARET, Vol.5, Issue-1, JAN2014.pp 138-144