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Analog Electronics Class 3
Vosi, Vois Drift, Ib, Ib Drift, Ibos
Sep 20, 2011
Gaussian (or Normal)
Distribution
18%
±1 St Dev
±3 St Dev
16%
14%
12%
10%
8%
6%
4%
2%
0%
145
140
135
130
125
120
115
110
105
100
95
90
85
80
75
70
65
68% within ±1 standard deviation
99.7% within ±3 standard deviations
Single Ended Limit
No Min Spec
Mean = 4.80
Std. dev. = 0.13
Max = 5.2uA
Mean = 4.8uA
Iq 25C, OPA827
1400
A typical MIN and MAX range is
at least +/-3σ:
1192
1200
1000
911
Mean = Typical
800
717
612
MAX = Mean + 3σ (or greater)
600
400
2
4 28
<4.08
<4.15
<4.23
<4.30
<4.38
89
24 6
0
1
0
0
>5.50
0
<5.50
0
<5.43
0
126
<5.35
0
<4.00
200
MIN = Mean - 3σ (or greater)
269
217
<5.20
Count
806
[V]
Num = 5004
-3σ
+3σ
99.7% of all
Measurements
<5.28
<5.13
<5.05
<4.98
<4.90
<4.83
<4.75
<4.68
<4.60
<4.53
<4.45
0
Double Ended Limit
Min = -150uV
Mean = 0uV
Max = 150uV
Typ = 75uV
=σ
Symmetrical Limits:
Max = 150uV is +/-150uV
Mean = often approximately zero
Typical = Mean + σ ≈ σ
Max = + 3σ (or greater)
-3σ
+3σ
99.7% of all
Measurements
Min = - 3σ (or smaller)
Yield – Percentage of devices that Pass Test
Min = -150uV
Failures
Mean = 0uV
-3σ
Max = 150uV
+3σ
99.7% of all
Measurements
Question: What is the probability of a failure?
Answer:0.3%
Failures
Yield – Multiple Tests
Probability that two or more events occur
P(A ∩ B ∩ C) = P(A) x P(B) x P(C)
If we assume that we set all the limits to +/-3σ
What is the probability that we see a failure for five (5) different tests:
P = (0.997) (0.997) (0.997) (0.997) (0.997) = (0.997)5 = .985
98.5% or a 1.5% chance of failure.
For a quad device (four times the number of parameters):
P = = (0.997)20 = .941
94.1% or a 5.9% chance of failure
Production Worthy Test Limits
Two Sided Testing
Number of
Parameters
Tested
1 Sigma 2 Sigma 3 Sigma 4 Sigma 5 Sigma
1
68.3%
95.4%
99.7%
99.99% 100.00%
3
31.8%
87.0%
99.2%
99.98% 100.00%
5
14.8%
79.2%
98.7%
99.97% 100.00%
10
2.2%
62.8%
97.3%
99.94% 100.00%
25
0.0%
31.2%
93.5%
99.84% 100.00%
50
0.0%
9.7%
87.4%
99.68% 100.00%
100
0.0%
0.9%
76.3%
99.37%
99.99%
150
0.0%
0.1%
66.7%
99.05%
99.99%
NPN Bipolar Transistor
c
+
Ic
Ib
Vce
b
+
Ie
Vbe
-
NPN Transistor – Current Controlled Device
Ic = Ib x β
Ie = Ib + Ic
Vbe = +0.7V typical
BVceo = Collector Emitter Breakdown voltage, base open
BVebo = Emitter Base Breakdown Voltage Collector Open
e
-
N-Channel Depletion Mode JFET
d
+
Id
g
Vds
Vgs
+
s
N-Channel Depletion JFET Transistor – Voltage Controlled Device
Vgs_off = Negative Voltage (no current)
Vgs max = 0V (maximum current)
Vp = Pinch off Voltage Which determines
Triode Region (ohmic region) Vp < Vgs < 0V, Vds < Vgs - Vp
Saturation Region (pinch-off region) Vp < Vgs < 0V, Vds > Vgs - Vp
N-Channel Enhancement Mode MOSFET
d
+
Id
Vds
g
+
Vgs
-
s
-
Don’t over voltage gate to
source junction
N-Channel JFET Transistor – Voltage Controlled Device
Vgs_off = Negative Voltage (no current)
Vgs max = 0V (maximum current)
Vp = Pinch off Voltage Which determines
LM741 Op-Amp Schematic
Simplified Op-Amp
Vcc
Cc
R1
Vin1
R2
-K
Q1
Vin2
IS1
Q2
Unity
Gain
Vout
Short Overview Of
Common Mode Voltage (Vcm)
Vcm is the average
voltage on the inputs of
the op-amp. If the op-amp
is closed loop the voltage
is approximately the same
on both inputs.
More detail next class!
Two Definitions
Percent_Error
Percent_Error
Measured  Ideal
Ideal
 100
Measured  Ideal
Measuremen_Range
 100
Common Def
Measurement Def
Note: The sign of the error tells you if your measured result is greater
or less then expected. A common error is to ignore the sign or reverse
the order of measured and Ideal.
What is the error?
R1 1k
R1 10k
+12V
Vout
10mV
+
V1 0
-12V
Percent_Error
Percent_Error
Measured  Ideal
Ideal
 100
Measured  Ideal
Measuremen_Range
 100
10mV  0V
0V
10mV  0V
24V
Common Def

0.042%
Measurement Def
IQ – Supply Current With No Load
IQ
Vcc
Cc
R1
Vin1
R2
-K
Q1
Vin2
IS1
Q2
Unity
Gain
Vout
No
Load
Data Sheet Specification Table
The power supply current is typically 17uA, maximum 25uA at 25C with
no load connected.
Data Sheet Specification Table
The power supply current is a maximum 28uA from -40C to 125C with no
load connected.
Absolute Maximum Ratings
Exceeding maximum ratings will cause
permanent damage to the device.
Absolute Maximum Ratings
Vcc
Absolute Maxim
Supply Rating
7V for OPA333
Cc
R1
Vin1
R2
-K
Q1
Vin2
IS1
Q2
Unity
Gain
Vout
Another Example OPA277
+/-15V is a 30V supply. If you
exceed 36V you will damage
the device. Also note the
“operating range” specification
of ±18V
OP-AMP Iq
(Max
High
Grade)
Iq max
(over
temp)
Specified
Power Supply
Range
Operating
Range
(or Max)
Technology
OPA369
1.2uA
1.49uA
1.8V to 5.5V
7V max
Low Power, Zero Crossover
OPA129
1.8mA
--na--
±15V
±5V to ±18V
±18V max
Difet – Ultra Low Bias
Current
OPA627
7.5mA
--na--
±15V
±4.5V to ±18V
±18V max
Difet – Precision High
Speed
OPA333
25uA
28uA
1.8V to 5.5V
7V max
Zero Drift CMOS
OPA277
825uA
900uA
±5V to ±15V
±2V to ±18V
36V max
Precision Bipolar
OPA211
4.5mA
6mA
±2.25V to ±18V
40V max
Precision Bipolar
OPA827
5.2mA
6mA
±4V to ±18V
40V max
JFET input, Bipolar,
Precision
OPA350
7.5mA
8.5mA
2.7V to 5.5V
7V max
CMOS
OPA835
350uA
365uA
2.5V to 5.5V
5.5V max
High Speed Bipolar
LM741
2.8mA
--na--
±15V
±22V max
Bipolar commodity
OPA333
OPA277
Iq + Output Current
IAM2 = Iq + Iout
= 415uA + 5.05mA
= 5.465mA
Iq + Output Current (low Rf)
IAM1 = Iq + Iout
= 415uA + 10mA
= 10.415mA
Iq + Output Current (low Rf, No Load)
IAM1 = Iq + Iout
= 415uA + 5mA
= 5.415mA
Input Offset
Vcc
Input offset from
Mismatch of
input transistors
Cc
R1
Vin1
R2
-K
Q1
Vin2
IS1
Q2
Unity
Gain
Vout
OPA333
OPA333
OPA827
OPA827
How is Vos Defined, Simulate it!
Drift Slope – Positive and Negative
OPA835
OPA835
For this example Vos drift is defined:
 
V os
Vos T1  Vos ( 25C)
T
T1  25C
Drift Slope – Common Definition
Vosi at Temp
160
140
(-40C, 100uV)
120
(85C, 150uV)
Vosi (uV)
100
80
60
40
(25C, 30uV)
20
0
-40
-20
0
20
40
60
Temp (degC)
Δ Vos
ΔT
Δ Vos
ΔT
=
=
 
 
Vos T1  Vos( 25C) + Vos T1  Vos( 25C)
T 1  T2
100μV  30μV + 150μV  30μV
85C  ( 40C)
= 1.52
μV
C
80
100
Drift Slope – Positive and Negative
(common definition)
 
 
V os
Vos T1  Vos ( 25C) + Vos T1  Vos ( 25C)
T
T1  T2
• Absolute value makes all results positive.
• Actual drift may be positive or negative.
OPA827
Warm Up
OPA277
Typical offset = 10uV
Initial error is 10% of typical.
Application Example
R1 1k
R2 99k
Vout = (1mV+ 0.1mV)*(100)
= 110mV
-
Vosi
0.1mV
+
R3 1k
+
Vin 1m
What is the percentage error?
Input Offset Drift Calculations
R1 1k
R2 99k
-
Vosi drift
1.5uV/C x (T – 25C)
+
Vosi
Initial +
Drift
+1.5uV/C
Vosi
Initial +
Drift
-1.5uV/C
-25C
25uV
175uV
0C
62.5uV
137.5uV
25C
100uV
100uV
50C
137.5uV
62.5uV
85C
190uV
10uV
125C
250uV
-50uV
+
Vosi
0.1mV
R3 1k
+
Vout
Temp
(C)
Vin 1m
Vosi = Vosi_room + Vosi_drift ( T  25C)
Example calculations:
μV
Vosi = 100μV + 1.5
 [ ( 25C)  25C] = 100μV
C
At 25C
μV
Vosi = 100μV + 1.5
 [ ( 125C)  25C] = 250μV
C
At 125C
OP-AMP
Offset
(max)
(high grade)
Vosi Drift
(max)
(high grade)
Technology
OPA333
10uV
0.05uV/C
Zero Drift CMOS
OPA277
20uV
0.15uV/C
Precision Bipolar
OPA211
50uV
1.5uV/C
Precision Bipolar
OPA827
150uV
1.5uV/C
(Typ only)
JFET input, Bipolar, Precision
OPA350
500uV
4uV/C
(Typ only)
CMOS
OPA835
1850uV
13.5uV/C
High Speed Bipolar
LM741
3000uV
15uV/C
Bipolar commodity
SimpleVccBipolar (No Ib Cancelation)
R1
R2
Ib1
Q1
Vin1
Vin2
Ib2
Q2
Bias current in Bipolar amplifiers is from Base
Current. It is typically larger then FET and it
flows into the input terminals.
Input offset current is the difference between
the two currents. It is typically smaller then Ib
for this simple configuration.
Ibos = Ib1 – Ib2
IS1
Bipolar with Ib Cancelation
Vcc
Ib
Cancel
Circuit
R1
R2
Ib1
Vin1
Vin2
Σ
Q1
Σ
Ibos = Ib1 – Ib2
IS1
Ib2
Ib
Cancel
Circuit
Q2
The input bias currents are mirrored and
summed back in to cancel the bias current.
This has the effect of significantly reducing
input Ib. Note that when this is done, Ib can
flow in both directions. Also Ibos is no longer
smaller then Ib.
Vcc
Bias current in MOSFET amplifiers
is mainly from leakage into ESD
diodes.
Vcc
R1
R2
Q1
Q2
Ib1
Vin1
Vcc
Vin2
Ib2
IS1
OP-AMP
Bias Current
(Max)
(high grade)
Ib at max
temp
Technology
OPA129
100fA
20pA typ
(doubles
every 10C)
Difet – Ultra Low Bias Current
OPA627
5pA
1nA
Difet – Precision High Speed
OPA333
70pA
150pA typ
Zero Drift CMOS
OPA277
1nA
2nA max
Precision Bipolar
OPA211
125nA
200nA
Precision Bipolar
OPA827
50pA
50nA max
JFET input, Bipolar, Precision
OPA350
10pA
500pA typ
CMOS
OPA835
400nA
530nA
High Speed Bipolar
LM741
80nA
0.2uA max
Bipolar commodity
OPA277
OPA333
CMOS Chopper amplifier:
Bipolar amplifier:
In this case the bias current is not
strongly effected by temperature.
In this case you see a dramatic
increase in bias current at 75C
OPA350
OPA333
CMOS amplifier:
CMOS Chopper amplifier:
In this case you see a dramatic
increase in bias current at 25C.
Note the logarithmic graph.
Shows that Vcm has an effect on
Ib.
Ib Calculation
Using nodal analysis
OPA211 At High Temp
R1 1k
Vin
R1
+
Vin  Vout
Rf
+ Ib = 0
Vin
Vin 

Vout = Rf   Ib +
+

R1
Rf


R2 99k
Using superposition set Vin=0V
0
0 
Vout = Rf   Ib +
+
= Ib  Rf
R1
Rf 


Ib 200nA
-
Ib 150nA
Ib 200nA
R3 1k
+
In this example
Vin 1m
Vout_Ib = ( 200nA)  ( 99kΩ) = 20mV
99
Vout_vin = 1mV 
+ 1  = 100mV
1

Vout_total = 20mV_100mV = 120mV
OPA188 Macro Model
No temperature
effects are
simulated. In our
models.
Ib, and Vosi at
25C. Typical
Values are the
target.
Simulating
Hand Calculation
Ib2n
Ib1n
R2 1k
R4 1k
R5 10k
R3 100k
VV-
Vout2
-
R1 100k
+
+
VG1
U3 OPA2188
U1 OPA2188
Vout1
+ Vos1 -
+
Ib1p
+
+
V+
+ Vos2 Vout1
V+
Simulated = 11.65mV
Calculated = 24.9mV
Vout1 = (Vos1 + Ib1p x R1) x Gain1 + Ib1n x R3
Vout1 = (6uV +160pA x 100k)x101 + 160pA x 100k = 2.238mV
Vout2 = (Vout1 + Vos2) x Gain2 + Ib2n x R5
Vout2 = (2.238mV + 6uV) x 11 + 160pA x 10k = 24.9mV
Why Sim <> Calculated
Ib2n
Ib1n
R2 1k
R4 1k
R5 10k
R3 100k
VV-
Vout2
-
R1 100k
+
+
VG1
U3 OPA2188
U1 OPA2188
Vout1
+ Vos1 -
+
Ib1p
+
+
V+
+ Vos2 -
Simulated = 11.65mV
Vout1
V+
Calculated1 = 24.9mV
Calculated2 = 11.22mV
Vout1 = ( - Vos1 + Ib1p x R1) x Gain1 + Ib1n x R3
(both 1 and 2 are possible)
Vout1 = (6uV -160pA x 100k)x101 + 160pA x 100k = 1.026mV
Vout2 = (Vout1 - Vos2) x Gain2 + Ib2n x R5
Vout2 = (1.026mV - 6uV) x 11 + 160pA x 10k = 11.22mV
Dominant Terms – Vos1 and Ib1p
Ib2n
Ib1n
R2 1k
R4 1k
R5 10k
R3 100k
VV-
Vout2
-
R1 100k
+
+
VG1
U3 OPA2188
+
U1 OPA2188
Vout1
+ Vos1 -
+
Ib1p
+
V+
+ Vos2 Vout1
V+
Vout1 = (Vos1 + Ib1p x R1) x Gain1 + Ib1n x R3
Vout1 = (6uV +160pA x 100k)x101 + 160pA x 100k = 2.238mV
Vout1 = (6uV +16uV)x101 + 160pA x 100k = 2.238mV
Vout1 = 1.01mV + 16uV = 2.238mV
Vout2 = (Vout1 + Vos2) x Gain2 + Ib2n x R5
Vout2 = (2.238mV + 6uV) x 11 + 160pA x 10k = 24.9mV
1. For the circuit below: Calculate and simulate the typical and maximum output
error voltage from Ib and Vosi.
RIN 100k
RF 1M
V3 1
VEE 18
++
Vout
U1 OPA170
VCC 18
2. For the circuit above: What is the dominant error source? Ib, or Vosi What
is the percentage error?
3. For the circuit below: Calculate and simulate the current flowing into each
supply.
RIN 100k
RF 1M
V3 1
VEE 18
++
Vout
U1 OPA170
VCC 18
3. Which of the circuits below will be damaged by power supply over voltage.
Which are outside the specified range but will not cause damage? Which are
inside the specified range?
R2 1k
R1 10k
R2 1k
R1 10k
+5V
+5V
-
-
Vout
+
+
Vout
+
+
U1 OPA333
V1 3
U1 OPA333
V1 3
+2V
R2 1k
-1V
R1 10k
R2 1k
R1 10k
+1.6V
+4V
-
-
Vout
+
V1 .1
+
Vout
+
U1 OPA333
+
V1 .1
-4V
U1 OPA333