Download 1030.Multi-phase stackable controllers for Non

Multi-Phase, Stackable Controllers
For Non- Portable Application
Nancy Zhang
Applications Engineer
Computing Power Management
1
Agenda
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Introduction
TPS40140 Dual Phase Stackable Controller
TPS40180 Single Phase Stackable Features
New 4-phase TPS40140EVM Performance
Conclusions
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Traditional Multiphase Buck
Controller
Advantages:
• Exactly match the phase numbers required by applications
Disadvantages:
• Hard to re-use the design for different applications
• No flexibility to expand the system for higher current
requirement
• Hard to layout for increased phase numbers
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Stackable Buck Controller Solution
Flexibility!!
Advantages:
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Very flexible for system expansion
Can easily stack with the same converter to achieve higher power
Identical stackable design block reducing layout complexity
Interleaved phases reduces input ripple for multiphase and multi-output applications
Very good for universal power solution design
Dynamic Phase Management
Single part number easy for part number and production control
Disadvantages:
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None
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Universal Stackable Building Blocks
Build ANY size Power supply with just 2 parts !!!!
TOOL BOX
Single Phase
Two Phase
Tps40180
Single phase
Block
Tps40180
Tps40140
Two phase
Block
Tps40140
Dual Output
Tps40140
Dual Output
Block
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Multiphase - Single Output
Single phase application (up to 25A)
Vin
Vo
Tps40180
Single phase
Block
Vin
Vin
Tps40140
Two phase
Block
Vo
Tps40180
Single phase
Block
COMP
Vo
CLKIO
or
Tps40180
Single phase
Block
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Multiphase - Single Output
Three phase output application (up to 75A)
Vin
Tps40180
Single phase
Block
Vo
Tps40140
Two phase
Block
Four phase output application (up to 100A)
Vin
Tps40140
Two phase
Block
Tps40140
Two phase
Block
Vo
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Multiple Output Rails
Three Output Rails with Synchronization
Vin
Tps40180
Single phase
Block
Vo1
Vin
Tps40180
Single phase
Block
Tps40180
Single phase
Block
Vo2
Tps40180
Single phase
Block
Vo1
or
Vo2
Tps40140
Dual Output
Block
Vo3
Vo3
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TPS40140 Dual-Phase Stackable Controller
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1V to 40V Input Voltage Range
•Supports multi bus rails
Internal 5V regulator
•No need for external 5Vbias
0.7V to 5.8V Output Voltage Range
•Easy-to-use solution for voltage rails up to 40A
Dual-phase Interleaved up to 16 phases
•Reduced Input, Output Ripple, Save input, output caps
Programmable switching frequency up to 1MHz •Optimized Efficiency and high power density
0.5% 0.7V reference voltage
•Tight Output Voltage Accuracy
Current mode control with forced current sharing•Supports all MLCC Designs
Support pre-biased outputs
•No output glitch when loads are pre-charged
Power sharing from different input voltage rail •Optimized input current from input rail
True remote sense differential amplifier
•Improve regulation and ease layout constrains
Programmable input under voltage lockout
•Flexibility design
Resistive or Inductor DCR current sensing
•Complete Control, power sequencing and system protection
PGOOD, OCP, OVP, UVP
•High Power Density, Excellent Thermal Performance
36pin QFN Thermally Enhanced Package
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Servers, Notebook/Netbook Computers
Networking Equipment
Telecommunications Equipment
Graphic Cards and Internet Serves
Low-voltage, Point-Of-Load Converters
DC Power Distributed System
Available
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TPS40140 Key Features
Stackable!!!
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Selectable Dual-Output or 2-Phase
Interleaved Operation, Stackable up to 16 Phases
VDD From 4.5 V to 15 V, With Internal 5V Regulator
VOUT From 0.7 V to 5.8 V
True Remote Sensing Differential Amplifier
Programmable Switching Frequency Up to 1MHz/Phase
Soft Start without/with Pre-biased Output
Resistive Divider Sets Input Under voltage Lockout
Resistive or Inductors DCR Current Sensing
Peak Current Mode Control with Forced Current Sharing
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Functional Diagram
Phase1 Driver
Current Loop1
Voltage Loop1
COMPx
Voltage Loop2
Current Loop2
Phase2 Driver
UVLOx Enable
PHSEL
CLKIO
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Stackable Configurations
ILIM2
BP5
ILIM2
VIN
VIN
EN
EN
EN
CLKIO
CLKIO
CLKIO
PG
RT
GND
VOUT
RGND
TPS40140 SLAVE
MODULE
COMP
L
SEL
PG
GND
TPS40140 SLAVE
MODULE
VOUT
L
L
VOUT
C
L
L
C
PG
COMP
SEL
C
SEL
VOUT
C
COMP
C
VIN
BP5
L
BP5
C
ILIM2
GND
TPS40140 MASTER
MODULE
• TPS40140 can be stackable up to 16 phases with synchronization
• One TPS40140 is configured as master and the other chips are configured
as slave
• Three wire connections are required: CLKIO, COMP, PHSEL
– CLKIO synchronize all the chips
– COMP force the current balance
– PHSEL provides the right phase information
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Digital Synchronization Scheme
PHSEL Pin:
• There are two CLK schemes in the design,
• The 6-Phase CLK scheme is to achieve symmetric phase balance for a 6phase or 12-phase converter
• The 8-Phase CLK scheme is to achieve symmetric phase balance for 2,4,8,16
phase converter
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Digital Synchronization Scheme
PHSEL Pin:
14
For example: 4-phase Configuration
PHSEL Pin:
R
• One phase resistor is connected to the PHSEL pin.
• COMP and CLKIO pins are connected together
• R=39.2k
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For example: 3-phase + Single Channel
Configuration
PHSEL Pin:
• M_Ch1, M_Ch2 and S_Ch1 construct the 3-phase converter, S_Ch2
is the single channel output
• The master chip is not only voltage loop master, also the CLK
master
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Master/ Slave Operation
CLKIO Pin:
• Only
three pins connection are required
CLKIO, PHSEL,
COMP (if current sharing)
• Required a 10k resistor connected
from CLKIO to GND
at Master- Slave operation
When the master device is shut down or power off, the master CLKIO
Pin goes to a high impedance state and there is no other active discharge part.
The slave controllers looks at the CLKIO line to determine if the system is
supposed to be running or not. A level below 0.5V on CLKIO is required.
This 10k resistor will ensure the CLKIO line falls to GND quickly
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How to Disable Slave Modules?
• Case 1: Parallel module without CLK distribution
UVLO_CEx Pin
– This application is mainly for module makers to do current sharing between
modules with a single pin
– The Pin is COMP for TPS40140 application
– One Module is set to master and the other modules are set to slave
– The slave modules can be disabled by toggle the UVLO_CEx pin to GND.
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How to Disable Slave Modules?
• Case 2: for stackable applications with distributed CLK
– To disable a slave module, the UVLO pin might not be directly pulled to
GND that will also pull down the CLK
MASTER
VREG is turned off when Both UVLO pins
are shorted to GND, then the CLK signal at
CLKIO pin is also clamped to GND by D1.
CLKIO
SLAVE
VDD
5V regulator
VREG
U1
UVLO-CE1
UVLO-CE2
C1
R1
U2
BP5
D1
CLKIO
LOGIC
U3
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How to Disable Slave Modules?
• Case 2: for stackable applications with distributed CLK
– Method1: Short one UVLO pin to GND while the other
UVLO pin is still higher than 1.5V
• This will shut down one channel and the other channel is still running
or in standby mode(1.5V<UVLO<2V)
– Method2: Held UVLO pin to be less than 2V and higher than
1.5V, so the chip is in standby mode
– Method3: Ground the PHSEL pin of the master that will shut
off all the slave modules, but the master is still running
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How to Disable Slave Modules?
• Case 2: for stackable applications with distributed CLK
– Method 4: Use a jumper to disconnect the CLK to the slave
module
MASTER
CLKIO
SLAVE
VDD
5V regulator
VREG
U1
UVLO-CE1
C1
R1
U2
UVLO-CE2
BP5
D1
CLKIO
SW1
LOGIC
U3
to other
Slaves
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How to Disable Slave Modules?
• Case 2: for stackable applications with distributed CLK
– Method 5: Turn off all the modules including the master by
disconnect the PHSEL resistor string
TPS40140
20uA
MASTER
CLKIO
PHSEL
R2
TPS40140
CLKIO SLAVE 2
When SW2 is open, the PHSEL Pin at the master
will rise to be over 4V and stop the master
controller, hence the slave modules are also
ceased.
PHSEL
R1
TPS40140
SLAVE 1
CLKIO
PHSEL
SW2
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Remote Sense
VOUT and GSNS Pin
• The unity gain differential amplifier has a high bandwidth to
achieve improved regulation at user defined point of load and
eases layout constrains.
• The output voltage is sensed between the VOUT and GSNS pins.
• The output voltage programming divider is connected to the
output of the amplifier, the DIFFO pin.
• Output 0.7V to 5.8V Voltage Range
• You can bypass differential amplifier. Just short VSNS,GSNS to
GND and leave DIFFO open
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Output Voltage Setting
DIFFO Pin
• Two resistors, R1 and RBIAS sets the output voltage
Or DIFFO
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Programmable Switching Frequency
RT pin
Master:
• Frequency Setting by Rt
• Can synchronize to external clock
Slave:
• RT pin tied to BP5
1.041
Rt  1.33 * (39.2 *103 * f PH
 7)
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Where
– fPH is the phase switching frequency in
kHz
– Rt is in kΩ
– There are two clock scheme in the chip
called 8-phase and 6-phase scheme.
– This equation gives the resistor
selection for a 8-phase scheme. For a 6phase scheme, the switching frequency
is 4/3 times higher
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Start Up and Shut Down Sequence
It shows a typical start up with the VDD applied to the controller and then the
UVLO-CEx being enabled. Shut down occurs when the VDD is removed.
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Soft Start without Pre-biased Output
TRKx Pin
Master:
• When UVLO_CEx is high and POR is cleared, the external soft start capacitor is charged
with 12-μA.
• The rising voltage across the capacitor serves as a reference for the error amplifier
• When TRK pin reaches the level of the reference voltage 0.7V, the converter’s output
reaches the regulation point
• When TRK pin voltage reaches 1.4 V, the PGOOD pin goes high at this time.
Slave:
Tie TRKx pin to BP5 for track function
Css: Soft start capacitor in Farads
Css connected from TRKx to GND
Tss: Soft start time in seconds
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Soft Start with Pre-biased Output
TRKx Pin (Master):
• When UVLO_CEx is high and POR is cleared, the external soft start capacitor is
charged with 6-μA until the TRK pin voltage is equal to the FB voltage
• When the first PWM pulse occurs, the charging current is increased to 12-μA. The
rising voltage across the capacitor serves as a reference for the error amplifier
• When TRK pin voltage reaches the level of the reference voltage 0.7V, the
converter’s output reaches the regulation point
•When TRK pin voltage reaches 1.4 V, the PGOOD pin goes high at this time.
•TRK pin voltage continues to rise to 2.4V which is clamped internally
•If the pre-biased output voltage is greater than the regulation voltage, the controller
does not start.
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Soft Start with Pre-biased Output
TRKx Pin:
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Programmable Under Voltage Lock Out
UVLO_CEx Pin
• A resistor divider is connected to UVLO_CEx pins
• Works as Enable function
• The controller begins to work when the voltage on the
UVLO_CEx pins is over 2V.
• The internal regulators are enabled when the voltage
on the UVLO_CEx pins exceeds 1.5 V, but switching
commences when the voltage is 2 V.
• This pin can be used to disable individual output for
dual channel configuration; for master-slave configuration
• UVLO hysteresis is only 40mV (Add three components
to improve hysteresis to 1V or 2V)
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UVLO Hysteresis Improved Circuit
Add R39(39.2k), D5 and C21(47pF) increase hysteresis from 40mV to 2V
LDRVx
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Current Sensing Scheme
CSx and CSRTx Pin
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TPS40140 uses Inductor DCR or sensing resistor to obtaining current feedback
information. DCR sensing is preferred as it is a lossless approach.
If the R1C1 time constant is matched to the L/DCR time constant, the voltage
across C1 will be equal to the voltage across DCR. A good starting point is
equating C1 = 0.1uF. Then R1 is calculated below.
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Current Sensing Scheme
CSx and CSRTx Pin
• The peak voltage of Vc should not exceed ±60 mV because that is
the maximum differential input voltage of the current sensing amplifier.
• If the voltage Vc exceeds ±60 mV, a resistor can be added in
parallel with C1 to provide the voltage attenuation.
The ratio
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Current Sensing Scheme
CSx and CSRTx Pin
• As mentioned in the previous slide, the maximum differential
input voltage of the CS amplifier is +/-60mV
• The offset voltage is +/-2mV that will affect the current sharing
accuracy
– i.e. DCR=1mohm, the sensing current tolerance is 2A
• The CS amplifier gain is typically 13
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Sub-harmonics Consideration
Inductor Selection
• Sub-harmonics in peak current mode control systems can cause
pulse skipping
• To avoid sub-harmonics make the inductor current rising slope
smaller than 2 x Vramp.
• The following equation gives the L/DCR consideration achieve
this
Where Vin is input voltage, Vramp is the internal ramp voltage of 0.5V, and Ac
is the current sensing amplifier gain of 12.5.
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Current Balance
COMPx Pin
• A 2-phase single output configuration is used here as an
example
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Current Balance
COMPx Pin
•The sensed current is amplified with a ratio of 12.5 and then is subtracted from
COMP.
• The subtracted voltage Ve is then compared with the ramp to generate the duty
cycle command.
• COMP is the same for the two channels. Also, the two ramps are also the same in
magnitude although with 180 degree phase shift.
• So, i.e. 1st channel has current I  I , then Ve1 is decreased, hence the duty
cycle of 1st channel is reduced that will reduce the current in that channel and
then bring back to current balance.
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Current Balance
COMPx Pin
1.
2.
Vout
* RAMP
Vin
Ipeak 
Rsns *12.5
Ipeak: inductor peak current
Vshr: ramp valley voltage
RAMP: it is equal to 0.5V
(COMP  Vshr ) 
The currents are balanced
because they have the same COMP, Vshr and RAMP
Then the tolerance of inductor DCR (Rsns)
will be the peak current tolerance.
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Current Balance
COMPx Pin
• To parallel modules without optimized phase shift, Single pin is
required for current balance.
• The TRK1 pin in the slave chip should be tied to +5V to disable the error amplifier.
• The COMP pins are tied together to force current balancing.
• Vshr pins do not have to be connected because Vshr is very accurate between chips.
Its tolerance is a few mVs.
So with the same equation shown above, we can find the paralleled channels are current balanced.
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Over Current Protection
ILIMx and VSHARE Pin (Master):
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If the over-current condition persists for seven (7) clock cycles the converter shuts down and initiates a
hiccup mode restart.
In hiccup mode, the TRKx pin is periodically charged and discharged.
After seven hiccup cycles, the controller attempts another soft-start cycle to restore normal operation.
If the overload condition persists, the controller returns to the hiccup mode.
ILIMx Pin(Slave):
Tied to GND
Over Current Setting By R1, R2
on lLIMx and VSHARE pin
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Over Current Protection
ILIMx and VSHARE Pin:
• U7 shows the over current protection.
If COMP voltage is greater than the ILIM
voltage, over current occurs.
• VOUT, VSHR and the 20uA current
source from ILIM pin will determine the
ILIM voltage
• IPEAK is the peak value of the phase
current
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Over Current Protection
• How to calculate R1 and R2?
Vo * 0.5
Vlim 
 DCR *13 * Ipeak  Vshr  V
Vin
V  31mV
for 8-phase CLK scheme
V  42mV
for 6-phase CLK scheme
Ilim voltage is also set by R1 and R2
Vlim
R2
R1
 I lim * ( R1 // R 2)  Vshr *
 Vo *
R1  R 2
R1  R 2
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Over Current Protection
• How to calculate R1 and R2?
We have calculation spreadsheet
to help calculate R1, R2
R1 
I pk * DCR *13  V 
0.5
*1.8
Vin
0.5
) * 20uA
Vin
0.5
I pk * DCR *13  V 
*1.8
Vin
R2 
0.5
* 20uA
Vin
(1 
Example: for Vin=12V, with 8-phase CLK scheme:
R1  0.678 * I pk * DCR  5.53
R2  15.6 * I pk * DCR  127.2
With 6-phase CLK scheme:
DCR unit in mohm, Ipeak unit in Amp
Ipeak is the phase current
R1 and R2 unit in Kohm
R1  0.678 * I pk * DCR  6.1
R2  15.6 * I pk * DCR  140.4
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Fault Protection
Fault Masking Operation
• If the TRKx pin voltage is externally limited below the 1.4-V threshold, the controller does not
respond to an undervoltage fault and the PGOOD output remains low.
• The overcurrent protection continues to terminate PWM cycle every time the threshold is
exceeded, but the hiccup mode is not entered.
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Peak Current Mode Control Loop Compensation
Peak Current Mode Control Transfer Function
Type II Compensator is employed to compensate the loop
COMP
Vo or DIFFO
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TPS40140 Loop Compensation Spreadsheet
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TPS40140 Component Selection Spreadsheet
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TPS40180 New features
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Single phase operation
Stackable to 8 Phases, multiple controllers can occupy any
phase
eTrimTM allow the user to trim the reference voltage in system.
Tis will tighten overall output tolerance by trimming out errors
caused by resistor divider and other system tolerance.
Thermal warning and thermal shutdown
Most Features are similar to TPS40140
24 pin QFN
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New 4-Phase TPS40140EVM
SYMBOL
TYP
UNIT
VIN
12
V
VOUT
1.2
V
IOUT
80
A
fsw
300
kHz
CSD16406Q3
CSD16401Q5
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New 4-Phase TPS40140EVM Schematic1
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New 4-Phase TPS40140EVM Schematic2
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EVM Performance
4-Phase TPS40140EVM Efficiency
100
80
70
60
50
Load Regulation
40
30
20
10
4-Phase TPS40140EVM
Load Regulation
0
0
10
20
30
40
50
60
70
80
ILOAD - Load Current - A
8.0 V
12.0 V
Efficiency
12Vin, 1.2V/80A,
Efficiency: 90.4%
14.0 V
VOUT - Output Voltage - V
h - Efficiency - %
90
1.224
1.22
1.216
1.212
1.208
1.204
1.2
1.196
1.192
1.188
1.184
1.18
1.176
0
10
20
30
40
50
60
70
80
ILOAD - Load Current - A
8.0 V
12.0 V
14.0 V
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EVM Performance
4 Phase TPS40140EVM Current Share
25.00
Phase Current(A0
20.00
Phase1
15.00
Phase2
Phase3
10.00
Phase4
5.00
Bode Plot
12Vin, 1.2V/80A,
Crossover frequency: 54.58kHz
Phase margin: 54.65deg, Gain margin: 12.78dB
0.00
0
10
20
30
40
50
60
70
80
Output Current(A)
Current Share
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EVM Performance
Output Transient
12Vin, 1.2Vout/ 20A-80A
Output Ripple
12Vin, 1.2Vout/ 40A
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EVM Performance
Switching Node
12Vin, 1.2Vout/ 40A
Start up
12Vin, 1.2Vout/ 40A
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Input Bulk Capacitor Savings
3-phase, 12Vin,
1.2V out, 50A load
Input Bulk
Capacitance (uF)
Input Voltage
Ripple (mV) *
No syn
With syn
47uF*6
47uF*6
75
20
With syn
With syn
With syn
47uF*5
47uF*4
47uF*2
21
30
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* The input ripple voltage is measured across the input bulk capacitor
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Input Bulk Capacitor Savings
• From the experiment results, the input bulk capacitance can be
reduced
• The system power density can be largely improved
• The cost can be reduced by saving the 47uF/16V SP capacitors
• The input capacitor life time and reliability can be improved due
to less ac current
• No high slew rate current provided from the input stage will
reduce the EMI effect ( the high ac current loop is very small
and constrained on the module)
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Conclusions
TPS40140/TPS40180 Dual/ Single Phase
Stackable Controller
Stackable
• Makes design flexible and easy to achieve the desired
power capability
• Efficiency is highly improved compared with noninterleaved multiphase converter
• Input bulk capacitor savings
• Output ripple reduction
• Excellent phase current sharing
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[email protected]
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