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Wide-VIN Supervised, Multi-Rail Power Supply With LowVoltage MCU Core Rail Reference Design Guide
Description
The TIDA-01369 reference design is a power supply
designed for providing power to lock-step, dual-core
microcontrollers (MCUs) with functional safety
architectures. Both power management products used
in the design operate over a wide input voltage range
to support direct connection to an automotive battery
line or industrial DC supply. MCUs from multiple
vendors are supported by the design. The core and I/O
rails for the MCU are supervised. If a fault condition
occurs, the MCU is disabled by hardware RESET
output signals, and the latching fault condition is
reported to the MCU after normal operation is
resumed. The reference design emphasizes the
complementary features of three products from TI: the
TPS653850-Q1 power management IC (PMIC), the
TPS57160-Q1 asynchronous DC-DC buck converter,
and the TPS3700-Q1 overvoltage and undervoltage
supervisor.
Resources
TIDA-01369
TPS653850-Q1 or
TPS653853-Q1
TPS57160-Q1
TPS3700-Q1
Features
• Supports Power and Sequencing Requirements of
Various Lock-Step Dual Core MCUs
• Low-Voltage MCU Core Rail with 3% Voltage
Ripple From 5-mA to 1.5-A Load
• Optimized for Hercules TMS570xxxxx Product
Family
• Supervisor and Reset Signals for MCU With
Latching Fault Condition
• Operates over a Wide VIN from 2.6 V to 36 V
(Ideal for Automotive Battery or Industrial Supplies)
Applications
• Automotive - Electric Power Steering (EPS)
• Industrial
– Elevators and Escalators
– Rail Transport Motor and Actuator Control
– Brushless DC Motor Drives
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3.5 V to 18 V
12V Typ.
1.23 V, 1.5 A max
Œ-Filter and
Reverse Voltage protection
VCC_Core
VIN
PH
VDDIO
VDD5
TPS57160-Q1
VDDIO
VDD
INA+
VDD5
uC_RST
OUTA
TPS3700-Q1
ENABLE
uC_RST
OUTB
INB-
VDD6
6V Preregulator
VBATP (Buck-Boost)
VDD6
Wake-up
from CAN
CANWU
5V LDO
IGN
from Ignition
VSOUT1
VSOUT2
VSOUT1
VSOUT2
Sensor LDOs
uC_RST
NRES
ERROR/WDI
4
SPI
VDD5
VDD5
TPS653850-Q1
VCC_Core
VDD3-5
µC Core Rail
VDD3-5
VDD3/5
3.3 or 5V LDO
µC IO Rail
VDDIO
Lock-Step
Dual-Core MCU
Diagnostics
Analog
Digital
DIAG_OUT
GPIO
ADC
uC_RST
3
(Ex: Hercules
TMS570LS1224)
RESET
SPI
ERROR
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
TIDUCK6B – December 2016 – Revised May 2017
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Wide-VIN Supervised, Multi-Rail Power Supply With Low-Voltage MCU Core
Rail Reference Design Guide
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1
System Overview
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1
System Overview
1.1
System Description
The TIDA-01369 reference design operates directly from a 2.6 V to 36 V car battery input and DC-to-DC
converters provide all supply rails for the MCU, while additional integrated LDOs provide power for the
controller area network (CAN) transceivers, inputs and outputs (I/Os), analog-to-digital converter (ADC),
and sensors (protected sensor supply LDO).
The design focuses on the TPS653850-Q1 (or TPS653853-Q1) as a flexible multi-rail power supply (or
PMIC) using LDOs to generate five low-noise voltage rails from a preregulated 6-V buck-boost supply for
CAN, I/Os, ADC, and sensors. The TPS57160-Q1, an asynchronous buck converter, supplies power to
the MCU core (nominal 1.23 V for the TMS570LS1224 in this assembly variation of the design) directly
from the battery. The sequencing and load regulation of the MCU are critical and, as a result, the MCU
core rail is supervised by the TPS3700-Q1. The other rails are supervised and monitored by the
TPS65385x-Q1.
Both the TPS65385x-Q1 and TPS57160-Q1 offer a wide-VIN range supporting start-stop and cold crank
conditions down to 2.6 V, resets, and then alerts the MCU of overvoltage (OV) or undervoltage (UV) fault
conditions on the MCU rails.
1.2
Key System Specifications
Table 1. Key System Specifications
PARAMETER
2
SPECIFICATIONS
DETAILS
Input power source
Direct connection to Automotive Battery line or Industrial DC
Power Supply. Fully operational between VBAT_IN of 4 V to 36 V
(after battery power up with VBAT_IN = 7 to 36 V). Cold-crank
supported with VBAT_IN range between 2.6 V and 36 V targeted
by design
Section 1.4
MCU core rail supply output
Vout_BUCK = 1.23 V nominal (1.14 V minimum, 1.32 V maximum)
Section 1.4.2
Low MCU core rail ripple voltage
±4% Vout_BUCK
Section 1.4.2
MCU core rail voltage supervisor
Fault condition triggered within ±5% Vout_BUCK
Section 1.4.3
Combined MCU reset signals for
overvoltage or undervoltage monitoring
Overvoltage and undervoltage conditions of supervisor analogOR with reset pin of multi-rail power supply. All open-drain
outputs required.
Power Management IC (PMIC) or Multirail power supply for lock-step dual core
MCUs
Provides multiple output voltages and digital signals in the
correct order, with the correct timing for power-up and powerdown sequencing, overvoltage and undervoltage monitoring, and
diagnostics to provide power fault information to MCU.
Section 1.4.1
Preregulator
Preregulator operates as a step-up (boost) or step-down (buck)
converter to generate 6 V from VBAT_IN for all power rails other
than MCU core rail.
Section 1.4.1
CAN power supply output
Provides a regulated 5-V rail at 200 mA for a CAN transceiver
Section 1.4.1
I/O supply output
Provides voltage rail for MCU inputs and outputs (I/O) with a
reference voltage of 3.3 V or 5 V at 350 mA
Section 1.4.1
Sensor supply output
Two low-noise sensor (or ADC) supply rails: VSOUT1 = 3.3 V or
5 V at 120 mA
VSOUT2 = 3.3 V or 5 V at 20 mA
Section 1.4.1
Operating temperature
AEC-Q100 Grade 1, –40ºC to +125ºC
Section 1.4
Low EMI emissions
Input π-filter and low-pass output filter added for optional CISPR
25 emissions testing
Section 1.3
Working environment
Automotive and industrial applications
Section 1.4
Form Factor
Smallest layout achievable to meet the above requirements with
all AEC-Q100 ICs, AEC-Q101 semiconductors, and AEC-Q200
passive components
Section 5.3
Wide-VIN Supervised, Multi-Rail Power Supply With Low-Voltage MCU Core
Rail Reference Design Guide
Section 1.4
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System Overview
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1.3
Block Diagram
3.5 V to 18 V
12V Typ.
1.23 V, 1.5 A max
Œ-Filter and
Reverse Voltage protection
VCC_Core
VIN
PH
VDDIO
VDD5
TPS57160-Q1
VDDIO
VDD
INA+
VDD5
uC_RST
OUTA
TPS3700-Q1
ENABLE
uC_RST
OUTB
INB-
VDD6
6V Preregulator
VBATP (Buck-Boost)
VDD6
Wake-up
from CAN
CANWU
5V LDO
VSOUT1
VSOUT2
TPS653850-Q1
VSOUT1
VSOUT2
Sensor LDOs
uC_RST
NRES
ERROR/WDI
4
SPI
VDD5
VDD5
IGN
from Ignition
VCC_Core
VDD3-5
µC Core Rail
VDD3-5
VDD3/5
3.3 or 5V LDO
µC IO Rail
VDDIO
Lock-Step
Dual-Core MCU
Diagnostics
Analog
Digital
DIAG_OUT
GPIO
ADC
uC_RST
3
(Ex: Hercules
TMS570LS1224)
RESET
SPI
ERROR
Copyright © 2016, Texas Instruments Incorporated
1.4
Highlighted Products
This reference design features the following devices, see corresponding data sheets for additional
information:
• TPS653850-Q1
• TPS57160-Q1
• TPS3700-Q1
1.4.1
TPS653850-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant Applications
The following excerpt from the TPS653850-Q1 data sheet highlights the features relevant to the operation
of this reference design (see Figure 1):
The TPS653850-Q1 (or TPS653853-Q1) device is a multi-rail power supply designed to supply
microcontrollers (MCUs) in safety relevant applications, such as those found in the automotive
industry. The device supports microcontrollers with dual-core lockstep (LS) or loosely coupled
architectures (LC).
The TPS653850-Q1 device integrates multiple supply rails to power the MCU, CAN, or FlexRay, and
external sensors. A buck-boost converter with internal FETs converts the input battery voltage between
2.3 V and 36 V to a 6-V preregulator output that supplies the other regulators. An integrated charge
pump provides an overdrive voltage for the internal regulators, and can also be used to drive an
external NMOS FET as reverse battery protection. The device supports wakeup from an ignition (IGN)
signal or wakeup from a CAN transceiver signal.
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An independent-voltage monitoring unit inside the device monitors undervoltage and overvoltage on all
internal supply rails and regulator outputs of the battery supply. Regulator current limits and
temperature protections are also implemented. The TPS653850-Q1 device features a question-answer
watchdog, MCU error-signal monitor, clock monitoring on internal oscillator, self-check on clock
monitor, cyclic redundancy check (CRC) on non-volatile memory and SPI communication, a diagnostic
output pin allowing MCU to observe device internal analog and digital signals, a reset circuit for the
MCU and an enable output to disable external power-stages on any detected system-failure. A built-in
self-test (BIST) allows for monitoring the device functionality at start-up. A dedicated DIAGNOSTIC
state allows the MCU to check TPS653850-Q1 functionality.
Battery Voltage
(2.3 V to 36 V)
TPS653850-Q1
5V
CAN wakeup
CAN Interface
Multirail Power Supply
Ignition
EN
FETs
Voltage Monitor
3.3 V / 5 V
DRVOFF
ENDRV
RESET
Error Signal
Monitor
6 × PWM
3 × HS
NRES
ERROR
Dual-Core Lock-Step
Microcontroller
Watchdog
SPI
DIAG_OUT
M
Motor-Driver
(DRV320x)
3 × LS
SPI
SPI
DIAG_OUT
3.3 V, 5 V
Sensor 1
Sensor 2
3.3 V / 5 V
Copyright © 2016, Texas Instruments Incorporated
Figure 1. TPS653850-Q1 Simplified Schematic
The TPS653850-Q1 was chosen as the central component in this reference design, because it is a flexible
multirail power supply frequently used as a PMIC for a variety of lock-step dual-core MCUs in automotive
and industrial applications. It provides low-noise voltage rails at 3.3 V and 5 V at varying output currents
from its five integrated LDOs. All of these LDOs are powered from a single buck-boost preregulator,
VDD6, that operates over a wide VIN from 2.3 V to 36 V. The uses for these LDOs are flexible, but for
simplicity are indicated in the data sheet to work ideally as power supplies for a CAN transceiver (VDD5 =
5 V, 200 mA), general purpose input/output (GPIO) signals (VDDIO = 3.3 V or 5 V), an analog-to-digital
converter (VDD3_5 = 3.3 V or 5 V), and sensors (VSOUT1, VSOUT2).
In addition to the multiple flexible power rails, the TPS653850-Q1 has multiple monitoring and diagnostics
features designed to work well with the MCU in safety applications where fault conditions on the power
supply may occur. These features help with start-up and sequencing of the MCU in the reference design .
The other power products used in TIDA-01369 were selected to integrate seamlessly with existing voltage
monitoring features of the TPS653850-Q1.
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Rail Reference Design Guide
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Designers and engineers who are not yet familiar with the TPS653850-Q1 are probably familiar with its
predecessor, the TPS65381A-Q1. The TIDA-01369 TI design is intended to assist designers that have
used the TPS65381A-Q1 in previous applications and want to quickly design a new power supply with the
TPS653850-Q1 or TPS653853-Q1.
1.4.2
TPS57160-Q1 1.5-A 60-V Step-Down DC-DC Converter With Eco-mode™ Control
The following excerpt from the TPS57160-Q1 data sheet highlights the features relevant to the operation
of this reference design (Figure 2):
• The TPS57160-Q1 device is a 60-V 1.5-A step-down regulator with an integrated high-side MOSFET.
Current-mode control provides simple external compensation and flexible component selection. A lowripple pulse-skip mode reduces the no load, input supply current to 116 µA. Using the enable pin,
shutdown supply current is reduced to 1.5 µA.
• Undervoltage lockout is set internally at 2.5 V, but can be increased using the enable pin. The output
voltage startup ramp is controlled by the slow-start pin that can also be configured for sequencing or
tracking. An open-drain power-good signal indicates the output is within 92% to 109% of the nominal
voltage.
• A wide switching-frequency range allows efficiency and external component size to be optimized.
Frequency foldback and thermal shutdown protects the part during an overload condition.
PWRGD
6
EN
3
VIN
2
Shutdown
UO
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
PWM
Comparator
VSENSE 7
Current
Sense
1 BOOT
Logic
And
PWM Latch
SS/TR 4
Shutdown
Slope
Compensation
10 PH
COMP 8
11 POWERPAD
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
TPS57160 Block Diagram
9 GND
5
RT/CLK
Figure 2. TPS57160-Q1 Block Diagram
The TPS57160-Q1 was chosen as the component that will generate the low-voltage core rail for the MCU
in this TI design, because it has the uncommon ability to generate a low-output voltage (0.8 V minimum)
across a wide range of load current (5 mA to 1.5 A) with low-voltage ripple (≈2 to 3%) from a very wide
input-voltage range (3.5 to 60 V). Due to these electrical characteristics, the TPS57160-Q1 can operate in
parallel to the TPS653850-Q1 and be connected directly to the automotive battery or industrial power
supply and does not need an additional preregulator to generate a mid-voltage rail. Generating all power
rails for an MCU from two ICs reduces overall BOM cost and size of the reference design.
In addition to the desirable input and output characteristics, another output voltage rail in the system can
enable the TPS57160-Q1. In the case of the TIDA-01369 design, the VDD5 rail from the TPS653850-Q1.
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In applications where a smaller input voltage range is specified, the TPS57140-Q1 is suitable to substitute
in this design when the maximum input voltage is less than 42 Volts.
1.4.3
TPS3700-Q1 Automotive, High-Voltage (18V) Window Comparator with Overvoltage and
Undervoltage Detection
The following excerpt from the TPS3700-Q1 data sheet highlights the features relevant to the operation of
this reference design (see Figure 3):
The TPS3700-Q1 wide-supply voltage window comparator operates over a 1.8-V to 18-V range. The
device has two high-accuracy comparators with an internal 400-mV reference and two open-drain
outputs rated to 18 V for overvoltage and undervoltage detection. The TPS3700-Q1 device can be a
window comparator or two independent voltage monitors; the monitored voltage can be set with the
use of external resistors.
When the voltage at the INA+ terminal drops below (VIT+ – Vhys), the OUTA terminal goes low. When
the voltage returns above the respective threshold (VIT+), the OUTA terminal goes high. When the
voltage at the INB– terminal rises above VIT+, the OUTB terminal goes low. When the voltage drops
below the respective threshold (VIT+ – Vhys), OUTB terminal goes high. Both comparators in the
TPS3700-Q1 device include built-in hysteresis for filtering to reject brief glitches, which ensures stable
output operation without false triggers.
VDD
INA+
OUTA
OUTB
INB–
Reference
GND
Figure 3. TPS3700-Q1 Block Diagram
The TPS3700-Q1 was chosen as the component that will supervise the low-voltage core rail for the MCU
in this reference design, simply because the voltage generated by the TPS57160-Q1 needs to be
regulated to within VCC ±7% and the power-good signal of the TPS57160-Q1 triggers a fault at 92% for
undervoltage and at 109% for overvoltage. To ensure the MCU is held in reset before its supply voltage is
outside the recommended operating conditions, a target of VCC ±5% is set for monitoring this voltage.
Since the TPS57160-Q1 will trigger a fault condition too late, the TPS3700-Q1 supervises the MCU core
rail to within a tighter tolerance; this ensures the TIDA-01369 meets the shutdown sequencing
requirements and avoids causing damage to the MCU. The OUTA+ and OUTB- overvoltage and
undervoltage outputs of the TPS3700-Q1 are both open-drain and are analog-OR’d with the NRES pin of
the TPS653850-Q1 to create a single RESET signal for the MCU generated from three hardware sources.
2
System Design Theory
In this system, designing for the core rail of the MCU is the most critical consideration. Setting the output
voltage and reducing ripple of the TPS57160-Q1 to generate the MCU core rail supply is explained in
Section 2.1, as well as enabling the TPS57160-Q1 from the VDD5 rail of the TPS653850-Q1. Monitoring
the voltage of the MCU core rail with the TPS3700-Q1 is explained in Section 2.2
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The TPS653850-Q1 is a large focus of the design both in physical size and because of the many power
rails it generates, but thankfully it is a highly integrated PMIC and the layout is more important than the
theory of operation. The layout of the TPS653850-Q1 is covered in detail in Section 5.3.1.
2.1
2.1.1
TPS57160-Q1 Design Theory
Adjusting the TPS57160-Q1 Output Voltage
The output voltage of the TPS57160-Q1 is set with a resistor divider from the output node to the VSENSE
pin. The recommendation is to use 1% tolerance or better divider resistors. In this reference design, use
Equation 1 to calculate R1 by sweeping common values for R2 that have 1% tolerance or better. Since
efficiency at light loads is less critical than voltage ripple due to noise, smaller value resistors were
considered as better than larger values that would slightly improve efficiency. If the values are too high,
the regulator is more susceptible to noise, and voltage errors from the VSENSE input current are
noticeable.
R1 = R2 ?
VOUT - 0.8 V
0.8 V
(1)
For supporting the TMS570LS1224 in the Hercules family of lock-step dual-core MCUs, the design
requires a nominal supply voltage of 1.23 V. After testing the TPS57160-Q1EVM for voltage ripple at the
selected switching frequency (see Section 2.1.2), it is determined that under light-loading conditions the
average output voltage will be higher than the nominal voltage at full load. For this reason, there is a
requirement for VOUT of 1.21 V to offset the difference and ensure regulation at light load. The feedback
resistors are calculated according to Equation 1. A value of 76.8 kΩ is selected for R2 and a resistance of
40.2 kΩ is calculated for R1. Details of this calculation are provided as a note in the schematic of the
design (refer to Section 5.1).
2.1.2
Switching Frequency of the TPS57160-Q1
The switching frequency of the TPS57160-Q1 is adjustable over a wide range from approximately 100 kHz
to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given
switching frequency, use Equation 2. To reduce the solution size, it is typical to set the switching
frequency as high as possible, but this reference design requires that the voltage ripple for the MCU core
rail be very small and that the maximum input voltage be high. In addition, a lower-switching frequency
increases efficiency, which may offset the efficiency lost by using smaller value resistors in Section 2.1.1.
For these reasons, this design uses a switching frequency of approximately 400 kHz, which results in an
RT resistance of 300 kΩ. Details of this calculation are in a note in the schematic of the design (refer to
Section 5.1).
206033
RT (kW) =
fSW (kHz)1.0888
(2)
As a result of the lower-switching frequency, the requirement is for larger inductance. A value of 22 µH is
selected by following additional equations provided in the TPS57160-Q1 data sheet that are outside the
scope of this document.
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2.2
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TPS3700-Q1 Design Theory
The TPS3700-Q1 monitors the supply voltage of the MCU for overvoltage and undervoltage conditions. If
either fault condition is detected, the device triggers an active-low reset signal that is combined with the
NRES pin of the TPS653850-Q1 in an analog-OR configuration to hold the MCU in reset until the fault
condition is no longer present.
The VDD5 rail of the TPS653850-Q1 supplies the TPS3700-Q1power and the voltage monitored is the
Vout_BUCK rail of the TPS57160-Q1, so the application requires that the TPS3700-Q1 monitor a voltage
other than VDD. For this reason, the diagram in Figure 4 from the TPS3700-Q1 data sheet most closely
resembles that application in this reference design.
VMON
(26.4 V to 21.7 V)
1.8 V to 18 V
R1
(2.61 MW)
VDD
OUTA
INA+
R2
(8.06 kW)
Device
OUTB
INB–
R3
(40.2 kW)
To a reset or enable input
of the system.
GND
Figure 4. TPS3700-Q1 Monitoring a Voltage Other than VDD
For the circuit to work as expected, the voltage that triggers an overvoltage condition for the TPS3700-Q1,
VMON(OV), must be lower than the maximum-recommended VCC-supply voltage of the MCU (1.32 V) and
higher than the maximum-output voltage of the TPS57160-Q1 under normal operating conditions. In
addition, the voltage that triggers an undervoltage condition for the TPS3700-Q1, VMON(UV), must be higher
than the maximum-recommended VCC-supply voltage of the MCU (1.14 V) and lower than the minimumoutput voltage of the TPS57160-Q1 under normal operating conditions.
To meet these requirements, three equations from the TPS3700-Q1 data sheet are used, taking into
consideration the tolerance (in %) of the resistors. These equations are in Equation 3, Equation 4, and
Equation 5, where VIT+ is a constant 0.4 V and Vhys is a constant of 0.0055 V.
RT = R1 + R2 + R3
R3 =
R2 =
RT
VMON(OV)
RT
VMON(UV)
(3)
´ VIT+
(4)
´ (VIT+ - Vhys)
- R3
(5)
A similar method is in Section 2.1.1 to determine the correct resistance values for the TPS3700-Q1,
except three values need to be selected instead of only two. A list of available resistors with 1% tolerance
or better is made for R1, then R2 and R3 are calculated, and the total resistance, RT, is monitored such
that the current through the divider is approximately 100-times higher than the input current at the INA+
and INB– terminals. The resistors can have high values to minimize current consumption as a result of
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low-input bias current without adding significant error to the resistive divider. VMON(OV) is set to be 1.29 V
and VMON(UV) is set to be 1.17 V to monitor ±5% above the nominal 1.23-V supply voltage of the MCU. A
value of 76.8 kΩ is selected for R1 then a resistance of 3.24 kΩ is calculated for R2 and a resistance of
36.1 kΩ is calculated for R2. Details of this calculation are provided as a note in the schematic of the
design (refer to Section 5.1).
If the MCU in the final application requires a different core rail voltage than the TMS570LS1224, then all
five resistances for the TPS57160-Q1 output voltage and TPS3700-Q1 monitoring voltage must be
recalculated to ensure proper operation of the design.
3
Getting Started Hardware and Software
3.1
Hardware
TIDA-01369 printed-circuit board (PCB), shown in Figure 5, was designed in four main sections:
• Input voltage filter and reverse current protection shared by the TPS653850-Q1 and TPS57160-Q1
• TPS653850-Q1 power path (Top of PCB only)
• TPS57160-Q1 power path and TPS3700-Q1 supervisor (Bottom of PCB only)
• The USB2ANY and headers for communicating from a PC to the TPS653850-Q1 via SPI using a miniUSB cable
The total PCB size is 100-mm long by 100-mm wide (3.94 in x 3.94 in), but this is larger than the final
solution size.
1.43 in (36.3 mm)
3.94 in (100 mm)
Since the USB2ANY section is for debug purposes only, this is not part of the final solution. The rest of
the solution (input filter and reverse current protection, TPS653850-Q1, TPS57160-Q1, TPS3700-Q1, and
required passive components) is essential to the reference design and the estimated total solution size is
89-mm long by 36.3-mm wide (3.5 in x 1.43 in). These measurements are also shown in Figure 5.
3.5 in (89 mm)
3.94 in (100 mm)
Red
Purple
Input voltage filter and reverse
current protection
Blue
TPS57160-Q1 power path and
TPS3700-Q1 supervisor
TPS653850-Q1 power path
Gray
USB2ANY and headers
(for debug only, not required)
Figure 5. Hardware Sections and Measurements
The necessary input and output power rails and signals all have connectors, headers, and/or test points
named with easy to understand abbreviations (as opposed to default Jxx or TPxx silk screen annotations)
and are located strategically for easy access while testing the solution. These connection points and all
ground (GND) test points are highlighted in Figure 6.
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Connectors
Input
ƒ
VBAT_IN(+), PGND(-)
ƒ
J1 Pin1 (+), Pin 2(-)
Output (MCU Core Rail)
ƒ
Bout_BUCK(+), Buck_GND(-)
ƒ
J2 Pin1 (+), Pin 2(-)
Headers
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
J3 = OUTA+ (Pin 1), OUTB- (Pin 2), and
NRES (Pin 3)
J4 = NRES LED (D3) power from USB
J5 = ENDRV LED (D4) power from USB
J6 = USB mini-B receptacle (power for
USB2ANY)
J7 = USB2ANY re-flash enable
J8-J15 = Signals that can optionally
connect to U4, the USB2ANY processor
(Pins 1-2 shorted to connect
TPS653850-Q1 signal to USB2ANY)
Test Points
Power ± 7 Yellow Test Points
ƒ
VBAT_BUCK and VBATP ± Input Supply
ƒ
VDD6 ± TPS653850-Q1 pre-regulator
ƒ
VDD5 ± TPS653850-Q1 5-V LDO
ƒ
VDD3/5 ± TPS653850-Q1 3.3-V LDO
ƒ
VDDIO ± TPS653850-Q1 I/O LDO (3.3 V)
ƒ
VSOUT1 ± TPS653850-Q1 Sensor 1 LDO
ƒ
VSOUT2 ± TPS653850-Q1 Sensor 2 LDO
GND ± 10 Black Test Points distributed around
the board
PGND ± 2
White
Test Points
Input Signals ± 2 Orange Test Points
ƒ
IGN ± TPS653850-Q1 Ignition wake-up
ƒ
CANWU ± TPS653850-Q1 CAN wake-up
Test/Output Signals ± 4 Metal SMD Test Points
ƒ
SW ± TPS57160-Q1 switching node
ƒ
SS ± TPS57160-Q1 switching node
ƒ
COMP ± TPS57160-Q1 switching node
ƒ
uC_RST ± Active-low MCU reset signal
Figure 6. Hardware Connectors, Headers, and Test Points
The following sections explain how to setup the hardware, connect equipment required to power the board
and take measurements, and perform basic measurements to verify steady-state operation of the design.
3.1.1
Equipment
The following equipment is needed to verify the operation of the design and complete the Section 4:
• TIDA-01369 Reference Design PCB → Device Under Test, or DUT
• Main Power Supply → A single DC-power supply capable of supplying 2.5 V to 36 V at 1.5 A
• Arbitrary Waveform Generator (or 2nd Power Supply) → A waveform generator or 2nd DC-Power
Supply capable of providing a +3.3V pulse for 500 µs (with negligible current consumption) to the
CANWU pin
• Cables → Use AWG20 or lower gauge (thicker) cables, <1.5 meters in length
• Multimeter (DMM) → One DMM, capable of measuring DC voltage and DC current
• 4-Channel Oscilloscope → An oscilloscope with 4-Channels to perform the measurements in the
Section 4
The hardware setup of the TIDA-01369 reference design requires a main power supply capable of
delivering 2.5 V to 36 V with sufficient amperes to power both the TPS653850-Q1 and TPS57160-Q1. The
circuit requires the output wattage at VIN ≥ 6 V is approximately 7.25 W, so a conservative input current
limit of 1.5 A will account for losses in the system.
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The output capability of the VDD6 pre-regulator in the TPS653850-Q1 varies as VIN drops below 6 V, and
the TPS57160-Q1 will be in a fault condition if VIN drops below 4.1 V, so the input power required at VIN
< 6 Volts will vary.
3.1.2
Power Supply Settings
The following power supply settings should be used:
• Set the main power supply voltage to 12 V and turn OFF before connecting to the EVM
• Connect the power supply return lead (for example, black cable) to PGND near Pin 2 of J1
• Apply the input power lead (for example, red cable) to VBAT_IN near Pin 1 of J1
• The current limit on the supply should be 1.5 A
• Set the 2nd power supply or waveform generator to create a >500-µs pulse from 0 V to 3.3 V, turn off,
and attach black lead to any GND test point and the red lead to CANWU test point
3.1.3
Initial Jumper Settings
The initial jumper settings for TIDA-01369 are in Table 2 if the hardware is tested without the assistance of
any software or the USB2ANY. To control and monitor the TPS653850-Q1 from a PC, follow the
TPS653850EVM User's Guide setup procedure and alternatively short Pins 1 and 2 of jumpers J8–J15.
Note that when a USB cable is connected from a PC to J6 and the USB2ANY U4 part is powered (LED
D5 on), voltages greater than 3.3 V should not be applied to the IGN or CANWU test points from external
power supplies.
Table 2. Initial Jumper Settings
3.1.4
Header Designator
Signal Name
Pins Shunted Together
J5
ENDRV
Yes (1 and 2 shorted)
J4
NRES
Yes (1 and 2 shorted)
J8-J15
USB2ANY Row of Headers
2 and 3 (USB2ANY to Test Point)
Multimeter (DMM) Connections
Connect the GND lead (for example, black cable) to Buck_GND near Pin 1 of J2 and connect the voltage
lead (for example, red cable) of DMM to Vout_BUCK near Pin 2 of J2. This will be the first steady-state
DC measurement to record the output voltage of the TPS57160-Q1 and is the first entry in Table 3. After
this first measurement, the black GND lead can remain in place or move to any other Test Point labeled
GND or PGND as necessary. The next set of measurements records the output voltages of the
TPS653850-Q1 (Yellow test points) then the digital output signals (used to drive the LEDs in the Software
Setup procedure), so move the red voltage lead around the PCB to measure these points.
3.1.5
Power-Up and Steady-State DC Measurements
Follow the provided steps to power on, wake up, and perform basic steady-state DC measurements of
TIDA-01369 with a digital multimeter (DMM). A summary of the important outputs were measured on the
DUT and recorded in Table 3.
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Table 3. Steady-State DC Measurements
Designator
Output Voltage (V)
Vout_BUCK (or J2, pin 2)
1.23
TPS57160-Q1 output voltage
VDD6
6.0
TPS653850-Q1 preregulator voltage
3.1.6
Description
VDD5
5.0
TPS653850-Q1 5-V LDO output
VDD3/5
3.3
TPS653850-Q1 3.3 or 5-V LDO output
VDDIO
3.3
TPS653850-Q1 I/O LDO output
VSOUT1
0
TPS653850-Q1 Sensor 1 LDO output
VSOUT2
0
TPS653850-Q1 Sensor 2 LDO output
uC_RST
3.3
Analog-OR of TPS3700-Q1 OUTA+, OUTB- pins and TPS653850-Q1 NRES pin
Power-Down
No specific power-down procedures for TIDA-01369 are required. The power-down sequence is handled
automatically by the TIDA-01369 circuitry. When the voltage falls below a certain level, the device uses
the uC_RST signal to begin the MCUs power-down sequence and hold the MCU in reset until a valid
power-up sequence occurs. If the voltage drops below 2.6 V and then rises, as in a “Cold Crank”, then a
warm boot occurs. If the voltage on VBAT_IN drops all the way to 0 V, then a cold boot occurs. More
importantly is the timing of the power-up and power-down sequence, the description is in Section 4.
3.1.7
Oscilloscope Connections
In addition to special equipment used to create line and loading conditions for the load regulation, load
transient, and line regulation tests in Section 4, use a common 4-Channel oscilloscope for all
measurements to record the results. The most common connections of the 4-channels of the oscilloscope
used during testing are shown in Table 4 as a reference for engineers that wish to reproduce the results.
Table 4. Oscilloscope Channel Setup
3.1.8
Scope
Channel
Name
Test Point Designator
Volts or
Amperes
1
VCC
Vout_BUCK
V
10-20 mV/div, AC-coupled or DC-coupled with 1.21-V offset
2
SW
SW
V
2-9 V/div, depending on input voltage (4.1 V to 30 V)
3
nRST
uC_RST
V
2 V/div
4
IL
N/A
A
10-500 mA/div depending on loading conditions, or
10-500 mV/div with 5 A/div current probe and 5x divider ratio on
scope channel
Vertical Scaling
Loading Conditions
Apply a load to the output of the TPS57160-Q1 to evaluate the ability of the buck converter to deliver
power to the desired MCU. The TPS57160-Q1 configuration has a 1.23-V nominal-output voltage and 1.0A maximum load current for evaluation of this circuit for powering the TMS570xxxx family of MCUs. The
loading method varies depending on the test. Use a power-resistor decade box or electronic load for static
loading conditions and a power NFET for dynamic loading conditions, where the load is generated by
driving the gate pin.
Loads may also be applied to the LDOs of the TPS653850-Q1, but these tests were not performed on the
DUT and are not covered in Testing and Results. To fully evaluate the capabilities of the TPS653850-Q1
supply rails, consider using the TPS653850EVM.
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3.2
Software
The software compatible with the TIDA-01369 reference design is the same software used for the
TPS653850EVM, because the TPS653850-Q1 is the only device on the reference design with a digital
interface for communicating with a microcontroller. To control the TPS653850-Q1 from a PC or to receive
diagnostic data and display it in a graphical user interface (GUI), follow the steps provided in the
TPS653850EVM User's Guide.
In the final application, the lock-step dual-core MCU SPI interface would be the master and the
TPS653950-Q1 would be an SPI Slave device so that power fault conditions are reported to and
interpreted by the MCU.
4
Testing and Results
4.1
Test Setup
The following sections describe and show a simplified drawing of the test setups used to generate the
Section 4.2.
4.1.1
Load Regulation
Figure 7 shows the test setup to test how well the MCU core voltage rail operates under loading. A DC
power supply initially set to between 12 V and 14 V is the input power to the TIDA-01369 board. Place a
voltmeter across the output connecters of each output, in addition to an electronic load (or decade box
power resistor load) with an Ammeter to monitor the load current. Apply the load at the output connector
(Vout_BUCK and Buck_GND) of the TPS57160-Q1 MCU core voltage rail. Set the following oscilloscope
channels according to Table 4 and capture the waveforms : Vout_BUCK (VSS), the Switching Node (SW),
uC_RST (nRST), and load current (IL).
Board Under Test
+
DC Power Supply
±
Circuit Output
±
+
Voltmeter
+
±
Ammeter
Electronic Load
Figure 7. Load Regulation Test Setup
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Load Transient
Using the setup in Figure 8, apply a load transient to the TPS57160-Q1 output (across Vout_BUCK and
Buck_GND) to determine how well the voltage rail responds to drastic changes in load. Set a DC power
supply to between 12 V and 14 V for the input power to the TIDA-01369 board. Place an AC-coupled
oscilloscope probe (or DC-coupled probe with 1.21-V offset) with a short ground lead directly across the
output capacitor of the respective voltage rail to capture the changes in Vout_BUCK due to the applied
load step.
To apply a fast load transient, connect a power field-effect transistor (FET) across the output rail under
test. Configure the FET switching performance (minimum load, maximum load, and slew rate) by
modifying the parameters of the function generator. Apply the resulting arbitrary waveform at the gate of
the power FET. The maximum load of the TMS570LS1224 MCU is 370 mA in normal operating mode and
470 mA in BIST mode. Test the loading conditions of 20% (94 mA) to 80% (376 mA) with a slew rate of
2.5 µs (188 mA/µs).
Board Under Test
+
1× Probe
Across output capacitor
DC Power Supply
Oscilloscope
±
System Output
Function
Generator
Figure 8. Load Transient Test Setup
4.1.3
Line Transient
Figure 9 shows the test setup to test a line-transient condition down to 3.9 V at the input of the TPS57160Q1 and TPS653850-Q1. Since the VDD5 rail of the TPS653850-Q1 controls the Enable pin of the
TPS57160-Q1, the output voltages of both ICs are impacted if the pre-regulator (VDD6 pin of the
TPS653850-Q1) can no longer generate a stable 6-V output.
Create the line transient profile down to 3.9 V using a power supply specifically designed for recreating
cold-crank voltage and timing requirements. Apply the load at the output of the TPS57160-Q1. Use the
following oscilloscope channels setup and capture the following waveforms: Vout_BUCK (VSS), input
voltage at VBAT_IN (VIN replacing SW in Table 4), uC_RST (nRST), and the load current (IL).
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Function
Generator
Board Under Test
+
1× Probe
Across output capacitor
Power Amplifier
Oscilloscope
±
Circuit Output
±
+
Electronic Load
Figure 9. Line Transient Test Setup
4.2
Testing Results
Record the test data in Section 4.2.1, Section 4.2.2, and Section 4.2.3 by applying a load at and
measuring the output voltage of the TPS57160-Q1 (across connectors Vout_BUCK and Buck_GND), the
input power supply to the MCU core rail. If a falling edge is captured on the uC_RST signal, this indicates
that the MCU is held in reset as a result of the test due to a fault condition triggered by either the
TPS653850-Q1 or TPS57160-Q1.
4.2.1
Steady-State Load Regulation
The following plots are the test results for the TPS57160-Q1 at steady state using the parameters stated
before the corresponding waveform.
• Input voltage, VBAT_IN = 4.1 V
• The specified full load for the corresponding figures at >470 mA (Figure 10)
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Figure 10. Steady-State Full Load Regulation, Input Voltage of 4.1 V
•
•
Input voltage, VBAT_IN = 12 V
The specified full load for the corresponding figures at >470 mA (Figure 11)
Figure 11. Steady-State Full Load Regulation, Input Voltage of 12 V
•
•
16
Input voltage, VBAT_IN = 30 V
The specified full load for the corresponding figures at >470 mA (Figure 12)
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Figure 12. Steady-State Full Load Regulation, Input Voltage of 30 V
•
•
Input voltage, VBAT_IN = 4.1 V
The specified light load for the corresponding figures at ≈10 mA (Figure 13)
Figure 13. Steady-State Light-Load Regulation, Input Voltage of 4.1 V
•
•
Input voltage, VBAT_IN = 12 V
The specified light load for the corresponding figures at ≈10 mA (Figure 14)
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Figure 14. Steady-State Light Load Regulation, Input Voltage of 12 V
•
•
Input voltage, VBAT_IN = 30 V
The specified light load for the corresponding figures at ≈10 mA (Figure 15)
Figure 15. Steady-State Light Load Regulation, Input Voltage of 30 V
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4.2.2
Load Transient
The following plots are the test results for the TPS57160-Q1 load transient response using the parameters
stated before the corresponding waveform.
• Input voltage, VBAT_IN = 6.9 V (Cold boot threshold of the reference design)
• Load starts at <94 mA, goes to >376 mA in ≈2.5 µs (Figure 16)
Figure 16. Load Transient Response, Input Voltage of 6.9 V
•
•
Input voltage, VBAT_IN = 12 V
Load starts at <94 mA, goes to >376 mA in ≈2.5 µs (Figure 17)
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Figure 17. Load Transient Response, Input Voltage of 14 V
•
•
Input voltage, VBAT_IN = 30 V
Load starts at <94 mA, goes to >376 mA in ≈2.5 µs (Figure 18)
Figure 18. Load Transient Response, Input Voltage of 30 V
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4.2.3
Line Transient Down to 2.6 V
The following plot is the test results for the TPS57160-Q1 line transient response using the parameters
stated before the corresponding waveform.
NOTE: In this case, the uC_RST signal toggles low twice: the first time after the input voltage goes
below 4.1 V, and the second time when the input voltage quickly goes back above 4.1 V and
the TPS57160-Q1 circuit begins to regulate the voltage again. This is expected behavior and
the resulting waveform would look different when the MCU is attached, because the MCU
itself is the load and is put in reset on the first falling edge of the uC_RST signal.
•
•
Full loading conditions at >470 mA
Voltage for VBAT_IN starts at ≈12 V, steps down to 2.6 V, and settles temporarily at ≈5 V(Figure 19)
Figure 19. Line Transient Down to 2.6 V
5
Design Files
5.1
Schematics
To download the schematics, see the design files at TIDA-01369.
5.2
Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-01369.
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PCB Layout Recommendations
As in every switch-mode-supply design, general layout rules apply to the TPS653850-Q1 and the
TPS57160-Q1:
1. Use a solid copper pour for power-ground (PGND) on the same layer as the power path (VBATP on
the top for the TPS653850-Q1 and VBAT_BUCK on the bottom for the TPS57160-Q1)
2. Connect the power ground copper pours to the inner layer ground plane with free vias near the IC and
large passive components such as 1 to 10-µF capacitors and inductors.
3. Use direct connections to the ground plane on an inner layer for Logic, LDOs, and Analog ground
(GND)
4. Place input capacitors as close as possible to the input pins of the IC. This placement is critical and
more important than the output capacitors.
5. Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the
IC.
6. Keep the loop-area formed by phase-node, inductor, output capacitor(s), and PGND as small as
possible.
7. For traces and vias on power lines, keep inductance and resistance as small as possible by using wide
traces and avoid switching layers. If switching layers is needed, use multiple vias with larger drill holes
than vias connected to signal lines.
5.3.1
TPS653850-Q1 Layout Recommendations
The layout guidelines of the TPS653850-Q1 have been followed according to the data sheet.
The following is an excerpt from the Layout section of the TPS653850-Q1 datasheet:
Use the guidelines that follow as the general layout guidelines for the device:
• Use ground planes and ground islands as required for the application and device grounds.
• Minimize parasitic impedance on the critical switching and high current paths.
• Minimize the parasitic impedance by using the widest traces possible.
• Minimize the via parasitic impedance by using multiple vias, especially on high current and
switching nodes.
• Follow printed circuit board (PCB) manufacturing rules and guidelines.
• Follow the layout considerations for the specific application, system thermal requirements, and
functional safety requirements in addition to the device-specific guidelines listed in the following
sections.
For layout guidelines specific to the power grounding (PGND) scheme, the VBATP power supply, the
charge pump capacitor (CP1/2 and VCP pins), the VDD6 buck-boost converter, and the five linear
regulator (LDOs named VDD5, VDD3/5, VDDIO, VSOUT1, and VSOUT2) refer to the TPS653850-Q1
datasheet which also provides a detailed layout example diagram.
In addition to following the layout recommendations of the TPS653850-Q1 datasheet, use the layout of the
TPS653850EVM as the base layout for the reference design before adding the additional components for
the TPS57160-Q1 and TPS3700-Q1 devices.
Make the following modifications for the TPS653850-Q1 layout to ensure the reference design adheres to
the data sheet recommendations:
• Input power path, VBATP and power ground have thick copper pours on the top layer to reduce
resistance to the VBATP pins of the TPS653850-Q1 device (Figure 20)
• The input capacitors are as close as possible to the VDD pins of the device (Figure 21)
• Add no additional components or traces on top of inductor, L3, to eliminate coupling of switching noise
onto those signals (Figure 22)
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VBATP
VBATP
VBATP
PGND
PGND
PGND
PGND
PGND
VBATP
VBATP
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Figure 20. TPS653850-Q1 Input Power Path and Ground Layout
Figure 21. TPS653850-Q1 Input Capacitor Layout
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Figure 22. TPS653850-Q1 Empty Area on Top of Inductor
5.3.2
TPS57160-Q1 Layout Recommendations
The layout guidelines of the TPS57160-Q1 have been followed according to the data sheet.
The following is an excerpt from the Layout section of the TPS57160-Q1 data sheet:
Layout is a critical portion of good power supply design. There are several signal paths that conduct
fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to
generate noise or degrade the power supplies performance. To help eliminate these problems, bypass
the VIN pin to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care
to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of
the catch diode. Refer to Figure 23 for a PCB layout example. Tie the GND pin directly to the
PowerPAD and the IC.
Connect the PowerPAD to any internal PCB ground planes using multiple vias directly under the IC.
Route the PH pin to the cathode of the catch diode and to the output inductor. Because the PH
connection is the switching node, locate the catch diode and output inductor close to the PH pins, and
minimize the area of the PCB conductor to prevent excessive capacitive coupling. For operation at fullrated load, the top-side ground area must provide an adequate heat-dissipating area. The RT/CLK pin
is sensitive to noise, so locate the RT resistor as close as possible to the IC and route with minimal
lengths of trace. Place the additional external components approximately as in Figure 23. It may be
possible to obtain acceptable performance with alternate PCB layouts, however, this layout produces
good results, so use as a guideline.
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Vout
Output
Capacitor
Topside
Ground
Area
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
Output
Inductor
Catch
Diode
PH
VIN
GND
EN
COMP
SS/TR
VSENSE
RT/CLK
PWRGD
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 23. TPS57160-Q1 Layout Example
In addition to following the layout recommendations of the TPS57160-Q1 data sheet, use the layout of the
TPS57160-Q1EVM as a reference for proper layout techniques on an existing PCB. The π-filter layout in
this reference design also closely matches the π-filter in the TPS57160-Q1EVM, because this EVM is
optimized for EMC performance.
The following connections are highlighted for the TPS57160-Q1 layout with images specific to the
reference design:
• Input power path, VBAT_BUCK and power ground have thick copper pours on the bottom layer to
reduce resistance to the VIN pin of the TPS57160-Q1 device (Figure 24)
• The input capacitors are as close as possible to the VIN pin of the device (Figure 25)
• Connect the compensation network ground directly to pin 9 (GND) of the device and the feedback
resistor divider ground directly to the PowerPAD (instead of to a via to the inner layer GND plane)
(Figure 26)
VBATP
PGND
Figure 24. TPS57160-Q1 Input Power Path and Ground Layout
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Figure 25. TPS57160-Q1 Input Capacitor Layout
Figure 26. TPS57160-Q1 Compensation and Feedback Circuit Ground Connections
5.3.3
TPS3700-Q1 Layout Recommendations
The TPS3700-Q1 device needs to be placed as close as possible to the output of the TPS57160-Q1
where it provides power to the MCU. Although the input power and output signals of the TPS3700-Q1 are
not critical, the input signals of the TPS3700-Q1 that monitor the MCU core-rail voltage must monitor the
voltage closer to the MCU VCC pin than the output capacitors of the TPS57160-Q1. In the reference
design, the Vout_BUCK test point is a placeholder for the VCC pin of the MCU. Use this test point as the
connection to monitor the output voltage.
A Kelvin connection, or thin trace that carries little current to monitor voltage accurately, is made from the
Vout_BUCK test point to the first of three resistors in the voltage divider network of the TPS3700-Q1. This
resistor is R1 in the TPS3700-Q1 data sheet and R12 in the reference design. Figure 27 shows the
connections of all three resistors in the voltage divider network (R12, R14, R17) to Vout_BUCK and the
INA+/INB- pins of the TPS3700-Q1.
26
Wide-VIN Supervised, Multi-Rail Power Supply With Low-Voltage MCU Core
Rail Reference Design Guide
TIDUCK6B – December 2016 – Revised May 2017
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Design Files
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Figure 27. TPS3700-Q1 Layout of Resistor Divider Network
5.3.4
Layout Prints
To download the layer plots, see the design files at TIDA-01369.
5.4
Altium Project
To download the Altium project files, see the design files at TIDA-01369.
5.5
Gerber Files
To download the Gerber files, see the design files at TIDA-01369.
5.6
Assembly Drawings
To download the assembly drawings, see the design files at TIDA-01369.
6
Software Files
To download the software files, see the design files at TIDA-01369.
7
Related Documentation
1. Texas Instruments, TPS653850/53EVM User's Guide TPS653850EVM EVM User Guide (SLVUAR6)
2. Texas Instruments, TPS653850-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant
Applications TPS653850-Q1 data sheet (SLVSDV4)
3. Texas Instruments, TPS57160EVM User's Guide (SLVUA80)
4. Texas Instruments, TPS57160-Q1 1.5-A 60-V Step-Down DC-DC Converter With Eco-mode™ Control
TPS57160-Q1 data sheet (SLVSAP1)
5. Texas Instruments, TPS3700-Q1 Window Comparator for Over- and Undervoltage Detection
TPS57160-Q1 data sheet (SLVSCI7)
TIDUCK6B – December 2016 – Revised May 2017
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Rail Reference Design Guide
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27
About the Author
7.1
www.ti.com
Trademarks
All trademarks are the property of their respective owners.
8
About the Author
BRIAN BERNER joined Texas Instruments as an Applications Engineer in 2011 after earning his Bachelor
of Science and Master of Science degrees in Electrical Engineering from Lehigh University. Prior to joining
Integrated Power Management, Brian worked as an applications engineer supporting the TPS6598x family
of USB Type-C and PD Port Controllers. As a member of the Integrated Power Management team, Brian
focuses on broad applications of PMICs and PMUs.
28
Wide-VIN Supervised, Multi-Rail Power Supply With Low-Voltage MCU Core
Rail Reference Design Guide
TIDUCK6B – December 2016 – Revised May 2017
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Copyright © 2016–2017, Texas Instruments Incorporated
Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (January 2017) to B Revision ............................................................................................... Page
•
Changed the part number in two history comments from TPS65380-Q1 to TPS653850-Q1.................................. 28
Changes from Original (December 2016) to A Revision ................................................................................................ Page
•
•
•
•
Changed TPS653850-Q1 from a block diagram to simplified schematic .......................................................... 4
Deleted the reference to the blank section number .................................................................................. 4
Deleted subsections 5.3.1.1 through 5.3.1.5 and TPS653850-Q1 Layout Example figure. ................................... 22
Changed link to TPS653850-Q1 data sheet throughout document ............................................................... 27
TIDUCK6B – December 2016 – Revised May 2017
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Revision History
29
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