Download DATA ACQUISITION

DATA ACQUISITION
Basics of Converter Technology
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Function
Data Sheet Characterizations
Quantization Error and SNR
Gain, Offset Errors
Linearity Errors and THD
SINAD
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DATA ACQUISITION
BASICS
ANALOG VOLTAGE RANGE
VFS
QUANTIZED INTO
2n LEVELS
WHERE n = # OF BITS
Nominal Quantization Step
0 1 2 3 4 5 6 7 8 9 10 11
Nominal Step Size Q = VFS/2n
Highest Voltage Step = VFS – Q
Max Count = 2n –1 (0 is a valid step)
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Quantization Error
Note: Last step occurs
at VFS(N-1)/N under
ideal conditions
Voltage is Measured as
Fraction of a reference
Vref
Quantization Error
VFS = Vref
Ideal 3 Bit A/D Converter Transfer Function
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n
A/D
D/A
• Max Quantization
Error:
Qerr = VFS/(2n) = 1 bit
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SNR = 20 log(2(n-1) * sqrt(6) )
= 20log (2(n-1)) + 20log (sqrt(6))
= 20(n-1)log(2) + 20log (sqrt(6))
= 20nlog(2)-20log(2)+20log (sqrt(6))
= 20nlog(2) + 20log (sqrt(6)/2)
= 6.02n + 1.76
n
A/D
D/A
Sinewave MAX SNRDB = 6.02n + 1.76
• Max Quantization Error, Qerr = VFS/(2n) = 1 bit
• More Resolution (higher n) means less quantization error
• Examples:
VFS = 10V, n = 8 Bit, Qerr = 39.96mV, SNRmax = 49.9DB
VFS = 10V, n = 12Bit, Qerr = 2.44mV, SNRmax = 74.0DB
VFS = 10V, n = 16Bit, Qerr = 0.16mV, SNRmax = 98.1DB
• More Resolution may require, slower speed, higher power
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Offset Error
• Example of ½ Bit Offset Error
• Offset Error: Shifts Ideal Staircase Function Right
(+) or Left (-) by Max Voltage or Max LSBs
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Gain Error
• Gain Error will change the converter “slope”
• Gain Error: Changes Ideal Staircase Function so that
last step is not at VFS(N-1)/N
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Integral Linearity Error: Max Deviation from Ideal Straight Line
(INL: Integral Non-Linearity)
Xfer Curve drawn at midpoint of each input step (ideal vs actual)
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Differential Linearity Error: Max Deviation from Ideal Step Size
(DNL: Differential Non-Linearity)
DNL max > 1 Bit can lead to missing codes
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Linearity Errors Induce Harmonic Distortions
D/A
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SINAD: Signal-to-Noise Ratio and Distortion
ENOB: Effective Number of Bits
• Combination of SNR and THD specifications
• Measure of overall “usable” Dynamic Performance
In Ideal Converter ENOB = n
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Power Supplies are Extremely Important !!
• PSRR: Power Supply Rejection Ratio
Measure of output noise injected by PS noise
• PSRR is function of frequency
Degrades with frequency
A/D converters require “quiet” supply
voltages
Use adequate bypass capacitances
Isolate supply voltages using separate
regulators
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DATA ACQUISITION
A/D Converter Architectures
• Flash
• Integrating
• Successive Approximating
High Speed, High Power
High Resolution, Parallel
Low Resolution, High Speed
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Successive Approximating
(SAR)
END OF CONV
SUCCESSIVE
Decision signal
n-1
n-2
n-3
APPROXIMATION
n
REGISTER
CLOCK
CONTROL
Clock
OUTPUT
n-n
BITS
V Ref
n-1
COMPARATOR
B
BIT
n-2
n-3
D/A
V in
Buffer
Converter
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Integrating
n-1
n-2
n-3
V in
n Output
Bits
COUNTER
Buffer
n-n
CLOCK
COMPARATOR
Clk
Clr
Current
Source
I
CONTROL
C
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FLASH
V Ref
n-1
n-1
n-2
OUTPUT
LOGIC
REGISTER
V in
BUFFER
n-2
n Output
Bits
n-3
n-n
2n –1 COMPARATORS
1
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