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Physics 331, Fall 2008 Lab VI - Exercises 1 LABORATORY VI : Flip-Flops 1 Reading: Simpson Sect. 12.1 - 12.5, 12.8.6 - 12.8.7 Sect. 13.1 - 13.5 Optional reading: Horowitz & Hill Sect. 8.01 - 8.03, 8.16 - 8.18. Introduction In this lab we will explore some digital electronics focusing especially on flip-flop circuits. A flipflop circuit is a binary memory element and forms the basic building block for many memory systems, counters, and other sequential logic circuits, i.e. circuits that respond to a series of inputs rather than merely the present input. A flip-flop has two output terminals and two stable voltage states. When operating correctly, if one of the output terminals is in a high voltage state the other output terminal is in a low voltage state. The output voltages of the two terminals can be flipped (exchanged) very quickly by applying a single input pulse to an appropriate input terminal. The new ”flipped” state of the output terminals is then stable, i.e. it persists even after the input pulse has ended. 2 Laboratory Preliminaries 2.1 Lighting LEDs In the following lab exercise we will be monitoring the output state of our logical devices using light-emitting diodes (LEDs). 220Ω NAND gate light emitting diode (LED) Figure 1: NAND output monitored using an LED An example is shown to the left, where we monitor the output of a NAND gate. The LED will be lit (dark) when the output is in the high (low) state. The 220 Ω resistor in series with the LED controls the current that is drawn from the NAND gate output and, therefore, the LED brightness. A few tens of milliamps is usually adequate and will not harm the output transistors of the 74LS chips (TTL logic) we will be studying. On the right hand side of your breadboard there are pre-installed eight LEDs, labeled LED 0 through LED 7, each already connected in series with its own 220 Ω resistor. For example, to construct the above circuit, you would only need to attach the NAND gate’s output to the LED 0 input on the lower right-hand side of your breadboard. If you prefer, there are LEDs available in colors other than green and you may use them instead. The ”low port” of the light emitting diodes can be recognized by having a flat part on the plastic housing and also a shorter pin (when new). That is, when building the circuit ground should be Physics 331, Fall 2008 Lab VI - Exercises 2 connected to the shorter of the two LED pins and then the flat part will point to ground. This ensures forward bias of the LED and it will light up. 2.2 Handling ICs Remember to always turn off the power on your breadboard before installing or removing an integrated circuit (IC). Also, please use the available tools to install and remove the IC circuits. Doing this by hand will very often bend the pins. 3 3.1 Lab Exercises NAND gate Logic a) Connect a 74LS00 four two-input NAND gate to power (see Fig. 2) and verify for one of the gates that it obeys the NAND truth table. To do so, attach the output to an LED and the inputs to either 0V or +5V. b) Connect several NAND gates together to make an OR gate and verify its correct operation, i.e., determine the truth table. +5V 13 14 12 11 10 8 9 VDD 7400 VSS 1 2 3 4 5 6 7 Top View Figure 2: Quad 2-Input NAND gate 3.2 Set-Reset Flip-Flop Build the set-reset flip-flop shown in Fig. 3a. As indicated in the figure, the inputs to this circuit, labeled S̄ and R̄, are active low, meaning that a change of the output Q results from switching the input from high (+5 V) to low (0 V). Physics 331, Fall 2008 Lab VI - Exercises 3 Investigate the properties of the SR flip-flop by testing a variety of input sequences and noting the results. a) Start with both inputs in the high state. What is Q and Q̄? Leave R̄ high, take S̄ to the low state and back to high. What happens to Q and Q̄? Repeat this operation several times. b) Now leave S̄ high, take R̄ to the low state and back to high. What happens to Q and Q̄? c) Try various other input sequences and summarize your observation. d) Try grounding both inputs of the flip-flop, then returning them simultaneously to high. What happens? (This input state is never used and is called indeterminate) a) +5 V b) S Q 1kΩ Out High Low Q R 1kΩ +5 V Figure 3: a) Set-Reset Flip-Flop b) NAND debounced switch 3.3 Switch Debouncing using a Flip-Flop An important application of flip-flops is as “debouncers” for switches. A NAND based debouncer is shown in Fig. 3b. Build this circuit and show that it works as you expect. (Can you explain how it works? Is the switching clean? Is it fast?) Don’t take the circuit apart, we’ll need it for the next exercise. 3.4 Divide-by-Two with D Flip-Flop The 74LS74 circuit, shown in Fig. 4, contains two independent positive-edge clocked D flip-flops. In these flip-flop circuits, the data input at D is passed to the output Q (and as inverted signal to the complement Q̄) whenever the clock signal at CLK makes a transition from low to high. Thus Q only changes when CLK makes a positive transition. For normal operation the SET and CLR inputs must be held high. a) Connect the output of the debounced switch to the clock input CLK, as shown in Fig. 5a. Verify (and report) that the input state of D, for both low and high inputs, can be passed only for positive Physics 331, Fall 2008 Lab VI - Exercises 4 7474 +5V 2CLR 13 14 2D 12 2Q 8 2Q 2CLK 2SET 11 10 9 VDD D CLR CLK SET D Q Q CLR Q CLK Q SET VSS 1 2 1CLR 1D 4 3 1CLK 1SET 6 1Q 5 1Q 7 Top View Figure 4: 74LS74: Dual D Edge-Triggered Flip-Flop going clock signals. Is Q̄ the complement of Q? b) Make a divide-by-two circuit as shown in Fig. 5b. Using the debounced switch check the operation. Does it work as expected? Now, disconnect the debounced switch from the clock and drive the clock with the “sync out” square wave from your signal generator at about 10 kHz. Observe the clock signal and the output simultaneously on the scope. c) Make a divide-by-four circuit by appropriately wiring two D-flip-flops. Demonstrate that your circuit works. To explain how the final output at one-fourth the input frequency is produced, record one-by-one the input signals and output signals and use these observations to sketch a ”timing diagram” (for an example see Simpson pg. 625) . Don’t take the circuit apart, we’ll need it for the next exercise. a) +5 V b) +5 V CLR +5V or 0 V CLR Q D to LED 74LS74 from Debouncer SET +5 V OUT 74LS74 Q CLK Q D to LED IN Q CLK SET +5 V Figure 5: a) Set-Reset to test 74LS74 Flip-Flop b) Divide-by-Two with D Flip-Flop Physics 331, Fall 2008 3.5 Lab VI - Exercises 5 Multiplexers A multiplexer is the electrical analog of a rotary mechanical switch. It allows one to select one of several input lines and connect it to the output. A demultiplexer does the reverse, it allows one to route an input to one of many output lines. Digital electrical multiplexers are unidirectional and one has to buy different IC chips for multiplexing and demultiplexing or purchase integrated chips with both capabilities. These latter IC chips are also simply called multiplexers. Such circuits are essential in many applications. For example in digital communication applications, the data that is to be transmitted is often represented by eight bits (= “byte”) and it needs to be send over a single wire, i.e. the byte must be sent one-bit at a time. This general problem is called parallel-to-serial conversion and is solved electronically by a multiplexer. There are also analog electrical multiplexer, which are typically bidirectional, allowing current flow in either direction. In this lab you will explore the operation of the 4051 analog electrical multiplexer (analog MUX). The 4051 is a single 8-Channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input (see Fig. 6). The three binary signals (A, B, C) select 1 of 8 channels IN/OUT IN/OUT to be Pinouts turned on, and connect 1 5 5 5 one of the 12 0 12 3 8 outputs to the input. X CHANNELS 11 A INH 6 a) INH 6 CD4051B (PDIP,VEE CDIP, SOIC, TSSOP) 10 B 7 TOP VIEW 9 C V 8 b) SS 4 1 16 VDD 6 2 15 2 COM OUT/IN 3 14 1 7 4 13 0 CHANNELS IN/OUT CHANNELS IN/OUT 5 5 12 3 INH 6 11 A VEE 7 10 B VSS 8 9 C INHIBIT INPUT STATES V 8 SS C CD4053B (PDIP, CDIP, TSSOP) CD4051BY CHANNELS TOP VIEW 0 16 VDD bx 2 IN/OUT IN/OUT CHANNELS 0 0 ax OR ay 14 OUT/IN Y CHANNELS cy 3 OUT/IN CX OR CY 4 0 ay 13 IN/OUT CX 5 12 0 ax INH 6 11 A VEE 7 10 B VSS 8 9 C IN/OUT 1 B † 10 † 9 † 1 14 1 3 40 1 5 INH 6 3 0 4 12 0 11 3 0 1 5 1 0 6 0 1 1 1 7 1 TSSOP) X CD4053B (PDIP, CDIP, TOP VIEW CD4052B X X None VEE 7 VSS 8 CD4051B CHANNEL IN/OUT 7 4 016 VDD 6 5 4 3 2 B 0 10 A 9 B 1 0 0 0x, 0y 1 1x, 1y 014 OUT/IN ax1 OR ay 0 TG 2x, 2y OUT/IN CX OR CY 4 013 ay 1 3x, 3y IN/OUT CX 5 112 ax X None LOGIC LEVEL CONVERSION 1 TG IN/OUT X TG CD4053B 11 A INHIBIT A OR B OR C 0 0 10 B VBINARY EE 7 TO VSS 1 OF 88 DECODER WITH INHIBIT 0 9 C 1 1 X 7 7 VEE 4 6 2 † All inputs are protected by standard CMOS protection network. 5 5 4 1 COMMON OUT/IN TG ay or by or cy ax or 3 bx or cx None TG CD4051B TG CHANNEL IN/OUT 8 16 VSS VDD TG TG X = Don t Care 6 X CHANNELS IN/OUT A bx0 OR 5015 1 OUT/IN 12 15 14 by 13 2 X CHANNELS IN/OUT 2 13 COMMON “X” OUT/IN 1 1 Functional Block Diagrams INH 31 1 INH 6 C 16 VDD 0 15 2 2 20 0 cy 3 † 0 “ON” CHANNEL(S) 0 IN/OUT 16 VDD bx 2 A 1 0IN/OUT 1 INHIBIT 11 A IN/OUT CDIP, TSSOP) TOP VIEW 9 B 10 A 0 1 0COMMON0 “Y” OUT/IN 0 15 OUT/IN bx OR by by 1 c) B IN/OUT 0 0 by 1 Functional Block Diagrams 11 3 TRUTH TABLES (PDIP, VEE 7CD4052B 3 12 2 15 1 14 0 13 TG Figure 6: The 4051 analog multiplexer: a) pinout diagram, b) truthtable, c) function block diagram. (Adapted from 4051 datasheet [1]) TG 2 A † 11 TG B C † † 10 9 LOGIC LEVEL CONVERSION BINARY TO 1 OF 8 DECODER WITH INHIBIT TG TG TG COMMON OUT/IN 3 Physics 331, Fall 2008 Lab VI - Exercises 6 Control of analog signals up to 20 Vpp can be achieved by digital signals, if the digital signal amplitudes are at least 4.5V. More precisely, if the digital supply voltage range is larger 4.5 V (VDD − VSS > 4.5 V), then analog output swings are possible with amplitudes set by the supply voltage range VDD − VEE and VDD − VEE ≤ 20 V. The advantage of analog multiplexers is that they have a low ON impedance and very low OFF leakage current. In this lab you will use an analog multiplexer to build a digitally controllable amplifier. This is a very useful circuit because in many measurement applications the gain of the input circuitry has to be adjusted depending on the amplitude of the incoming signal in order avoid clipping of the amplified output signals (oscilloscopes are an example). a) On resistance: Measure the On-resistance of output channel 3 of the 4051 analog MUX. For a possible approach recall last week’s lab, where you determined the on-resistance of the 4066 analog switch. Note that you need to connect VDD to 5V, VSS and Inh to ground, and you need to set the input bits (A, B, C) such that output-channel 3 is selected. You may connect VEE to ground or -15V. Does your result agree with the datasheet? b) Analog voltage range: Connect VDD to 5V and VSS , Inh, and VEE to ground. Pick the input bits (A, B, C) such that output channel 3 is selected. Use a 411 opamp to implement a unity gain buffer. Connect the buffer’s output to the “Analog In” channel of the multiplexer and the buffer’s input to the function generator (Tektronix CFG 280). For a sinusoidal input wave, measure the multiplexer output (channel 3). What is the output voltage range? Does this agree with you expectations? How can you change your circuit to increase the output voltage range? Do it and quantify the result. c) Digital Gain Control: Rewire the 411 opamp used for the unity gain buffer and build the inverting amplifier with digital gain control shown in Fig. 7. (Note that VEE = - 15V). Pick the resistances R0-R3 such that gains of one, two, three, and four are achieved. Test your circuit and discuss the result. (Does it work as expected? Are there potential issues with this circuit?) You may test the circuit, for example, by connecting the MUX’s digital-inputs A and B to the input line (CLK) and output line (Q) of the divide-by-two circuit you constructed previously and by observing the amplifier output on the oscilloscope. Make sure you drive the divide-by-two circuit using square-waves with amplitudes in between 0 and 5 V. It is recommended that you use the sync-out signal of the signal generator and frequencies of around 100 Hz. Since a TTL gate (divideby-two circuit) is used to drive a CMOS gate (4051 MUX), difficulties may arise because the 3.5 V TTL output-high is barely high enough for CMOS logic. Therefore it is recommended to use a pull up resistor as shown in Fig. 7 before connecting to the A and B inputs of the CMOS 4051 MUX. References [1] CD4051B datasheet, Texas Instruments Incorporated, 2000. (Available, for example, from www. ee.washington.edu/stores/DataSheets/cd4000/cd4051.pdf.) Physics 331, Fall 2008 Lab VI - Exercises 7 +5V 20K r +5V Vin 10K Vout 10K 16 VDD 13 4051 MUX 0 R0 14 1 R1 15 2 R2 12 3 R3 Analog In 3 +5V +5V 1K Dig In to 5V CMOS TTL A 11 1 4 B 10 5 5 C 9 2 6 Inh 6 4 7 VEE VSS 7 8 −15V Figure 7: The 4051 analog multiplexer: “rotary control” type schematic of 4051 used to implement an inverting amplifier with digital gain control.