Download PPT

CSCI 2510
Computer Organization
Memory Addressing and
Assembly Instruction Basics
1
Part 1
Memory
2
Memory
 This lecture: focus on memory and addressing memory
 Revision: Main Memory (MM) consists of storage cells
 Arranged as bits (b)
 We can deal with them in n-bit groups called words
 Typically 8, 16, 32 or 64 bits
 Sometimes we use bytes which are 8-bits in length (B)
 1024=1K
 1024*1024=1M
 1024*1024*1024=1G
 Usually refer to memory size in bytes
 e.g. say, we have 512MB memory and rarely use words as the unit
3
Addresses
Use addresses to store or retrieve a single
item of information
For some k, memory consists of 2k unique
addresses which range from 0 – (2k-1)
The possible addresses are the address space
of the computer
e.g. 28-bit address  228 = 268435456 locations
Talk about word address: we use words
Talk about byte address: we use bytes
Talk about memory size: we use bytes/ sometimes bits
4
Quiz
 Given the information about the machine below
from Dell’s website, how many unique 32-bit
word locations does it have?
How many bits are there in the memory system?
What does the 2x512 mean?
Online Price HKD 5,899.00
Base System Dimension(TM) 9200 Intel(R) Pentium(R)
D915 Processor with Dual Core Technology
Memory 1GB (2x512) NECC Dual Channel DDR2 667MHz
SDRAM Memory
5
Byte addresses
Information quantities: bit, byte, word
1 Byte = 8 bits
Word typically varies 16-64 bits (the IA-32
architecture has 32-bit words which we will
assume from now on)
Intel Architecture, 32-bit
Most machines address memory in units of
bytes (byte-addressable)
Implies for a 32-bit machine, successive words
are at addresses 0, 4, 8, 12 …
6
Organization of memory
n bits
first word
second word
•
•
•
i th word
•
•
•
last word
7
More/ Less Significant Bytes
 Consider the hexadecimal (base 16) 32-bit number
12342A3F16
=1x167+2x166+3x165+4x164+2x163+10x162+3x161+15x160
=30540857510
 This 32-bit number has four bytes 12, 34, 2A, 4F
(4 bytes x 8 bits/byte = 32 bits)
 Bytes/bits with higher weighting are “more significant”
 e.g. the byte 34 is more significant than 2A
 Bytes/bits with lower weighting are “less significant”
 We also use terms “most significant byte/ bit” and “least significant
byte/ bit”
8
Big/ Little Endian
Two ways byte addresses can be assigned/
arranged across words
more significant bytes first (big endian)
e.g. Motorola
less significant bytes first (little endian)
e.g. Intel
9
Big/ Little Endian
What would 12342A3F16 look like in these two endianship assignments?
Word
address
Word
address
Byte address
Byte address
0
0
1
2
3
0
3
2
1
0
4
4
5
6
7
4
7
6
5
4
•
•
•
k
2 -4
k
2 -4
k
2 -3
•
•
•
k
2- 2
k
2 - 1
(a) Big-endian assignment
e.g. Motorola
k
2 - 4
k
2- 1
k
2 - 2
k
2 -3
k
2 -4
(b) Little-endian assignment
e.g. Intel
Assume k-bit address, 4-byte (32-bit) word
10
Word alignment
32-bit words align naturally at addresses 0,
4, 8 …
These are aligned addresses
Unaligned accesses are either not allowed
or slower, why?
e.g. read a 32-bit word from address 00000001
What about for 16- and 64-bit words?
11
Representing strings
All data so far (bits, bytes, words) are of
known length
How can we represent strings which could
be variable length?
e.g. the character string “University”?
12
Representing strings
 Method 1:
Use a null character to mark the end of the string, e.g. C
 ’U’, ’n’, ’i’, ’v’, ’e’, ’r’, ’s’, ’i’, ’t’, ’
y’, 0
 Method 2:
Use a separate number to represent the length, e.g. Pascal
 10, ’U’, ’n’, ’i’, ’v’, ’e’, ’r’, ’s’, ’i’, ’t’
, ’y’
 What are the pros and cons of them?
Say, length limit of the string, processing speed,
convenience in handling, etc.
13
Memory Operations
 Computer instructions serve to transfer and
manipulate data from memory
 Two operations
Load (read or fetch):
 processor sends address to memory,
 memory returns data e.g. R1 ← [LOC]
(assume R1 is an internal register in the processor)
Store (write):
 processor sends address and data to memory,
 memory overwrites location with new data e.g. [LOC] ← R1
14
Part 2
Instructions
15
Instructions
 Computer operates by executing a sequence of
instructions
 Machine instruction categories:
Data transfer between processor and memory
Arithmetic and logical operations on data in processor
Program sequencing and control
(i.e. branches, subroutine calls)
I/O transfers
16
Assembly language
 Three-address instructions:
 “opcode src1, src2, dst”, there are 3 operands
 e.g. “add a, b, c” means “c←[a]+[b]”
 Two-address instructions:
 “opcode src, dst”, some designs only use 2 operands
 e.g. “move a, b” means “b←[a]”
 e.g. “add a, b” means “b←[a]+[b]”
 Operand b is both a source and destination
 Note: some machines (e.g. Intel IA-32) put destination first
 e.g. “opcode dst, src”
 How do I compute “add a, b, c” on a two-address instruction
machine?
17
Assembly language:
One-address instructions
 In some machines, there is an implicit register
called an accumulator (A or ACC)
“add b” means “A←A+[b]”
“load b” means “A←[b]”
“store b” means “[b]←A”
 What are some of the advantages and
disadvantages of one-/ two-/ three-address
instructions?
Think in terms of power (instruction complexity) as well as
number of bits needed to specify all the operands
18
Registers
 Most higher end machines have a number of registers to store
temporary data in the processor




Transfers to/ from memory (i.e. Load/ Store) are relatively slow
Operations only involving registers are fast
High speed makes time to execute an instruction shorter
e.g. "opcode src, dst" format:
Load
A,R1
Load
B,R2
Mul
R1,R2
Store
R2,C
 In many computers (e.g. IA-32), at most one operand can be from
memory, and the other operands need to be in registers
 “Add x, y” and “Mov x, y” are not allowed on IA-32
where x and y are memory locations.
 Then, how would we do “Mov x, y” ?
19
Instruction execution
 Assume 32-bit words
 Memory is byte addressable
 Wish to compute “C←[A]+[B]”:
Move
Add
Move
A,R0
B,R0
R0,C
 The scenario follows…
20
A program in memory
• Memory holds words that
represent instructions
Begin execution here
• Program counter (PC) holds
address of instruction to be
executed next
• Processor control circuits fetch
and execute instruction pointed by
the PC
• Instruction fetch IR ← [PC]
Address
Contents
i
i+ 4
i+ 8
Move A,R0
Add B,R0
Program
segment
Move R0,C
A
B
Data for
the program
• Update PC = PC + 4
• Instruction execute – look at
IR and take the appropriate
action
C
Figure 2.8. A program for performing C  [A] + [B].
21
Adding n numbers
i
i +4
Move NUM1,R0
Move
N,R1
Add NUM2,R0
Clear
R0
i +8
Add NUM3,R0
•
•
•
LOOP
Program
loop
Determine address of
"Next" number, and
add "Next" number to R0
Decrement R1
i + 4n -4
Add NUMn ,R0
Branch>0
LOOP
i + 4n
Move R0,SUM
Move
R0,SUM
Which value > 0?
•
•
•
•
•
•
SUM
SUM
NUM1
N
n
NUM1
NUM2
•
•
•
NUMn
NUM2
•
•
•
NUMn
Straight line version
22
Loop version
Condition codes/ Flags
 In order to do special instructions such as conditional
branches/ jumps, many operations like arithmetic and logic
instructions implicitly set flags after execution
 Four commonly used (1-bit) flags
 N (negative flag)
 Z (zero flag)
 V (overflow flag)
 C (carry flag)
set to 1 if result is –ve; else 0
set to 1 if result is 0; else 0
set to 1 if arithmetic overflow occurred; else 0
set to 1 if carry out occurred; else 0
 E.g. "Add R1,R2" could affect any of these flags
 Give values for R1 and R2 for each case in the following slide:
(assuming they are 32-bit registers)
23
Condition codes/ Flags examples
 Set N (negative) to 1, Z to 0, V to 0, C to 0
R1 = 2, R2 = –5
 Set Z (zero) to 1, …
R1 = 10, R2 = –10
 Set V (overflow) to 1, …
R1 = 7FFFFFFF, R2 = 1
 Set C (carry) to 1, …
R1 = –2 (FFFFFFFE), R2 = 5
Not Overflow!
24
Condition codes/ Flags examples
 After Decrement R1, flags are set.
Decrement R1
 Branch>0 LOOP
Branch>0
LOOP
Move
R0,SUM
Which value > 0?
is equivalent to
if (N == 0 && Z == 0) Jump to LOOP
i.e. PC  LOOP
 I.e. After Decrement R1, if the result (new value in R1) is
larger than zero, Jump to LOOP
25
Summary
More about Memory Addressing and
Organization
Endianship and Word Alignment
Machine Instruction Formats
Instruction Execution and Condition Codes
26