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03/21/2016 System Bus Model Comp 255: Principle of Computer Organization ARC Instruction Set Architecture 1. ARC (A Reduced Instruction Set Computer) ISA Overview – based on SPARC (Scalable Processor Architecture) 2. Memory 3. CPU Instruction Set Architecture 4. Instruction Set 5. Functional vs. Physical/Implementation Point of View 6. ArcTools Simulator Reduces the number of interconnections between CPU and subsystems. ISA Level: View of computer that includes 1. Programmer-accessible hardware 2. Instructions that manipulate data within the hardware ARC Central Processing Unit (CPU) ARC Memory Byte addressable, 32-bit memory address space = 4Gigabytes 32-bit (4 byte) words addressable by low address byte Big-endian Byte Ordering Little-endian 33222222 22221111 111111 10987654 32109876 54321098 76543210 bit +--------+--------+--------+--------+ 00 01 02 03 byte where the “work” is done Data Section (data path) and Control Section (control unit) General Purpose Registers ←ARC Program Counter (PC) Instruction Register 33222222 22221111 111111 10987654 32109876 54321098 76543210 bit +--------+--------+--------+--------+ ←Intel 80x86 03 02 01 00 byte Memory access (word) is hard-aligned (all addresses end in 00) Memory Map: 0000 – 2047: used by O/S Data path = Registers ALU Buses 2048: user program space ↓ ← program code begins at 2048 0x0200 231-4: system stack bo;om ↑ 231 – (232- 4): memory mapped I/O space Fetch-Execute Cycle 1. Fetch next instruction from memory IR ← M[C(PC)] 2. Decode instruction 3. Fetch Operands 4. Execute Instruction (ALU) and Write Back Results 5. Repeat Instruction Types: data movement (load, store) arithmetic-logical control (i.e. conditional branching) miscellaneous ARC CPU & Registers 32 32-bit registers: %r0 - %r31 (%r0 = 0 i.e. hardwired to zero) %r14 = %sp = stack pointer; %r15 = link register 32-bit program counter %pc contains address of current instruction 32-bit program status register %psr: z (zero), n (negative), c (carry) and v (overflow) flags (compare with PDP-8 & HACK) trap enable/disable general purpose vs. specialized registers Trap/interrupt: an automatic subroutine call caused by an internal(trap) or external (interrupt) event which interrupts normal processing. Traps are usually calls to O/S to provide some service; interrupts are caused by external events. Exceptions: conditions that make further computation impossible (e.g. divide by 0) 1 03/21/2016 ARC as Load Store machine ARC is twos-complement representation machine All computations (e.g. Add/And) are done in registers; memory access restricted to load register from memory or store register to memory (compare with PDP-8 & HACK architectures) All instructions are word length (data flow left to right) ld [a], %r1 ld [b], %r2 add %r1, %r2, %r3 st %r3, [c] Mnemonic Meaning Memory Opcode 11 ld Load register from memory st Store a register to memory Call - Opcode 01 call Call Subroutine andcc Bitwise logical and (set control codes) Arithmetic/Logic Opcode 10 Fig 4-13 modified SETHI/Branch Opcode 00 ARC Instruction Set: Fig 4-16 (Code Formats) orcc Bitwise logical or orncc Bitwise a or not b (≠ nor) srl Shift right logical addcc Add (set control codes) jmpl Jump and link (return) sethi Load the 22 most significant bits of a register be Branch on equal bneg Branch on negative bcs Branch on carry bvs Branch on overflow ba Branch always Notes on Fig 4-13 4 instruction formats determined by opcode in bits 30-31 (compare with PDP-8) Instruction Types: Data Movement (Load/Store), Arithmetic/Logic, Control and Miscellaneous (e.g. SETHI) instructions Arithmetic/Logic instructions have two formats addcc %rs1, %rs2, %rd addcc %rs1, imm13, %rd ! Sign extend imm13 to 32 bits imm13 - Immediate mode (addressing) – operand is part of instruction (compare with PDP-8 and HACK) Load/Store instruction format (left to right dataflow): L1: ld [address], %rd or L2: st %rs1, [address] label is optional; direct addressing mode (compare with PDP-8) Point of View: Functional vs. Physical Implementation ARCTools Simulator Copy ArcTool07 folder to your Q:\ drive folder The same ISA feature can be examined/seen from two points of view: the functional as it appears to the assembly language programmer and the physical as it is actually implemented. Example: Functionally the PDP-8 instruction TAD X loads the accumulator with the contents at address X; however physically, effective address X can be computed one of two ways either using zero page addressing or current page addressing. Is this one addressing mode or two? Q:\Computer Science\Classes\Comp255Sp16\...\ArcTools07\ArcToolsv2.1.2.jar 2