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EXAMPLE 7.1 BJECTIVE Determine the total bias current on an IC due to subthreshold current. Assume there are 107 n-channel transistors on a single chip, all biased at VGS = 0 and VDS =2 V. Assume Isub = 10-10 A for each transistor for this bias condition and for a threshold voltage of VT = 0.5 V. What happens to the total bias current on the IC if the threshold voltage is reduced to VT = 0.25 V, all other parameters remaining the same. Solution The total bias current is the bias current of each transistor times the number of transistors, or IT = Isub(107) = (10-10)(107) 1 mA We can write so 10 10 VGS VT I sub I 0 exp Vt 0 0.5 I 0 exp I0 0.0259 0.0242 Now, if the threshold voltage changes to VT = 0.25, then the subthreshold current at VGS = 0 becomes I sub or VGS VT I 0 exp Vt 0 0.25 0.0242 exp 0.0259 Isub = 1.56 106 A Now, the total bias current for this IC chip would be IT = (1.56 10-6)(107) = 15.6 A Comment This example is intended to show that, taking into account subthreshold currents, the threshold voltage must be designed to be a “reasonable” value such that the zero-bias gate currents are not excessive. EXAMPLE 7.2 OBJECTIVE To determine the effect of channel length modulation on the value of drain current. Consider a n-channel MOSFET with a substrate impurity doping concentration of Na = 2 1016 cm-3, a threshold voltage of VT = 0.4 V, and a channel length of L = 1 m. The device is biased at VGS = 1 V and VDS = 2.5 V. Solution We find that Fp and Na Vt ln ni 2 1016 0.0259 ln 0.365V 10 1.5 10 VDS(sat) = VGS VT = 1 0.4 = 0.6 V Now 211.7 8.85 10 14 L 19 2 1016 1.6 10 or We can write or Comment 1/ 2 0.365 0.6 2.5 0.6 0.365 0.6 L = 0.181 m ID L 1 ID L L 1 0.181 ID 1.22 ID Due to channel length modulation, the drain current is 22 percent larger than the ideal long channel value. EXAMPLE 7.3 OBJECTIVE To calculate the effective electric field at threshold for a given semiconductor doping. Consider a p-type silicon substrate at T = 300 K and doped Na = 3 1016 cm-3. Solution From Equation (6.8b) in Chapter 6, we can calculat and Na 3 1016 0.376V Fp Vt ln 0.0259 ln 10 1.5 10 ni 1/ 2 1/ 2 4 s Fp 411.7 8.85 10 14 0.376 xdT eN 1.6 10 19 3 1016 a which is xdT = 0.18 m. Then max QSD 8.64 108 8.34 104 V/cm 14 11.7 8.85 10 At the threshold inversion point, we may assume that Qn = 0, so the effective electric field from Equation (7.10) is found as eff 1 8.64 10 8 4 max QSD 8 . 34 10 V/cm 14 11.7 8.85 10 s Comment We can see, from Figure 7.10, that this value of effective transverse electric field at the surface is sufficient for the effective inversion charge mobility to be significantly less than the bulk semiconductor value. EXAMPLE 7.4 OBJECTIVE To determine the ratio of drain current under the velocity saturation condition to the ideal longchannel value. Assume an n-channel MOSFET with a channel length L = 0.8 m, a threshold voltage of VT = 0.5 V, an electron mobility of n = 700 cm2/V-s, and vsat = 5 106 cm/s. Assume that the transistor is biased at (a) VGS = 2 V and (b) VGS = 3 V. Solution We can write ID v ,sat ID ideal vsat 2 0.8 10 4 5 10 6 n VGS VT 700 VGS 0.5 2L For (a) VGS = 2 V, we find and for (b) VGS = 3 V, we obtain Comment ID v ,sat ID ideal ID v ,sat ID ideal 0.762 0.457 We see that as the applied gate-to-source voltage increases, the ratio decreases. This effect is a result of the velocity saturation current being a linear function of VGS VT , whereas the ideal long-channel current is a quadratic function of VGS VT . EXAMPLE 7.5 BJECTIVE Calculate the threshold voltage shift due to short-channel effects. Consider an n-channel MOSFET with Na = 5 1016 cm-3 and tox = 200 Å. Let L = 0.8 m and assume that rj = 0.4 m. Solution We can determine the oxide capacitance to be Cox ox 3.98.85 10 14 7 2 1 . 73 10 F/cm tox 200 10 8 and can calculate the potential as Fp Na 5 1016 0.0259 ln 0.389V Vt ln 10 1.5 10 ni the maximum space charge width is found as 1/ 2 xdT 4 s Fp N a eN a 411.7 8.85 10 14 0.389 0.142m 19 16 1.6 10 5 10 Finally, the threshold voltage shift, from Equation (7.22), is VT or 1.6 10 5 10 0.142 10 0.4 19 4 16 1.73 10 7 20.142 1 1 0 . 8 0 . 4 VT = 0.101 V Comment If the threshold voltage of this n-channel MOSFET is to be VT = 0.40 V, for example, a shift of VT = 0.101 V due to short-channel effects is significant and needs to be taken into account in the design of this device. EXAMPLE 7.6 OBJECTIVE Design the channel width that will limit the threshold shift because of narrow channel effects to a specified value.. Consider a n-channel MOSFET with Na = 5 1016 cm-3 and tox = 200 Å. Let = / 2. Assume that we want to limit the threshold shift to VT = 0.1 V. Solution From Example 7.5, we have Cox 1.73 107 F/cm 2 xdT 0.142m and From Equation (7.28), we can express the channel width as W or eN a x Cox VT 2 dT 5 10 0.142 10 4 2 1.73 10 7 0.1 1.6 10 19 16 2 W = 1.46 m Comment We can note that the threshold shift of VT = 0.1 V occurs at a channel width of W = 1.46 m, which is approximately 10 times larger than the induced space charge width xdT . EXAMPLE 7.7 BJECTIVE Calculate the theoretical punch-through voltage assuming the abrupt junction approximation. Consider an n-channel MOSFET with source and drain doping concentrations of Nd = 1019 cm-3 and a channel region doping of Na = 1016 cm-3. Assume a channel length of L = 1.2 m, and assume the source and body are at ground potential. Solution The pn junction built-in potential barrier is given by Na Nd Vbi Vt ln 2 n i 1016 1019 0.0259 ln 0.874V 10 2 1.5 10 The zero-biased source-substrate pn junction width is 1/ 2 xd 0 2 s Vbi eN a 211.7 8.85 10 14 0.874 0.336 m 19 16 1.6 10 10 The reverse-biased drain-substrate pn junction width is given by 2 s Vbi VDS xd eN a 1/ 2 At punch-through, we will have xd 0 xd L or 0.336 xd 1.2 Which fives xd = 0.864 m at the punch-through condition. We can then find 2 4 2 19 16 Vbi VDS 5.77V xd eN a 0.864 10 1.6 10 10 14 2 s 211.7 8.85 10 The punch-through voltage is then found as VDS = 5.77 0.874 = 4.9 V Comment As the two space charge regions approach punch-through, the abrupt junction approximation is no longer a good assumption. EXAMPLE 7.8 BJECTIVE Design the ion implant dose required to adjust the threshold voltage to a specified value. Consider an n-channel MOSFET with a doping of Na = 5 1015 cm-3, and oxide thickness of tox = 500 Å, and an initial flat-band voltage of VFBO = 1.25 V. Determine the ion implantation dose such that a threshold voltage of VT = +0.70 V is obtained. Solution We may calculate the necessary parameters as Fp0 Na Vt ln ni 5 1015 0.0259 ln 10 1 . 5 10 0.329V 1/ 2 14 4 s Fp 0 411.7 8.85 10 0.329 0.413m xdT 0 19 15 eN a 1 . 6 10 5 10 ox 3.9 8.85 10 14 8 2 Cox 6 . 9 10 F/cm tox 500 10 8 1/ 2 The initial pre-implant threshold voltage is VT 0 VFBO 2 Fp0 eN a xdT 0 Cox 1.6 10 5 10 0.413 10 1.25 20.329 19 4 15 6.9 10 8 0.113V The threshold votage after implant, from Equation (7.31), is so that eDI VT VT 0 Cox 1.6 10 D 0.70 0.113 19 I 6.9 108 Which gives DI = 3.51 1011 cm2 If the uniform step implant extends to a depth of xI = 0.15 m, for example, then the equivalent acceptor concentration at the surface is DI 3.511011 16 -3 Ns Na 2 . 34 10 cm xI 0.15 10 4 or Ns = 2.84 1016 cm3 Comment The required implant dose to achieve the desired threshold voltage is DI = 3.51 1011 cm-2. This calculation has assumed that the induced space charge width in the channel region is greater than the ion implant depth xI. We can show that this requirement is indeed satisfied in this example.