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Transcript
QIE10P5 status
1. Digital power-up issue
2. New: power sequencing issue
3. Suggested strategy for impedance issue
4. Submission plans
Tom Zimmerman
7/3/13
1. Digital power-up issue
At the last meeting, I pointed out a possible ADC encoder bus contention problem, which results in excess
supply current upon power-up. I have redesigned the ADC latch as proposed, run simulations, and modified the
layout.
Ck
Power-on-resetb
Differential flash ADC
latch
SIG in
REF in
+
_
1
+
_
1
+
_
1
compare
latch
Ckb
Ck,Ckb
latch
Changed this
63
6
encoder
I
+
_
0
+
_
0
A “1100” transition
is encoded
0
to that
Working on the digital power-up issue exposed another issue: power sequencing. This was NOT an issue
with QIE8, since QIE8 was a single-supply device. QIE10 requires two separate supplies: 3.3V and 5V. Prior
to thinking about the digital power-up issue, I had not considered the impact of powering up one supply
before the other one.
The situation is as follows: if one supply is powered up and the other is still at 0V, then in multiple areas of
the chip, certain bipolar transistor voltage ratings are exceeded. In addition, extra current flows from the
powered supply into the unpowered supply pin. On the prototype, this has no disastrous effect. However, it
can result in long-term reliability issues. This is NOT acceptable.
IDEALLY, each supply should be completely independent and either could be powered up or down before the
other WITHOUT exceeding any transistor voltage ratings.
I have identified all areas (>10!) in which this problem exists and have made appropriate design
modifications. The changes have been implemented in the layout. None of these changes are major, but
given the number and extent of the changes, I think that another prototype submission is required. A QIE11
prototype submission could in principle verify all the power-up related design changes.
Some thoughts on the impedance matching issue
It would be preferable to NOT have to program the impedance of each and every chip.
The two sources of impedance variation that we cannot avoid are:
A. Cable-to-cable variation (measured to be up to 3% across one bunch of 24 cables)
B. QIE input impedance variation with signal amplitude:
De-biasing problem
worst in this range
We want to avoid signal reflections, especially large opposite-sign reflections that would de-bias the
QIE for many buckets.
Possible strategy:
Natural increase in impedance helps
to avoid opposite sign reflections for
moderately big signals
Use modified bias: lower power,
better impedance profile.
Set this impedance with
0.1% external resistors.
Set to slightly > 50 ohms to avoid
possible opposite sign reflections
for the biggest signals.
Or, set to exactly 50 ohms and
tolerate occasional de-biasing due
to infrequent biggest signals.
Region 1
Impedance determined
by feedback amp bias:
Rsetp, supply voltage,
temperature, MOS Vth.
Region 2
Impedance determined
only by external resistors
Impedance mismatch doesn’t matter so much in Region 1
since signals are too small to de-bias the QIE. Either
tolerate possible mismatch, or program the QIE Region 1
impedance to match the cable. Easy to adjust this
impedance with an added DAC.
Minimize the impedance variation in
Region 1 with an improved biasing scheme:
Present scheme
Improved scheme
Feedback
amp bias
Internal
Isetp DAC
External
Rsetp
Default
Current
=0
Eliminate this DAC. Originally
intended to allow Region 1
impedance tweaking, but not an
efficient way to do that.
Vbandgap (generated
on-chip) = 1.7V
Temperature
compensation
External
Rsetp
Insensitive to Vsupply,
temperature, MOS Vth.
Chip pinout does not change,
only external resistor value.
Internal
Iclamp
DAC
An efficient way to adjust
Region 1 input impedance.
Leave it at the default or
choose to program it.
Submissions
MOSIS submission dates: 8/26 and 11/11.
As of now, the power-up and power sequencing changes have been implemented in a QIE10P5_mod directory. The
suggested changes for the impedance issue are not implemented.
The QIE11 front end (if shown to work) could be stitched into the QIE10P5_mod layout. This would verify all the powerrelated design changes. Not known if this could be done in time for an August submission – depends on QIE11 front-end
testing (starting now). What QIE11 shunt factors are desired?? Not sure yet what is achievable. Preliminary results: the
QIE11 prototype is alive and functioning in X1 mode.
If QIE11 submission is not possible in August, then should we submit a QIE10 (with impedance design changes implemented)??