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LARC 研究群 – 晶片驗證實驗室
LARC – VLSI Verification Lab.
指導老師：清華大學電機系 黃錫瑜 副教授
辦公室: 資電館 818 室 E-mail: [email protected]
Research Topics At a Glance
(1) Fault Diagnosis Tool Development for Logic IC’s
Problem of Fault Diagnosis
Our research is mainly in the areas of VLSI design,
Testing, and Electronic Design Automation (EDA).
(1) For VLSI design, we focus on Nanometer SRAM
design and CMOS image sensor design.
(2) For VLSI testing, we are working on Built-In
Speed Grading (BISG) and fault diagnosis
(3) For EDA, we are developing tools for
efficient average and peak power estimation
A New Paradigm for Scan Chain Diagnosis
Fault diagnosis is to locate the defects in a
failing IC. It is an important pre-processing
step to guide the failure analysis process of
an IC so as to improve the manufacturing yield.
Scan chains have been popularly used as the
channels for silicon testing and debugging. We
have developed a more versatile model-free
paradigm for locating the faulty flip-flops in a
scan chain by a number of signal processing
techniques, such as filtering and edge detection.
expected response
Circuit
Model
EDA
Tools
VLSI Design
Limitations of Existing Methods


test patterns
not equal !
=


Our contributions


faulty response
CMOS
Image Sensor
Design
Nanometer
SRAM
Design
Power
Estimation
BISG
& Fault
Diagnosis
(1) More or less bound to certain fault models
(2) Not suitable for bridging faults
(3) Not suitable for intermittent faults


a chip with defects inside

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Question: Where are the fault locations ?
Use signal processing techniques
Free of fault models
Good for stuck-at, transition, bridging, etc.
Works well when the fault is intermittent
Can be applied to hold-time faults
(2) Power Estimation for Complex Logic IC’s
The power estimation is to predict the power consumption of an IC. It is important for battery lifetime estimation, thermal analysis for packaging and
signal integrity analysis. Existing methods for power estimation have certain limitations such as inadequate accuracy and/or too time-consuming. In
this research, we have developed an integrated prototype system consisting of two sub-program:
(1) ToggleFinder: which can calculate the total switching activities inside a given RTL code without time-consuming gate-level simulation.
(2) PowerMixer: which can translate a certain amount of switching activities derived by ToggleFinder to a real power dissipation value.
Jointly, these two program can solve the power estimation problem accurately and efficiently.
Power Estimation Problems for an IC
Our Methodology from the Register-Transfer Level
Chip
RTL Code
RTL Simulation
Results
quick synthesis
ToggleFinder
Analog
Components
Logic
Sub-systems
3.82 %
Embedded
Memories
netlist
Toggle count
Static or
Logic Simulation
Feasible
Inaccurate
Quick SPICE
Model-Based
Too slow
Feasible
(3) Built-In Self Repair Scheme for
CMOS Space Image Sensor
The image sensor serves as the optical front-end
of a digital camera that captures frames of images
as electronic signals inside the chip.
A space sensor requires the integration of multiple dies
 There could be die-to-die misalignment!
Die-to-Die Misalignment is hard to resolve physically
Yet it is easy to overcome by our built-in self-repair scheme,
which requires only 2.43% area overhead.
A line sensor of 12500 pixels
Sensing area of 2500 pixels
 Problem: There are gaps between dies
Horizontally aligned sensor
 vertical misalignment exists!
PowerMixer
schematic
or even layout
Total power
(4) Nanometer SRAM Design
In an SRAM circuit, the leakage currents on the bit lines are getting
more and more prominent with the dwindling of transistors’ threshold
voltages as the technology scales down to 90 nm or below. Excessive
bit-line leakage current not only results in slower read operations but
also could lead to functional failure.
We developed a new technique, named X-calibration, to combat this
phenomenon. Unlike the previous method that attempts to compensate
the leakage current directly, we first transform the bit-line leakage
current into an equilibrium offset voltage across the bit-line pair, and
then simple circuitry is utilized to cancel this offset accurately.
Experiments show that this X-calibration scheme can handle much
higher bit-line leakage current than the previous direct current
compensation scheme.
Row decoder
ADC & control ADC & control ADC & control ADC & control ADC & control
3%
Simulation for an 32x32 SRAM macro
Cell current, Icell, is 150 uA;
Extra bit-line capacitive loading, CBL, is 200fF
Cell array
2
Calibration circuitry
IO circuitry
ADC & control
ADC & control
ADC & control
ADC & control
ADC & control
cell expansion
or physical design
Access time (ns)
SPICE
Quick SPICE
Simulation
Column decoder
Control &
Input buffer &
Row address buffer
Conventional
1.9
1.8
1.7
X-calibration scheme
1.6
1.5
Output buffer &
Column address buffer
0
100
200
300
400
Bit-line leakage current (uA)
500