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IC Design Research Laboratory A Case Study: Design of a CMOS ASIC For Pulse Shape Discrimination Dr. George L. Engel Department of Electrical and Computer Engineering Southern Illinois University Edwardsville ANSiP Acireale, Italy November 21 – 24, 2011 1 IC Design Research Laboratory Introduction This talk will discuss the design flow of a CMOS ASIC (Application Specific Integrated Circuit), from modeling of the integrated circuit (IC) at the system level to tapeout. The presentation will be in the form of a case study. 2 IC Design Research Laboratory ug V(t) [c urre nt thro Design Conception A h a loa d R] Sa mple Integra tion gates B C Detector Physicists identify need for ASIC Ga te control WA DB WB DA WC DC Physicists describe how IC is to operate. VME Physicists describe how IC will be used in a larger system. OR IC designers determine appropriate technology and obtain Cadence process design kit (PDK) from foundry. PSD Integrator Chip External logic A BC T Multiplexed with other chips and sent to 4 channels of one VME Pipeline ADC Ca ble C F D D E L A Y IC Design Research Laboratory The Team Southern Illinois University Edwardsville: Dr. George Engel (professor / analog designer) Michael Hall (graduate student / behavioral simulation / system designer) Justin Proctor (graduate student / electrical simulation) Dinesh Dasari (graduate student / analog layout ) Nagendra Sai Valluru (graduate student / digital layout) Washington University in St. Louis: Dr. Lee Sobotka (professor / project manager / CEO / CFO) Jon Elson (electronics specialist) Dr. Robert Charity (researcher / end-user) Rebecca Shane (graduate student / test engineer) IC Design Research Laboratory Pulse Shape Discrimination t0 Event t1 t2 StartInt t4 StopInt DUMP INT-x t3 t5 StartInt Event Dx DUMP Delay Generator Delay Generator Start Start Out Control Wx Out StopInt INT-x Control DUMP Where X = A, B, C Resistor Array INT-x 10 pF Input from Detector 3 DAC DAC Setting Control OPAMP Out AGND SUB CHANNEL Integrator Output IC Design Research Laboratory Phases of Development Top-Down System Level Design and Verification Electrical Level Design and Verification Physical Layout and Verification Final Design Verification and Tapeout Fabrication Integration into a System Testing of Prototype System IC Design Research Laboratory System Level Design (Top-Down) TOP – DOWN Design Methodology Brainstorming! Define how the system is to operate. Simulate high-level behavior of system using MATLAB® Accurately model input signals and external environment (many parameters). Determine relationship between specifications for analog sub-systems and performance of overall system. Incorporate description of performance of sub-systems into the MATLAB simulation. MATLAB simulations should include description of input signal shape, gains, thermal/flicker noise sources, etc. Use Cadence Virtuoso® symbol and schematic ediitors to create hierarchial description of the design. Create VerilogA view for the various sub-system modules using specifications arrived at through MATLAB simulation. Cadence Hierachy Editor® allows one to select desired view. Testbench creation using a mix of Verilog and VerilogA modules Simulate noise-free system using Cadence AMS® mixed-signal simulator to ensure system operates as intended/specified. AMS uses ncsim® to simulate Verilog modules and either Spectre/MMSIM® or Ultrsim® used to simulate modules at the electrical level. Compare results of AMS simulation with those obtained using MATLAB® IC Design Research Laboratory Electrical-Level Design (Bottom-Up) Select module for implementation. Simulate using Cadence’s electrical simulator Spectre/ MMSIM 6.2 Choose appropriate circuit topology and draw transistor level schematic. Iterate until design meets specifications. Create MATHCAD® design sheet to determine device sizes and predict performance of selected module. Use a collection of OCEAN® scripts to automate the running of the simulator to test across all PVT corners of interest. Summarize results using Excel spreadsheet. Generate “datasheet” for module. Annotate schematic with device sizes. Replace VerilogA module with FET level schematic. All modules implemented? yes no IC Design Research Laboratory Physical Layout Select cell for layout Use Calibre for LVS (Layout Versus Schematic) verification Use Cadence Virtuoso® XL for layout along with pcell generators supplied in PDK (Process Design Kit) Use Calibre for PEX (parastic extraction) OR Simulate using Cadence’s electrical simulator Spectre®/MMSIM 6.2 Use Cadence VCAR (Virtuoso® Chip Assembly Router) for connecting modules together All cells layed out? Use Mentor Graphics Calibre® for design rule verification (DRC). yes no IC Design Research Laboratory Final Verification and Tapeout Use Cadence AMS® program to simulate entire IC at the electrical level. Can take several days! If simulations successful, continue else go back and fix the problem. Generally speaking there are few problems at this stage. Run DRC and LVS one last time! Generate GDSII file. Submit to MOSIS (MOS Implementation Services) Wait for 2 to 6 months for packaged parts to return. IC Design Research Laboratory The ASIC! IC Design Research Laboratory Integration Into a System Detector ASD 16 ch ASD Amplifier-Splitter-Delay OR Ind ivid ua l Linear Logic CFD - 32 PSD rts sta Extra logic Logic CB with 2 PSD8C Common stop MB with slots for 16 CB’s TABC To ADC IC Design Research Laboratory Prototype Testing Pulse Shape Discrimination Total pulse height information. IC Design Research Laboratory Questions ??? 14 IC Design Research Laboratory Timing permitting …. IC Design Research Laboratory Op Amp Used in Integrator IC Design Research Laboratory Use of MathCAD® The compensation capacitor should be chosen so that the we can ensure at least 60 degrees of phase margin. We can do this by making sure that the parasitic pole is at least 2.2 times greater in frequency than the GBW. We also need to make sure that the RHP zero introduced by the compensation capacitor is 10 times greater than the GBW. Capacitive Load: Unity gain frequency Parasitic pole frequency Zero introduced by comp cap CL 5pF u gmi p z gmo Cc Eqn (4) Eqn. (2) CL gmo Using (1) and (2) we can write gmi Cc 2.2 CL gmo Eqn. (1) Cc Eqn (3) IC Design Research Laboratory Use of MathCAD® Using (1) and (3) we write gmi 0.1 gmo Eqn (5) Using (5) in (4) we find that Cc can be found using Cc 0.22 CL Eqn (6) Compensation Capacitor 12 Cc 1.1 10 F If nested MIller compensation is used then the compensation capacitor can be made smaller. IF Cgs_out 0.5pF CM Cc Cgs_out THEN 15 CM 741.62 10 We need 60 MHz of GBW 6 GBW 60 10 Hz 81 u 2 GBW 3.77 10 s F IC Design Research Laboratory Excel Datasheet Ref Comments Type W L M I (µA) Theta Alpha gm (Mhos) Vds,sat M1 M2 M3 M4 Vds,sat+Vt A (um^2) Cin(pF) AF A est PFET input device PFET input device NFET input device NFET input device PFET PFET NFET NFET 50 50 50 50 9 9 30 30 2 2 2 2 5 5 5 5 7.5 7.5 6.8 6.8 0.34 0.34 0.36 0.36 4.40E-05 4.40E-05 4.58E-05 4.58E-05 0.168 0.168 0.165 0.165 1.17E+00 1.17E+00 1.17E+00 1.17E+00 M41 M39 Tail current for P-stage Tail current for N-stage PFET PFET 4.2 4.2 12.2 12.2 2 2 10 10 240.9 240.9 0.06 0.06 1.71E-05 1.71E-05 0.953 0.953 M11 M12 M13 M14 PFET mirror PFET mirror PFET cascode PFET cascode PFET PFET PFET PFET 5 5 12.5 12.5 6 6 0.6 0.6 2 2 2 2 15 15 10 10 149.3 149.3 4.0 4.0 0.08 0.08 0.43 0.43 3.27E-05 3.27E-05 1.11E-04 1.11E-04 M15 M16 M17 M18 NFET cascode NFET cascode NFET mirror NFET mirror NFET NFET NFET NFET 3.6 3.6 14.7 14.7 0.6 0.6 60 60 2 2 2 2 10 10 15 15 3.8 3.8 138.5 138.5 0.44 0.44 0.08 0.08 M31 M29 PFET mirror NFET mirror PFET NFET 4.2 2.4 12.2 21.6 1 1 5 5 240.9 203.5 M37 M36 PFET cascode voltage NFET mirror PFET NFET 4.2 2.4 12.2 21.6 1 1 5 5 M32 M30 PFET mirror NFET cascode voltage PFET NFET 4.2 2.4 12.2 21.6 1 1 M33 M23 M24 PFET mirror NFET diode NFET diode PFET NFET NFET 4.2 3 3 12.2 12 12 M21 M22 M38 PFET diode PFET diode NFET mirror PFET PFET NFET 4.2 4.2 2.4 M25 M38 PFET output FET NFET output FET PFET NFET M28 M27 Floating I Floating I M20 M19 Floating I Floating I Os (mV) OS/Vsat % 900.0 900.0 3000.0 3000.0 1.5 1.5 5 5 4 4 4 4 3600 3600 12000 12000 0.9 0.9 0.5 0.5 5.2E-01 5.2E-01 2.9E-01 2.9E-01 1.95E+00 1.95E+00 102.5 102.5 0.1708 0.1708 4 4 409.92 409.92 2.6 2.6 2.7E-01 2.7E-01 0.750 0.750 0.122 0.122 1.75E+00 1.75E+00 1.12E+00 1.12E+00 60.0 60.0 15.0 15.0 0.1 0.1 0.025 0.025 4 4 4 4 240 240 60 60 3.4 3.4 6.7 6.7 4.5E-01 4.5E-01 5.5E+00 5.5E+00 1.14E-04 1.14E-04 3.28E-05 3.28E-05 0.123 0.123 0.746 0.746 1.12E+00 1.12E+00 1.75E+00 1.75E+00 4.3 4.3 1764.0 1764.0 0.0072 0.0072 2.94 2.94 4 4 4 4 17.28 17.28 7056 7056 12.5 12.5 0.6 0.6 1.0E+01 1.0E+01 8.3E-02 8.3E-02 0.06 0.07 8.57E-06 9.03E-06 0.953 0.905 1.95E+00 1.90E+00 51.2 51.8 0.0854 0.0864 4 4 204.96 207.36 3.6 3.6 3.8E-01 4.0E-01 240.9 203.5 0.06 0.07 8.57E-06 9.03E-06 0.953 0.905 1.95E+00 1.90E+00 51.2 51.8 0.0854 0.0864 4 4 204.96 207.36 3.6 3.6 3.8E-01 4.0E-01 5 5 240.9 203.5 0.06 0.07 8.57E-06 9.03E-06 0.953 0.905 1.95E+00 1.90E+00 51.2 51.8 0.0854 0.0864 4 4 204.96 207.36 3.6 3.6 3.8E-01 4.0E-01 1 2 2 5 5 5 240.9 45.2 45.2 0.06 0.15 0.15 8.57E-06 1.91E-05 1.91E-05 0.953 0.426 0.426 1.95E+00 1.43E+00 1.43E+00 51.2 72.0 72.0 0.0854 0.12 0.12 4 4 4 204.96 288 288 3.6 3.1 3.1 3.8E-01 7.2E-01 7.2E-01 12.2 12.2 21.6 2 2 1 5 5 5 120.4 120.4 203.5 0.09 0.09 0.07 1.21E-05 1.21E-05 9.03E-06 0.674 0.674 0.905 1.67E+00 1.67E+00 1.90E+00 102.5 102.5 51.8 0.1708 0.1708 0.0864 4 4 4 409.92 409.92 207.36 2.6 2.6 3.6 3.8E-01 3.8E-01 4.0E-01 60 17.5 2 2 2 2 60 60 16.6 15.5 0.24 0.25 3.92E-04 3.92E-04 0.250 0.250 1.25E+00 1.25E+00 240.0 70.0 0.4 0.116667 4 4 960 280 1.7 3.1 6.7E-01 1.2E+00 PFET NFET 15 8.1 2 4.2 2 2 5 5 5.5 5.9 0.38 0.38 4.95E-05 4.84E-05 0.144 0.154 1.14E+00 1.15E+00 60.0 68.0 0.1 0.1134 4 4 240 272.16 3.4 3.2 2.3E+00 2.1E+00 PFET NFET 7.5 2.2 12 12 2 2 5 5 66.3 61.7 0.12 0.13 1.63E-05 1.64E-05 0.500 0.498 1.50E+00 1.50E+00 180.0 52.8 0.3 0.088 4 4 720 211.2 1.9 3.6 3.9E-01 7.2E-01 IC Design Research Laboratory VerilogA (Op Amp) module ota(vout, vref, vin_p, vin_n, vspply_p, vspply_n); input vref, vspply_p, vspply_n; inout vout, vin_p, vin_n; electrical vout, vref, vin_p, vin_n, vspply_p, vspply_n; parameter real gain = 3.0 ; parameter real freq_unitygain = 3.0e3; parameter real rin = 1e15 ; parameter real vin_offset = 0.0; parameter real ibias = 10e-6; parameter real iin_max = 10e-6; parameter real slew_rate = 2e6; parameter real rout = 1e12 ; parameter real vsoft = 0.0; real c1; real gm_nom; real r1; real vmax_in; real vin_val; electrical cout; IC Design Research Laboratory VerilogA (Op Amp) analog begin @ ( initial_step or initial_step("dc") ) begin c1 = (1/(3*gain)) * ibias/(slew_rate); gm_nom = 2 * `PI * freq_unitygain * (3 * gain * c1) ; r1 = gain / gm_nom; vmax_in = iin_max/gm_nom; end vin_val = V(vin_p,vin_n) + vin_offset; // // Input stage. // I(vin_p, vin_n) <+ (V(vin_p, vin_n) + vin_offset)/ rin; I(vref, vin_p) <+ 0.0 ; I(vref, vin_n) <+ 0.0 ; IC Design Research Laboratory VerilogA (Op Amp) // // GM stage with slewing // if (vin_val > vmax_in) I(vref, cout) <+ iin_max; else if (vin_val < -vmax_in) I(vref, cout) <+ -iin_max; else I(vref, cout) <+ gm_nom*vin_val ; // // Parasitic pole // I(cout, vref) <+ ddt(c1*V(cout, vref)); I(cout, vref) <+ V(cout, vref)/r1; IC Design Research Laboratory VerilogA (Op Amp) // // Output Stage. // I(vref, vout) <+ V(cout, vref) / r1 ; I(vout, vref) <+ V(vout, vref) / rout; // // Soft Output Limiting. // if (V(vout) > (V(vspply_p) - vsoft)) I(cout, vref) <+ gm_nom*(V(vout, vspply_p)+vsoft); else if (V(vout) < (V(vspply_n) + vsoft)) I(cout, vref) <+ gm_nom*(V(vout, vspply_n)-vsoft); end endmodule IC Design Research Laboratory VerilogA (Delay Generator) module delay_gen(start, Dx, dig_reset,ana_reset, capsel1, capsel0, cap_gnd VB_TC, VBN_DISC, AVDD, AVSS, SVSS); inout start, Dx, dig_reset, ana_reset, capsel1, capsel0, cap_gnd, VB_TAC, VBN_DISC, AVDD, AVSS, SVSS ; electrical start, Dx, dig_reset, ana_reset, capsel1, capsel0, cap_gnd, VB_TAC, VBN_DISC, AVDD, AVSS, SVSS ; parameter parameter parameter parameter parameter parameter parameter parameter real real real real real real real real Vth = 2.5 from (1 : 4) ; logic_low = 0 ; logic_high = 5 ; vscale = 1 ; gmi = 10e-6 ; tr = 1n ; tf = 1n ; vos = 1 from (0.5 : 2.5) ; IC Design Research Laboratory VerilogA (Delay Generator) real ramp_voltage, tscale, run_status, offset ; analog begin @(initial_step) begin ramp_voltage = 0 ; run_status = logic_low; end ; @(cross(V(start)>Vth)) begin offset = $realtime ; run_status = logic_high ; end ; if (V(vb_tvc) > 0.5) tscale = 500n ; else tscale = 2u ; IC Design Research Laboratory VerilogA (Delay Generator) if (V(dig_reset)>Vth) run_status = logic_low ; if (V(stop)>Vth) run_status = logic_low ; if (V(ana_reset) > Vth) ramp_voltage = 0 ; else if (run_status > Vth) ramp_voltage = vscale * ($realtime - offset) / tscale ; if (ramp_voltage > 4) ramp_voltage = 4 ; I(vb_tvc) <+ gmi * V(vb_tvc) ; V(tvc_out) <+ transition(ramp_voltage, 0, tr, tf) + vos ; end endmodule