Download DLL Considerations in QDRII/DDRII SRAMs

DLL Considerations in QDRII/DDRII SRAMs
This KB article provides an overview of the Delay Locked Loop (DLL) and describes the operation in DLL
disabled mode in QDRII/DDRII SRAMs.
Introduction
QDR™ SRAMs are a family of products defined and developed by members of the QDR Consortium, comprising
of Cypress, Renesas, IDT, NEC, and Samsung. The QDR SRAM family mainly consists of the QDRI/DDRI and
QDRII/DDRII. devices.One of the main improvements of QDRII/DDRII over the QDRI/DDRI devices is a wider data
valid window. The QDRII/DDRII has a 30% increase in the data valid window time. This is achieved by adding a DLL
to synchronize the output data to the input clocks. This KB article discusses the timing associated with the
DLL when it is disabled.
Overview of DLL in QDRII/DDRII
SRAMs
The main purpose of implementing a DLL on the QDRII/DDRII SRAMs is to place the output data coincident
with the rising edge of the input clocks—C and C clocks, if supplied, otherwise K and K clocks. Because the data is
so tightly controlled to the clocks, the first piece of data begins to output a half clock cycle later than the first
generation QDR.
Figure 1 shows this scenario for a read operation. Write operation is unaffected by the presence of DLL.
As illustrated in Figure 1, the tco for QDRII is very small compared to the tco on QDRI. Also, the hold times are
negative on QDRII. This means that the data bus goes invalid before the next rising edge of the inverted clock. An
insight into some internal details about DLL is required to understand this. For the sake of clarity, this application note
focuses only on the single clock domain. The same argument applies for C and Cb clocks.
DLL Timings when Enabled and
Disabled
During initial design, it is natural to run the system at lower frequencies, which makes data capturing easy. The DLL
on the SRAM can operate at a wide frequency range—from the designated frequency of the part to 120 MHz. To
operate the system below this frequency, DLL can be bypassed by strapping the DOFF (ball 1H) signal LOW.
When DOFF signal is tied HIGH, the DLL is enabled in this mode and the device operates with a read latency of 1.5
clock cycles. When the DLL is locked to a specific frequency in the range 120 MHz to the specified maximum clock
frequency, all the timings specific to the designated frequency of the part are valid. These timings are guaranteed by
design.DLL does not lock below the frequency of 120 MHz and the timings are no longer valid.
When DOFF signal is tied LOW, the DLL circuit is disabled. Table 1 shows the timings when the DLL is disabled.
Table 2 outlines the read latency of the different revisions of the QDRII device when the DLL is bypassed or disabled.
Refer to the respective device data sheets for timings with DLL enabled. The output timings differ significantly
between when the DLL is enabled and disabled. For instance, considering the 167 MHz frequency operation, the t co
is 0.5 ns and the tdoh is –0.5 ns when the DLL is locked,whereas they are 3 ns and 1.2 ns respectively when the DLL
is disabled or unlocked. These values are not tested and are guaranteed only by design. Clocking mode (single clock
or dual clock domain) has no effect on these timings.
DLL Constraints
There are some constraints for the DLL to work properly.Because the DLL uses either C or K as its synchronizing
input, the input clocks must have low phase jitter, which is specified as tKC. Phase jitter refers to the maximum
allowed value of variation from one rising edge to the next expected rising edge of the clocks. For example, if the
frequency is 167MHz, tCYC being 6.0 ns, from any rising edge of one clock,the next rising edge should occur between
5.9 ns and 6.1 ns later. If the next rising edge violates this specification too much, there is a possibility of the DLL
temporarily getting unlocked.The next constraint is the lock time. After the SRAM starts receiving stable input clocks,
it takes tKC lock(1024) clock cycles for the DLL to lock onto the incoming clock. It is recommended to have the voltage
supply ideally DC stable before supplying clocks to the SRAM so that the DLL locks accurately within the lock time of
1024 cycles. Also, the incoming clock should be stable for the DLL to lock onto the correct frequency. If the incoming
clock is unstable (varying frequency) and the DLL is enabled, then the DLL may lock onto a wrong frequency and this
is undesirable. If this is not possible, then the DOFF pin must be used to turn off the DLL. It can be turned it on when
the clock becomes stable. In this way, the DLL gets locked onto the correct frequency and within 1024 cycles.
There is also a constraint on the lower end of the frequency at which the DLL can operate, which is 120 MHz. All the
timings for that designated frequency on the part is guaranteed by design. Below 120 MHz, the DLL must be
disabled for correct operation with loose output timings, as shown in Table 1.
Lastly, the change in DC value of the power supply must be kept down to a minimum since the DLL may get affected
with instant changes in the power supply voltage.
Summary
This application note describes the operation of the DLL and the operation of the QDRII SRAM with the DLL enabled
or disabled. The possibility of operating the part down to 120 MHz with no performance hit is illustrated. The
application note also discusses a few constraints to be noted when operating with the DLL enabled.